JPS5847327A - Analog-to-digital converter - Google Patents

Abstract

PURPOSE:To improve the reliability of converted data as well as the S/N and at the same time to realize a reduction of cost, by performng an automatic gain control in response to the voltage level of an analog input signal. CONSTITUTION:A level detecting/controlling circuit 18, a variable resistance circuit network 20 and an operational amplifier 21 are added to various types of A/D converters. Thus automatic gain control is performed in accordance with the level of an analog input signal, and an A/D conversion is possible with high accuracy. As a result, the high reliability is maintained for a converted data. AT the same time, the S/N is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog-to-digital converter that performs automatic gain control in response to an analog input signal level and can perform analog-to-digital conversion with high accuracy.

Hereinafter, conventional problems will be explained using typical successive approximation type analog-to-digital converters and parallel processing type analog-to-digital converters as examples. The same applies to serial-parallel type analog-to-digital converters.

Figure 1 shows a configuration diagram of a conventional successive approximation type analog-to-digital converter, where 1 is an analog signal input terminal;
2 is a comparator, 3 is an analog-to-digital conversion start pulse input terminal, 4 is a successive approximation register, and 5 is a digital
A signal output terminal, 6 is a digital-to-analog converter, and 7 is a reference voltage input terminal for the digital-to-analog converter 6. When the number of converted bits of the analog-to-digital converter is n, the successive approximation register 4 has an n-pit configuration.

The operation of FIG. 1 is as follows. When a conversion start pulse is applied to the terminal 3, the most significant bit of the successive approximation register 4 temporarily becomes 1'' state.

The digital-to-analog converter 6 has a reference voltage input terminal 7
This circuit creates an analog voltage corresponding to the digital value of the successive approximation register 4 based on the voltage Vref input from 1”, 1/2F
The voltage of SR (FSR is full scale and indicates the maximum input voltage allowable range) is applied to comparator 2. Comparator 2
is the analog input voltage Vin from terminal 1 and the digital -
The output voltage of 1/2 FSR from the analog converter 6 is compared, and when Vin > 1/2 FSR, the most significant bit of the successive approximation register 4 is set to "1n" and the next (most significant - 1) Set the bit to '1' and Vin<1/2FS
When R, the most significant bit of successive approximation register 4 is set to 0''
and set only the next (most significant -1) bit to the "1" state. As a result, the digital-to-analog converter 6 outputs (1/2+174)F when Vin>1/2FSR.
SR, Vin (When 172FSR is used, an output voltage of 174FSR is obtained. Comparator 2
) Compare FSR or 1/4FSR and Vin again,
When Vin > (1/2 + 174) FSR, the highest position of successive approximation register 4,
) bit remains ``1'', and the next (most significant - 2nd) bit is set to ``1'' (2, Vin < (1/2 + 1/4
) For FSR, set the most significant bit to "'1", (
Set the most significant - 1) bit to 0# and then the next (most significant - 2)
Set the bit to “1”. Also, Vin > 174
For F SR, the most significant bit is 0'', (most significant - 1
) bit to 1'', then the next (most significant - 2) bit to 1'', and when Vin<1/4FSR, the most significant, (
The most significant -1) bits are all set to 0'', and only the next (most significant -2) bit is set to 1''. Thereafter, each bit of the successive approximation register 4 is sequentially changed from the most significant bit to '1# or @ until the analog signal input from terminal 1 and the output voltage of the digital-to-analog converter 6 match.
0# is set, and when a match occurs, the digital value of the successive approximation register 4 is sent out from the output terminal 5.

Figure 2 shows a configuration diagram of a conventional parallel processing analog-to-digital converter, in which 1 is an analog signal input terminal, 5 is a digital signal output terminal, 7 is a reference voltage input terminal, and 8 is an analog-to-digital converter. Conversion pulse input terminal, 9 is a resistance circuit, 10 is a comparison R< group, 11 is an encoder, 1
2 is a latch circuit.

As in the case of the first tooth, when n-bit analog-to-digital conversion is performed in FIG. Create 2n-1 different comparison voltages. The comparator group 10 consists of 2'-1 comparators, the 2n-1 comparison voltages created by the resistance circuit 9 are used as one input of each comparator, and the analog signal Vin of the input terminal 1 is used as the input for each comparison. Parallel (= is applied to the other input of the device, and comparison is performed simultaneously at the application timing of the pulse given to terminal 8. As a result, 20-1 high level and low level signals are output from the comparator group 10. The encoder 11 is
This is a circuit that converts the 2n-1 signals outputted from the comparator group 10 into n-bit binary codes in response to the high level and low level, and the converted n-bit digital signal is a child circuit. 12, output terminal 5
Sent from O, Ru.

By the way, these analog-to-digital converters quantize the output into a digital amount that increases directly or linearly with respect to the amplitude of the analog input signal, so for a low level input signal +'f It is difficult to obtain sufficiently good accuracy. That is, for example, if the input snow number of θ~5■ is 1
If conversion is performed using a 0-pit analog-to-digital converter, an accuracy of 0.1% can be maintained for 5■, but 2
, 5■, 0.2%, IV, Q, 5, and 0.5V, only 1% accuracy can be achieved. Therefore, even if a conventional analog-to-digital converter is used as is in a measuring instrument for measuring signals with a wide dynamic range, the converted digital data will have different accuracies.
The drawback is that the reliability of the data is lost. Additionally, modulators and demodulators have the disadvantage that the S/N (signal power to noise power ratio) of the signal deteriorates.

Therefore, an analog-to-digital converter has been proposed that performs automatic gain control in response to the level of an analog input signal. 3 and 4 show conventional examples of this type of analog-to-digital converter. Here, the third
The figure shows a first analog-to-digital converter 14 that converts and outputs the analog signal amplified by the variable gain amplifier circuit 13 into a binary code digital signal, and a first analog-to-digital converter 14 that converts the input analog signal into a binary code digital signal and outputs the analog signal amplified by the variable gain amplifier circuit 13. a second analog for setting the gain of the variable gain amplifier circuit 13;
A digital converter 15 is configured so that a full-scale analog input signal is always applied to the first analog-to-digital converter 14. Further, FIG. 4 shows a configuration in which an electronic computer 17 reads the digital signal converted by the analog-to-digital converter 16 and adjusts the gain of the variable gain amplifier circuit 13 according to the level of the digital signal converted by the analog-to-digital converter 16. A full-scale analog input signal is always applied to the

However, the configuration in Figure 3? uses two analog-to-digital converters, which increases cost and
Also, the configuration shown in Figure 4 requires faster calculation speed.
In order to eliminate these drawbacks, the present invention is difficult to say that it is an optimal configuration in that it places a burden on the soft signal. a level detection/control circuit that selects one of the plurality of output terminals according to the detected level and sends a control signal to the selected output terminal;
A variable resistance network is digitally controlled by the output signal of the level detection/control circuit, and an operational amplifier is added to obtain a voltage value proportional to the resistance value of the resistance network, corresponding to the analog input signal voltage level. The objective is to provide a new and inexpensive analog-to-digital converter that performs accurate analog-to-digital conversion while performing automatic gain control.
Details will be explained below with reference to the drawings.

FIG. 5 shows an embodiment in which the present invention is applied to a successive approximation type analog-to-digital converter (number of conversion bits is n), where 1 is an analog signal input terminal, 2 is a comparator, and 3 is an analog-to-digital conversion start pulse. Input terminal, 4 is successive approximation register, 5 is digital signal output terminal, 6 is digital-to-analog converter, 7 is digital-to-analog conversion reference voltage input terminal, 18 is signal level detection/control circuit, 19 is variable resistance circuit control No. output terminal, 20 is a variable resistance circuit network,
21 is an operational amplifier, and 22 is a constant current source.

In FIG. 5, the operations of comparator 2, successive approximation register 4, and digital-to-analog converter 6 are the same as in FIG. 1, and digital data determined in proportion to the analog input signal level is output to terminal 5. Ru. This digital data output is directed to a digital circuit (not shown) after the analog-to-digital converter, and m bits from the most significant bit (m≦n) are sent to a level detection/control circuit 18 for automatic gain control. is input. In the level detection/control circuit 18, first, the analog-digital conversion time (
The average level of the digital signal output during a time T that is an integral multiple of Ts (equal to the sampling period of the signal) is determined. The average level is calculated for each of the m bits from the most significant bit of the digital data output (two bits make a digital sum of T/Ts times, and if this sum is T/2Ts or more, it is the bit that is the best bit). If it is less than T, /2Ts, set the Needless to say, the variable resistance circuit that is the output terminal of the level detection/control circuit 18 follows an algorithm that selects a small resistance value when the analog input signal voltage is small, and selects a large resistance value when the analog input signal voltage is large. One of the control signal output terminals 19 is selected to send a voltage, and one of the switches in the variable resistance network is closed.

Variable resistance network 20 (selected resistance value is Rx)
The operational amplifier 21 and the constant current source 22 form a resistance voltage conversion circuit, and the reference voltage vrer at the digital-to-analog converter reference voltage input terminal 7 is V ref = Is
−Rx (1) given by (I
s is the current value of the constant current source). Therefore, when the analog input signal voltage is small, the reference voltage source voltage Vref becomes small, and when the analog input signal voltage is large, the reference voltage source voltage Vref becomes large.

On the other hand, the maximum allowable input voltage range FSR of the analog-to-digital converter is also proportional to the reference voltage source voltage Vref, and since there is a relationship between FSll= and -Vref (K is a constant) (2), the maximum input voltage is The voltage tolerance range FSR is determined by the following formula: FSR=KIs, x (3). Here, when the analog input signal voltage is small, Rx is set small, and conversely, when the input signal voltage is large, RX is set large, so PA
The value of IL is also determined following the voltage fluctuation of the analog input signal, and it becomes possible to perform analog-to-digital conversion of the analog input signal in a state always at F'SR or close to FSR.

Next, the above-mentioned process will be explained using a 3-pit successive approximation analogue device and a digital converter as examples, focusing on the procedure for setting the resistance value of the variable resistance network described above. This example mouth =
In this case, the digital output code is a binary code,
The upper two pins are used for level detection, and the variable resistance network can be set to three levels of voltage.

The configuration of the level detection/control circuit and the variable resistor C circuit network in this case is shown in Fig. 6 (2 shown. In Fig. 6, 18 is a signal line).The level detection/control circuit, 21 is an operational amplifier, and 22 is a constant current source. (I
s = lQ-3N), 23 to 25 are variable resistance circuit control signal output terminals, + is a switch connected to the variable resistance circuit control signal output terminal, and G is connected to each variable resistance circuit control signal output terminal. Switch, A is the switch connected to the variable resistance circuit control signal output terminal, 29 is the resistance value 2
, the resistance of Ω is added to the resistance value of 2, the resistance of Ω is added to the resistance value of 2, and 31 is the resistance of 4
32 is a digital output signal input terminal.

Now, let K in equation (3) be 1, and Is = 1O-3A
Considering that, equation (3) becomes FS = 10-3·R(4). Also, as mentioned above, the most significant bit and (most significant -1) bit are used to select the switch. FIG. 8 shows a method of selecting switches in the circuit of FIG. 6, and according to this method, voltage gain control is automatically performed. For example, if the average value of the analog input signal per second is 1.6V, the average value of the digital data output before automatic gain control is '001', but in the case of '001', the C2 , a switch selection control signal is sent from terminal 5, switch 4 is closed, and R
When x=2, it becomes Ω. When RX is set to 2Ω, the (
From formula 4), the input voltage I''SR is 2v, so the correspondence between the analog input signal and digital data output when the FSR is 2v as shown in Fig. 9 is established.
The digital data output becomes '110', allowing more accurate analog-to-digital conversion.

The following is an example in which the present invention is applied to a successive approximation type analog-to-digital converter, but #1 is almost the same when applied to a parallel processing type analog-to-digital converter.

FIG. 7 shows an embodiment in which the present invention is applied to a parallel processing type analog-to-digital converter. In Fig. 7, 1 is an analog signal input terminal, 5 is a digital signal output terminal, 7 is a reference voltage input terminal, 8 is an analog-digital conversion pulse input terminal, 9 is a resistance circuit, 10 is a comparator group, and 11 is an encoder. , 12 is a Radzi circuit, 18 is a signal level detection/
The control circuit includes a variable resistance circuit control signal output terminal 19, a variable resistance circuit network, an operational amplifier 21, and a constant current source n.

As in the case of the successive approximation type analog-to-digital converter shown in Fig. 5, among the digital data outputs determined in proportion to the analog input signal level, the m pits from the highest pit are set at the level in order to perform automatic gain control. The signal is input to the detection/control circuit 18. The level detection/control circuit 18 calculates the average level of each bit during time T, and the method of determining the resistance value based on the average level is the same as in the case of FIG.
The resistance value is set small for small analog input signals, and the resistance value is set large for large analog input signals. The maximum allowable input voltage range FSR of an analog-to-digital converter is determined by equation (3) in the case of a parallel processing type analog-to-digital converter; Voltage tolerance range FSRt! The FSR is set to a small value, and the FSR is set to a large value for an analog input signal of a large voltage.

I have explained successive approximation type analog-to-digital converters and parallel processing type analog-to-digital converters, but
The present invention can achieve exactly the same effect even when the level detection/control circuit, variable resistance network, and operational amplifier described in section (H) are added to an integral type analog-to-digital converter or a series-parallel type analog-to-digital converter. can be found.

As explained above, according to the present invention, by adding a level detection/control circuit, a variable resistance network, and an operational amplifier to various analog-to-digital converters, automatic gain control can be performed in response to the analog input signal level. Since analog-to-digital conversion can be performed with high accuracy, the reliability of the analog-to-digital converted data is maintained, or the S/N ratio is maintained at a good level.

Furthermore, since all of the circuit networks added to perform automatic gain control are inexpensive, the present invention has the advantage of being superior in terms of cost.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional successive approximation type analog-to-digital converter, and Figure 2 is a block diagram of a conventional parallel processing type analog-r.
A block diagram of a digital converter; Figures 3 and 4 are block diagrams of a conventional analog-to-digital converter that performs automatic gain control; Figure 5 shows a case in which the present invention is applied to a successive approximation analog-to-digital converter. FIG. 6 is a diagram showing an embodiment of the main part of the present invention in a 3-bit successive approximation type analog-to-digital converter, and FIG. 7 is a diagram showing the case where the present invention is applied to a parallel processing type analog-to-digital converter. 8 and 9 are diagrams showing an example of the switching method and the correspondence between analog input and digital output in the circuit of FIG. 6. 1...Analog signal input terminal, 2...Comparator,
3... Analog-digital conversion start pulse input terminal, 4... Successive approximation register, 5... Digital signal output terminal, 6... Digital-analog converter, 7... Digital-analog converter reference Voltage input terminal, 8... Analog-digital conversion pulse input terminal, 9... Resistance circuit, 1o... Comparator group, 11
...Encoder, 12...Latch circuit, 18.
...Signal level detection/control circuit, +9...Variable resistance circuit control signal output terminal, I...Variable resistance circuit network, 2
1...Operation amplifier, η...Constant current source. Figure 1 Atsushi Figure 2 Figure 3 Figure 15 Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] 1. In an analog-to-digital converter of the type that generates a comparison analog signal using a reference voltage input as a reference and obtains a digital signal output corresponding to the analog input signal by comparing an analog force signal with the comparison analog signal, A level that detects the average signal level of the digital signal output for a predetermined period, selects one terminal from a plurality of output terminals according to the detected level, and sends a control signal to the selected output terminal. detection/control circuit,
A variable resistance network digitally controlled by the output signal of the level detection/control circuit and an operational amplifier for obtaining a voltage value proportional to the resistance value of the variable resistance network are added, and the operational amplifier An analog-to-digital converter characterized in that an output voltage value is used as a reference voltage input.