JPS6028270A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To contrive accomplishment of reduction in interelectrode parasitic capacitance and improvement in dielectric breakdown withstand voltage by a method wherein the first electrode is provided on the composite gate insulating film of SiO2 and Si3N4 located on an Si substrate, an etching reaching the surface of the substrate is performed, the second gate insulating film is formed by performing a two-stage oxidizing method, and the second electrode is formed thereon. CONSTITUTION:The first gate insulating film is formed by superposing a thermal oxidized film 12, a CVD Si3N4 film 13, and an SiO2 film 14 which is formed by thermally oxidizing on an Si substrate 11, and a P-added poly Si 15 is superposed thereon. A selective etching is performed on the layer 15 and the film 12 successively, the substrate 11 is exposed, and a gate structure is formed. Oxide films 16 and 17 are formed on the substrate 11 and the poly Si 15 by performing an H2 combustion oxidizing method. At this time, an edge 18 is generated at the end part of the poly Si 15. An oxide film 19 is left by performing an etching on an oxide film 16, the second gate oxide film 20 is formed on the surface of the substrate in a high temperature dried O2 atmosphere, and the oxide film 19 is converted into the film 20. At this time, said edge part 18 is eliminated. Then, the second electr?ode 22 of poly Si is coated, and the titled device is completed by performing the ordinary method. According to this constitution, an excellent thick oxide film can be formed between gate electrodes, parasitic capacitance is reduced, and the edge part 18 can be eliminated, thereby enabling to improve the dielectric breakdown withstand voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method of manufacturing a semiconductor integrated circuit that can obtain an electrically good interelectrode insulator.

(Prior art) In general, one-element dynamic RAM is used in semiconductor integrated circuits.
Alternatively, to achieve higher density in COD devices, 2
A layered polysilicon structure is used. A method of manufacturing a conventional semiconductor integrated circuit having such a two-layer polysilicon structure will be explained with reference to FIG. In FIG. 1(a), 1 is a silicon substrate, 2 is a first gate insulating film, and 3 is polycrystalline silicon. This gate insulating film 2 is formed on the silicon substrate 1 by thermal oxidation, and the film thickness varies depending on the degree of integration of the device, but is usually 20 nm;
00n is used. Then, polycrystalline silicon 3 is deposited as a first electrode, and impurities are introduced to make it conductive. Methods for introducing impurities include a simultaneous phosphine gas (P:H,)k flow method (so-called Doped-poly Si method) during polycrystalline silicon formation, a diffusion method using a pacts source after polycrystalline silicon is formed, or There is a method called ion implantation. Although the N-channel type is explained here as an example, the P-channel type is essentially the same except that the impurity is changed from the N-type to the P-type. A state in which the polycrystalline silicon 3 serving as the electrode of the box 1 is formed on the entire surface of the sea urchin (sea urchin) is shown in FIG. 1(a). Next, polycrystalline silicon 3 and oxide film 2 are etched away using a normal photolithography technique.

At this time, when etching the oxide film 2, the polycrystalline silicon 3 is usually used as an etching mask, so the edges of the oxide film 2 are formed inside the edges of the polycrystalline silicon 3 (
Figure 1(b)). Thereafter, the surface of polycrystalline silicon 30 and the surface of silicon substrate 1 are thermally oxidized to form silicon oxide films 4 and 5. 4 is an oxide film of polycrystalline silicon 3, 5
indicates an oxide film on the silicon substrate 1. Then, a conductive polycrystalline silicon 6 is formed as a second electrode in the same manner as the first conductive polycrystalline silicon 3 (FIG. 1(C)).
). In this way, the silicon oxide film 4 acts as an insulating film that separates the polycrystalline silicon 3 and 6, which are the two electrodes. Further, the silicon oxide film 5 is used as a second gate insulating film, and is required to have a relatively thin film thickness due to device characteristics. The thickness of this oxide film 5 is normally the same as that of the gate insulating film 2 of the tube 1 91? 1 equivalent film thickness is used.

By the way, in order to achieve high performance in a semiconductor integrated circuit, polycrystalline silicon 3 (first electrode) and polycrystalline silicon 6 (
It is desirable to reduce the parasitic capacitance between the silicon oxide film 4 and the second electrode, and for this reason, efforts have been made to make the silicon oxide film 4 as thick as possible while keeping the thickness of the silicon oxide film 5 constant. ing. That is, this is a technique that utilizes the oxidation rate ratio between polycrystalline silicon and single crystal silicon in a relatively low temperature (700° C. to 900° C.) region when a high concentration of phosphorus is introduced into polycrystalline silicon. However, even if such a technique is used, in order to make the silicon oxide film 4''f sufficiently thick, there are problems with the following two points.

The first problem is that if phosphorus is diffused at a level of l x 10"cm-" in order to increase the oxidation rate of polycrystalline silicon 3, it will be difficult to diffuse into polycrystalline silicon 3 when forming silicon oxide films 4 and 5. The problem is that the phosphorus is diffused onto the silicon substrate 1, lowering the threshold voltage of the MOS transistor formed in that area. As a result, the desired operating characteristics may not be obtained, and in the worst case, there is a risk of malfunction. Therefore, the phosphorus concentration in the polycrystalline silicon must be kept at a level that does not cause a drop in the threshold voltage. There is 10"
The oxidation rate ratio between polycrystalline silicon and single crystal silicon could not be increased because the oxidation rate was limited to less than cm''3 level.

The second problem is that as the oxide film 4 becomes thicker, the edge portion of the polycrystalline silicon 3 is lifted by the formed oxide film 4, and as shown in FIG. This means that a recess 7 is formed in the oxide film.

Due to the occurrence of this recessed portion 7, the second polycrystalline silicon 6 formed in this portion is not removed during pattern formation, often resulting in a short-circuit failure, and the second polycrystalline silicon 6 formed in this portion is not removed. The oxide film in step 3 is thinner than other parts.
The dielectric breakdown voltage between polycrystalline silicon 3 and polycrystalline silicon 6 is reduced. Furthermore, as the oxide film 4 of the polycrystalline silicon 3 is made thicker, the etched portions are lifted up significantly, and in extreme cases, the polycrystalline silicon becomes distorted.

(Object of the Invention) The present invention has been made in view of the above-mentioned conventional problems, and provides a method for manufacturing a semiconductor integrated circuit that can slightly reduce the parasitic capacitance between electrodes and improve its dielectric breakdown voltage. The purpose is to

(Example) An embodiment of the present invention will be described below with reference to FIG.

In FIG. 2(a), 11 is a silicon substrate, 12 is an oxide film, and 13 is a silicon nitride film. These are made by thermally oxidizing single crystal silicon, which is a silicon substrate 11, to form a thin oxide film 12 (100 pieces), and then forming a thin silicon nitride film 13 (100 pieces) on the surface of the oxide film 12 using the CVD method. This is what I did. Next, the silicon nitride film 13 is oxidized by a normal thermal oxidation method to form a silicon oxide film 14 (50 layers) (FIG. 2(b)). These oxide films 12
, silicon nitride film and silicon oxide film 14 first
A gate insulating film is formed.

Next, polycrystalline silicon 15 is formed as a first electrode by a normal low pressure CVD method. The film thickness of this polycrystalline silicon 15 was 350 nm. and phosphorus oxychloride (P
OC1! Phosphorus is introduced into polycrystalline silicon in an ordinary diffusion furnace using the phosphorus as a diffusion source. The concentration of phosphorus introduced is 3
About X 10" cm-3 to 6 X 1020 cm-3 lowers the sheet resistance of polycrystalline silicon, increases the oxidation rate ratio between polycrystalline silicon and single crystal silicon, and inhibits autodoping from polycrystalline silicon. A preferable result was obtained from the viewpoint of reducing the amount of space, and here 4
).

Thereafter, polycrystalline silicon 15 is partially removed using conventional photolithography techniques. In this step, a photoresist was used as an etching mask, and a parallel plate plasma etching apparatus was used as an etching apparatus. Conditions are RF power 300W, etching gas 5%02
-CF, gas flow rate 95 cc/n1in, degree of vacuum 0
, 5 Torr. Next, the oxide film 14 is etched using a KIXF solution and the polycrystalline silicon 15 is used as an etching mask, and the photoresist used in etching the polycrystalline silicon 15 is removed with 120° C. sulfuric acid. Then, the silicon nitride film 13 is removed by etching with a phosphoric acid solution heated to 170° C. using the polycrystalline silicon 15 as a mask, and then the oxide film 12 is removed by etching in the same manner as the oxide film 4 (FIG. 2(d)). ).

Next, hydrogen burning oxidation at 850°C (hydrogen 31/A-).

An oxide film 16 is formed on the silicon substrate 11 using oxygen (3t153-).
300 people. At this time, about 1000 oxide films 17 are formed on the polycrystalline silicon 15. Further, a corner portion 18 is formed at the edge portion of the polycrystalline silicon 15 (FIG. 2(e)
)). Then, the oxide film 16 is removed with 5% hydrofluoric acid to expose the surface of the silicon substrate 11. At this time, the oxide film 17 is also etched in the same way, and when the oxide film 16 is removed, approximately 700
The oxide film 19 in the hole remains (FIG. 2(f)). Next 950℃
An oxide film 20 of 300 Å is formed on the surface of the silicon substrate 11 in dry oxygen to serve as a second gate insulating film. At this time, the polycrystalline silicon 15 is also oxidized at the same time, and the oxide film 19 is about to
It changes to the oxide film 21 of ooA. Furthermore, the corner portions 18 shown in FIGS. 2(e) and 2(f) also disappear, resulting in a good cross-sectional shape. Furthermore, similarly to the polycrystalline silicon 15, polycrystalline silicon 22 is deposited as a second electrode (FIG. 2(g)).

Thereafter, a SiVe is formed by a commonly used MO8 type integrated circuit process.

As described above, in this embodiment, since a composite film is used for the first gate insulating film and the second goo 146& film is oxidized in two stages, the following advantages are obtained.

That is, the first advantage is that the lifting of polycrystalline silicon 3 shown in FIG. 1(e) can reduce the occurrence of wrinkles 8.

The lifting of the polycrystalline silicon 3 9 can be explained as follows. First, when forming oxide films 4 and 5, oxygen diffuses through gate insulating film 2 and is supplied to the lower surface of polycrystalline silicon 3, oxidizing the lower surface. As a result, the thickness of the oxide film formed is approximately twice the thickness of the consumed polycrystalline silicon 3, so that the oxide film pushes up the polycrystalline silicon 3, causing a raised portion 8. In this case, the amount of oxygen supplied increases as the gate insulating film 2 becomes thicker. However, if the thin oxide film of the silicon nitride film 13 is used as the oxide film under the polycrystalline silicon 15 as in the embodiment, the amount of oxygen supplied to the underside of the polycrystalline silicon 15 will be negligible and the lift will be reduced. rarely occurs. In addition, similar effects can be expected with conventional technology if the thickness of the oxide film is made comparable to the thickness used in the example, but in that case, there is a limit due to the electric field applied to the oxide film during device operation. This tends to cause damage to the oxide film. If the first gate insulating film has a structure of oxide film/silicon nitride film/oxide film as in the embodiment, the oxide film in the portion in contact with polycrystalline silicon can be thinned and the first polycrystalline silicon can be lifted up. It is possible to reduce the electric field applied to the first gate insulating film by making the oxide film/silicon nitride film thicker in other parts while maintaining a good edge shape with less damage, which increases stability against gate breakdown. You can improve your sexuality. Note that an oxide film 14 of silicon nitride is added to the oxide film.
The use of silicon nitride takes advantage of the slow oxidation rate of silicon nitride, which allows a thin oxide film to be stably obtained, and the oxide film 14 improves the insulation properties of the first gate insulating film. It works to improve.

A second advantage is that the corners 18 shown in FIGS. 2(e) and 2(f) eventually disappear. This corner 18
The occurrence of this is explained as follows. That is, when oxidation is performed at a low temperature as in the embodiment in order to make the oxide film 17 of the polycrystalline silicon 15 thicker than the single crystal silicon oxide film 16, the oxidation rate of the polycrystalline silicon 15 is such that the oxide film thickness is at least 200A. It is said that in the following regions, the rate is determined by the amount of oxygen diffused to the surface, and the rate is determined by the rate of reaction between silicon and oxygen. However, since the corner portion 18 is close to the silicon nitride film 13, the amount of oxygen supplied is small and the oxygen concentration tends to decrease. In addition, as the thickness of the oxide film 17 increases, the compressive stress increases at the corners 18, making it difficult for oxygen to diffuse, and the amount of oxygen supplied determines the oxidation rate rather than the reaction rate between oxygen and silicon. A corner portion 18 is generated where the p oxidation rate is slower than the portion . In the example, after removing the oxide film 16, oxidation is performed at a high temperature of 950°C.
The entire surface of the polycrystalline silicon 15 is oxidized at a rate determined by the amount of oxygen diffused in the oxide film 19, and as a result, the corners 18 disappear.

As described above, if the corner portion 18 exists in the polycrystalline silicon 15, dielectric breakdown is likely to occur because the oxide film thickness at that portion is thin, and electric field concentration also occurs, making dielectric breakdown likely to occur. By eliminating the corner portion 18, the dielectric breakdown voltage between the p1 first polycrystalline silicon 15 and the second polycrystalline silicon 22 could be increased from 15V to 26V.

In the above embodiment, polycrystalline silicon was used as the first gate electrode material, but a high melting point metal silicide such as molybdenum silicide may be used instead.
Similar effects can be obtained even when high melting point silicide is used in place of polycrystalline silicon for the gate electrode material. In addition, as the first gate insulating film, silicon oxide film/silicon nitride film/silicon oxide film/silicon nitride film/
Although a silicon oxide film is used, the silicon oxide film 14 on the polycrystalline silicon 15 side is not necessarily necessary and can be omitted depending on the allowable leakage current of the first gate insulating film. Furthermore, even if the silicon substrate is a polycrystalline silicon substrate, the same effects as in the above embodiment can be achieved.

(Effects of the Invention) As described above, according to the method of manufacturing a semiconductor integrated circuit of the present invention, a composite film of an oxide film and a silicon nitride film is formed on a silicon substrate to serve as the first gate insulating film. After forming a first electrode on the first gate insulating film, etching is performed to the surface of the silicon substrate, then a second gate insulating film is formed by two-step oxidation, and a second electrode is formed on the second gate insulating film. As the electrodes are formed, a thick oxide film can be effectively formed between the first gate electrode and the second gate electrode, reducing parasitic capacitance, and further preventing dielectric breakdown between the electrodes. It has the advantage of improved breakdown voltage and can be used for high-density, high-performance l-element type dynamic RAM or COD devices.

[Brief explanation of the drawing]

FIG. 1 is a process explanatory diagram of a conventional semiconductor integrated circuit manufacturing method, and FIG. 2 is a process explanatory diagram showing an embodiment of the semiconductor integrated circuit manufacturing method of the present invention. 11... Silicon substrate, 12... Silicon oxide film,
13... Silicon nitride film, 14... Silicon oxide film, 15... First gate electrode, 16.17, 19, 2
0°21...Silicon oxide film, 18...Corner, 22
...Second gate electrode. Figure 1 Figure 2 Procedural amendment (voluntary) Commissioner of the Patent Office Kazu Wakasugi Failure 1 Display of the case 1982 Patent Application No. 135232 2 Name of the invention Method for manufacturing semiconductor integrated circuits 3, ? +I] Relationship with the person making the correction Patent applicant (029) Oki Electric Industry Co., Ltd. 4 Agent 5 Detailed explanation of the invention in the specification subject to amendment 6 Contents of the amendment Page 7, line 19 of the specification “Membrane Correct "and" to "1 film 13, and". 3M-

Claims (7)

[Claims] (1) A step of oxidizing the silicon substrate surface to form an oxide film, a step of forming a silicon nitride film on the oxide film, and a step of forming the silicon nitride film on the silicon nitride film after or after oxidizing the silicon nitride film. a step of etching these composite films to the surface of the silicon substrate to form a gate structure; and a step of oxidizing the gate structure to form an oxide film on this surface. A step of removing the thickness of this oxide film formed on the silicon substrate, and re-oxidizing the surface of the gate structure on which the oxide film is formed, and then forming a second electrode film on this gate structure. A method for manufacturing a semiconductor integrated circuit, comprising the steps of: (2) The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein the silicon substrate is a single crystal silicon substrate. (3) The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein the silicon substrate is a polycrystalline silicon substrate. (4) The method for manufacturing a semiconductor integrated circuit according to any one of claims 1 to 3, wherein the first electrode is made of conductive polycrystalline silicon. (5) The method for manufacturing a semiconductor integrated circuit according to any one of claims 1 to 3, wherein the first electrode is made of high melting point metal silicide. (6) The method for manufacturing a semiconductor integrated circuit according to any one of claims 1 to 5, wherein the second electrode is made of conductive polycrystalline silicon. (7) The method for manufacturing a semiconductor integrated circuit according to any one of claims 1 to 5, wherein the second electrode is made of high melting point metal silicide.