8. 12條正 A7 B7 經濟部中央樣準扃負工消费合作社印«. 五、發明说明（) 現在參考圖九。然後，形成所述金氧半場效電晶體之閘氧化層7 (Gate Oxide)，接著，以所述•第一介電層5』作爲離子佈植保護罩（Ion Implantation ProtectionMask)，利用離子佈植技術（Ionlmplantat丨on)在所述『凹槽內進 行『通道慘雜9』（(Channel Doping)，以形成摻雜區域11 (Doping Region)， 以調整所述金氧半場效電晶體之臨界電壓（Threshold Voltage) »所述『閘氧化層! 7』是利用熱氧化技術（Thermal oxidation)氧化所述P型砂半導體晶圓1之表面 而成，其氧化溫度介於900到1000 °C之間，其厚度則介於80到160埃之間。 所述111通道慘雜9』，其離子種類是硼原子（Bll)，其離子佈値劑量介於1E11 到1E13原子/平方公分之間，其離子佈値能量則介於10到30 Kev之間。 現在參考圖十、圖十一和圖十二。接著，沉積一層複晶矽13 (Polysilicon)，所述『複晶矽13』並塡滿所述f凹槽6』，如圖十所示。然後， 在高溫環境中將所述第一介電層j表面之所述『複晶矽13』熱氧化（Thermal Oxidation)，以形成『複晶矽氧化矽14』（Polysilicon Dioxide)，在所述《凹槽1 6』內則保留有-Γ部份未被氧化的Γ複晶矽13A』。複晶矽熱氧化溫度介於750到’ 900 °C之間，於濕氧的環境中進行，爲習知技術。第-介電層之厚度介於2000 '到4000埃之間，電晶體之通道寬度介於1S00到4000埃之間，沉積之複晶矽 厚度介於1000到3000埃之間，藉著控制熱氧化溫度和時間，吾人可將所述凹槽 外的複晶矽完全氧化，而在所述凹槽內的複晶矽則被氧化掉500到1000埃，保 留之複晶矽厚度約介於1500到3000埃之間--『複晶矽13A』。接著利用氫氟 酸蝕刻溶液去除所述『複晶矽氧化矽14』，而在所述『凹槽6』內則保留有所述 『複晶砂13A』，以形成埋層複晶砂閘極13A(RecessedPolysiliconGate) ’如圖 Η^一所示。接著，旋即利用氫氟酸蝕刻溶液去除所述『複晶矽氧化较ΗΑ』’而 在所述『凹槽6』內則保留有所述『複晶矽13Α』，以形成金氧半場效電晶體之 埋層複晶砂閘極13Α (Recessed Polysilicon Gate) ’如圖十一所不。所述『複晶砂 13』通常是利用磷原子之同步攙雜技術形成（In-Situ Phosphorus Doped )，反應方 式是低壓化學氣相沉積法，反應氣體是PH3、SiH4與N2的混合氣體，反應溫度 介於520到580 °C之間，其厚度介於丨〇〇〇到3〇〇〇埃之間，必需塡滿所述『凹槽 6』° 現在參考圖十三和圖彳·四。接著’去除所述『第·介電層5A』以露出所述 『埋層複晶砂閘極13Aj，如圖十三所示’並利用離子佈植技術形成金氧半場效 電晶體之N-淡摻雜源極/汲極15 (LightlyDopedSource/Drain) ’如圖十四所 示。通常是利用稀釋氫氟酸去除所述『第一介電層5A』。所述『N_淡摻雜源極 /汲極15 j之離子種類是磷原子（P3】），離子佈値劑量介於1ΕΠ到3E14原子 /平方公分之間，離子佈値能量則介於2〇到40 Kev之間。 . 』 * ——-•i .1.^1 ϋ— m 11 —ϋ m —if i^i i m nm— flu I (請先閱讀背£之注$項再填寫本*) 本纸《：欠度逋用中國國家椟準（〇^>入4规格（210><297公釐） 8. 12條正 A7 B7 經濟部中央樣準扃負工消费合作社印«. 五、發明说明（) 現在參考圖九。然後，形成所述金氧半場效電晶體之閘氧化層7 (Gate Oxide)，接著，以所述•第一介電層5』作爲離子佈植保護罩（Ion Implantation ProtectionMask)，利用離子佈植技術（Ionlmplantat丨on)在所述『凹槽內進 行『通道慘雜9』（(Channel Doping)，以形成摻雜區域11 (Doping Region)， 以調整所述金氧半場效電晶體之臨界電壓（Threshold Voltage) »所述『閘氧化層! 7』是利用熱氧化技術（Thermal oxidation)氧化所述P型砂半導體晶圓1之表面 而成，其氧化溫度介於900到1000 °C之間，其厚度則介於80到160埃之間。 所述111通道慘雜9』，其離子種類是硼原子（Bll)，其離子佈値劑量介於1E11 到1E13原子/平方公分之間，其離子佈値能量則介於10到30 Kev之間。 現在參考圖十、圖十一和圖十二。接著，沉積一層複晶矽13 (Polysilicon)，所述『複晶矽13』並塡滿所述f凹槽6』，如圖十所示。然後， 在高溫環境中將所述第一介電層j表面之所述『複晶矽13』熱氧化（Thermal Oxidation)，以形成『複晶矽氧化矽14』（Polysilicon Dioxide)，在所述《凹槽1 6』內則保留有-Γ部份未被氧化的Γ複晶矽13A』。複晶矽熱氧化溫度介於750到’ 900 °C之間，於濕氧的環境中進行，爲習知技術。第-介電層之厚度介於2000 '到4000埃之間，電晶體之通道寬度介於1S00到4000埃之間，沉積之複晶矽 厚度介於1000到3000埃之間，藉著控制熱氧化溫度和時間，吾人可將所述凹槽 外的複晶矽完全氧化，而在所述凹槽內的複晶矽則被氧化掉500到1000埃，保 留之複晶矽厚度約介於1500到3000埃之間--『複晶矽13A』。接著利用氫氟 酸蝕刻溶液去除所述『複晶矽氧化矽14』，而在所述『凹槽6』內則保留有所述 『複晶砂13A』，以形成埋層複晶砂閘極13A(RecessedPolysiliconGate) ’如圖 Η^一所示。接著，旋即利用氫氟酸蝕刻溶液去除所述『複晶矽氧化较ΗΑ』’而 在所述『凹槽6』內則保留有所述『複晶矽13Α』，以形成金氧半場效電晶體之 埋層複晶砂閘極13Α (Recessed Polysilicon Gate) ’如圖十一所不。所述『複晶砂 13』通常是利用磷原子之同步攙雜技術形成（In-Situ Phosphorus Doped )，反應方 式是低壓化學氣相沉積法，反應氣體是PH3、SiH4與N2的混合氣體，反應溫度 介於520到580 °C之間，其厚度介於丨〇〇〇到3〇〇〇埃之間，必需塡滿所述『凹槽 6』° 現在參考圖十三和圖彳·四。接著’去除所述『第·介電層5A』以露出所述 『埋層複晶砂閘極13Aj，如圖十三所示’並利用離子佈植技術形成金氧半場效 電晶體之N-淡摻雜源極/汲極15 (LightlyDopedSource/Drain) ’如圖十四所 示。通常是利用稀釋氫氟酸去除所述『第一介電層5A』。所述『N_淡摻雜源極 /汲極15 j之離子種類是磷原子（P3】），離子佈値劑量介於1ΕΠ到3E14原子 /平方公分之間，離子佈値能量則介於2〇到40 Kev之間。 . 』 * ——-•i .1.^1 ϋ— m 11 —ϋ m —if i^i i m nm— flu I (請先閱讀背£之注$項再填寫本*) 本纸《：欠度逋用中國國家椟準（〇^>入4规格（210><297公釐） 經濟部中央橾率局員工消费合作社印装 A7 B7 五、發明説明（） (三).發明之簡要說明 本發明之主要目的是提供一種具有低接面漏電（Low Junction Leakage)與低接 面電容（Low Junction Capacitance )之金氧半場效電晶體的製造方法。 本發明之另一個目的是提供一種金氧半場效電晶體之局部通道摻雜（Local Channel Doping)的製造方法。 茲說明本發明之主要方法如下。 首先，以傳統淺凹槽隔離技術（Shallow Trench Isolation ; STI)在砂半導體晶圓 上形成隔離『金氧半場效電晶體』所需要的厚氧化層（FieldOxide)。然後’形成一 層第一介電層（FirstDielectric)，並利用微影技術與電漿蝕刻技術蝕去所述第一介 電層以形成凹槽（Trench)。形成所述『凹槽』之微影光阻圖案是傳統形成金氧半場 效電晶體之間極的逆圖案（Reversed-Tone)。 然後，形成所述金氧半場效電昂體之閘氧化層（Gate Oxide)，接著，以所述 『第一介電層』作爲離子佈植保護罩（Ion Implantation Protection Mask )，利用離子 佈植技術在所述凹槽內進行『通道摻雜』，以調整所述金氧半場效電晶體之臨界電 壓（Threshold Voltage)。 接著，沉積一層複晶矽（Polysilicon)，所述複晶矽塡滿所述『凹槽』。然後， 在高溫環境中將所述『第一介電層』表面之所述複晶矽熱氧化（Thermal Oxidation)，以形成複晶较氧化砂（PolysiliconDioxide)，在所述『凹槽』內則保 留有一部份未被氧化的複晶矽，並旋即利用氫氟酸蝕刻溶液去除所述『複晶矽氧化 矽』，而在所述『凹槽』內貝IJ保留有所述複晶矽，以形成埋層複晶矽閘極(Recessed Polysilicon Gate ) 〇 接著，去除所述第一介電層，並利用離子佈植技術形成N_淡摻雜源極/汲極 (LightlyDopedSource/Dr?iin)，再形成一層第二介電層（SecondDielectric)，並利 用電漿蝕刻技術對所述第二介電層進行垂直單向性的回鈾刻，以在所述閘極的旁側 形成第二介電層側壁子（SecondDielectric Spacer) 〇最後，利用離子佈植技術形成 N+濃摻雜源極/汲極（Heavily Doped Source/Drain)，一種具有低接面漏電（Low Junction Leakage)與低接面電容（Low Junction Capacitance)之N通道金氧半場效電 晶體於焉完成。 本紙張.尺度適用中國國家棣準 ( CNS.) A4規格_.( 210X.297公釐） (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局員工消費合作社印褽 4 A7 B7 五、發明説明（） (四).圖示的簡要說明 圖一到圖六是製造金氧半場效電晶體（MOSFET)之傳統方法的製程剖面示意圖 (Process Cross Section)。 圖七至圖十六是本發明之實施例的製程剖面示意圖。_ 圖一是形成隔離金氧半場效電晶體所需要的場氧化層後的製程部面示意圖: 圖二是形成金氧半場效電晶體之閘氧化層，並進行所述金氧半場效電晶體之通道摻 雜（Channel Doping )’以調整所述金氣半場效電晶體之臨界電壓（Threshold Voltage)後的製程剖面示意圖； \ 圖三是形成一層複晶矽（Polysilicon)，並利用微影技術與電漿蝕刻技術敏去斯述複 晶矽以形成金氧半場效電晶體之閘極（GateElectrode)後的製程剖面示意圖； _四是形成金氧半場效電晶體之N·淡摻雜源極/汲極後的製程剖面示意圖； 圖五是形成一·層二氧化矽（SiliconDioxide)，並對所述二氧化矽進行垂直單向性的 回蝕刻（Anisotropic Etchback)，以在所述閘極之二側形成二氧化砍側壁子（siliC0n Dioxide Spacer)後的製程剖面不意圖； 圖六是利用離子佈植形成金氧半場效電晶體之N+濃摻雜源極/汲極後的製程剖面示 思圖， · 圖七是在较半導體晶圓形成一層第一介電層（FirstDielectric)後的製程剖面示意 圖， 圖八是利用微影技術與電漿蝕刻技術餓去所述第一介電層以形成凹槽Clinch)後的 製程剖面示意圖； 圖九是形成所述金氧半場效電晶體之閘氧化層（GateOxide)，並以所述凹槽作爲離 ，子佈植保護罩（Ion ImpJ_^tion Protection Mask )，利用離子佈植技術在所述凹槽內 進行名通道後的製程剖面示意圖； 圖十是祝^一·^晶砂（Polysilicon)後的製程剖面示意圖，所述複晶砂塡滿所述 『凹槽』； ，. 圖十一是在在高溫環境中將所述『第一介電層』表面之所述複晶砍熱氧化CThermal Oxidation)，以形成複晶砂氧化砂（PolygiliconDioxide)後的製程剖面示意圖，而 在所述『凹槽』內則保留有一部份的未被氧化的所述『複晶矽』 ί十二是利用氫窠戡蝕刻溶液去除所述『複晶矽氧化矽』後的製程剖面示意圖，而 在所述f凹槽』內則保留有所述複晶矽，以形成埋層複晶矽閘極（Recessed Polysilicon Gate )； -圖十三是去除所述第一介電層後的製程剖面示意圖； 圖十四是利用離子佈植技術形成N-淡摻雜源極/汲極後的製程剖面示意圖； 圖十五是形成一層第二介電層（ Second Dielectric )，並利用電發蝕刻技術對所述第 f介電層進行垂直單向性的回蝕刻以在所述閘極的側邊形成第二介電層側壁子 I： Second Dielectric Spacer )後的製程剖面示意圖； ， 圖十六是利用離子佈植技術形成N+濃摻雜源極/汲極後的製程剖面示意圖。 本紙張尺度適用中國國家揉準（CNS ) A4规格（210X297公釐） —叫___^---f^------訂----.--C: 二- (請先閲讀背面之注意事項再填寫本頁) A7 B7 經濟部中央揉準局貝工消費合作社印裝 五、發明説明（） (五).發明之詳細說明 以下利用N通道金氧半場效電晶體（NMOS)闡述本發明之方法，但是，本發 明之方法也可以延伸到P通道金氧半場效電晶體（PMOS)與互補式金氧半場效電 晶體（Complementary Metal Oxide Semiconductor Field Effect Transistor ； CMOSFET)積體電路的製造。 先參考圖七。利用傳統淺凹槽隔離技術（ShallowTrench Isolation ; STI)在晶 格方向（100)的P型砂半導體晶圓上1 (Silicon Semiconductor Wafer)形成隔離 金氧半場效電晶體所需的厚氧化層（FieldOxide)，所述厚氧化層之厚度介於3000 埃到8000埃之間，所述厚氧化層未顯示於圖七。接著，沉積一層第一介電層5 (FirstDielectric)，如圖七所示。 現在參考圖八。接著，利用微影技術與電漿蝕刻技術蝕去所述第一介電層5以 形成凹槽6 (Trench)，如圖八所示。所述電漿蝕刻終止於所述P型矽半導體晶圓 1之表面。所述『凹槽6』之寬度視積體電路設計準則而定，在深次微米領域，所述 『凹槽6』之寬度約介於0.18到0.4微米之間。通常，所述『第一介電層5』是 利用低壓化學氣相沉積法（Low Pressure Chemical Vapor Deposition ; LPCVD)形成 之慘雜的二氧化较（Doped Silicon Dioxide)或是無摻雜的二氧化砂（Undoped Silicon Dioxide )，其反應氣體是四已基矽酸鹽（TetraEthOxySilane ; TEOS)或是矽 甲烷（Silane )，反應溫度介於650到750 °C之間，反應壓力介於0.2到0.4 torr之 間，厚度介P 2000到4000埃之間。要特別注意的是，形成所述1**凹槽6』之微 影光阻圖案（Lithography Photoresist Pattern)是傳統形成金氧半場效電晶體之_極的 逆圖案（Reversed-Tone)。 對所述『第一介電層5』之電漿蝕刻，可以利用磁場增強式活性離子式電漿鈾 刻技術（Magnetic Enhanced Reactive· Ion-Etching ; MERIE)或電子迴旋共振電獎餓刻 _技術_( Electron_Cyclotron. Resonance ΈΟΙ)，抑或是傳統的活性離子式電獎軸刻技 術（Reactive I〇n Etching ; RIE)，在次微米技術領域或深次微米領域，一般是利用 磁場增強式活性離子式電漿鈾刻，其電漿反應氣體是CF4和CHF3等氟類氣體搭配 少量的氬氣氣體（Argon)。 b— II —ί i-··. I1 - ί - I--- 11 Is I—I 1 — 1- ·*' * (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度il用中國國家捸率（CNS ) .A4规格.(.210 X_ 2+97公釐:） A7 B7 經濟部中央標準局員工消費合作杜印«. 五、發明説明（） 現在參考圖九。然後，形成所述金氧半場效電晶體之閘氧化層7 (Gate Oxide) ’接著，以所述第一介電層5』作爲罐子佈植保護罩（Ion Implantation Protection Mask)，利用離子佈植技術（Ion Implantation)在所述『凹槽6』內進行 『通道摻雜9』（Channel Doping)，以形成摻雜區域11 (Doping Region)，以調 整所述金氧半場效電晶體之臨界電壓（Threshold Voltage)。所述『閘氧化層7』是 利用熱氧化技術（Thermal oxidation)氧化所述P型矽半導體晶圓1之表面而成， 其氧化溫度介於900到1000 °C之間，其厚度則介於80到160埃之間。所述『通 道摻雜9』，其離子種類是硼原子（Bll )，其離子佈値劑量介於1E11到1E13原 子/平方公分之間，其離子佈値能量則介於10到30 Kev之間。 現在參考圖十、圖十一和圖十二。接著，沉積一層複晶矽13 (Polysilicon)和 鈦金屬層14 (Metal)，所述『複晶矽13』並塡滿所述『凹槽6』，如圖十所示。 然後，在高溫環境中將所述『第一介電層』表面之所述『複晶矽13』熱氧化 (Thermal Oxidation)，以形成複晶砍氧化砂 14 (Polysilicon Dioxide)，在所述 『凹槽6』內則保留有一部份未被氧化的『複晶矽13A』，並旋即利用氫氟酸蝕刻 溶液去除所述^複晶矽氧化矽14』，,而在所述1r凹槽0』內則保留有所述『複晶矽 13A』，以形成埋層複晶砂閘極13A (Recessed Polfsilicon Gate)，如圖~ί^一所示。 接著，旋即利用氫氟酸蝕刻溶液去除所述『複晶矽氧化矽14Α』，而在所述『凹槽 6』內則保留有所述1複晶矽13Α』，以形成金氧半場效電晶體之埋層複晶矽閘極 13Α (Recessed Polysilicon Gate)，如圖十二所示。所述『複晶砂13』通常是利用憐 原子之同步攙雜技術形成（In-Situ Phosphorus Doped )，反應方式是低壓化學氣相沉 積法，反應氣體是PH3、SiH4與N2的混合氣體，反應齒度介於520到580 °C之 間，其厚度介於1〇〇〇到3000埃之間，必需塡滿所述『凹槽6』。 . - 現在參考圖十三和圖十四。接著，去除所述第一介電層5Aj以露出所述 『埋層複晶矽閘極13A』，如圖十三所示，並利用離子佈植技術形成金氧半場效電 晶體之N-淡接雜源棒/汲極15 (Lightly Doped Source/Drain)，如圖十四所示。通 常是利用稀釋氫氣酸去除所述『第一介電層5A』。所述『N-淡摻雜源極/汲極 15』之離子種類是磷原子（P31)，離子佈値劑量介於1E13到3E14原子/平方公 分之間，離子佈値能量則介於20到40 Kev之間。 (請先閲讀背面之注意事項再填窍本頁) 訂 本纸張尺度遑用中國國家搞準（CNS )A4規格( 210X297公釐） .經濟部中央橾準局貝工消費合作社印$. A7 B7 五、發明説明（） 現在參考圖十五和圖十六。接著，形咦一層第二介電層17 (Second Dielectric)，並利用電漿蝕刻技術對所述『第二介電層17』進行垂直單向性的回蝕 刻，以在所述所述『埋層複晶矽閘極13A』的側邊形成第二介電層側壁子17 (Second Dielectric Spacer)，如圖十五所示。最後，利用離子佈植技術形成金氧半 場效電晶體之N+濃摻雜源極/汲極19 (HeavilyDoped Source/Drain)，如圖十六 所示。 本發明揭露之利用習知的複晶矽熱氧化CMnnal Oxidation)的觀念，配合 p凹槽6』形成埋層複晶砂閛極13A (Recessed Polysilicon Gate)之方法，可以將金 氧半場效電晶體之『通道摻雜』侷限在通道區域（ChannelRegion)，因此，當製造 深次微米金氧半場效電晶體而在所述『通道區域』需要非常高的摻雜濃度時，通道 區域以外之矽半導體晶圓的雜質濃度不會昇高，故能降低接面漏電與接面電容，得 到具有$越電性之金氧半場效電晶體。是故，在形成所述『N+濃摻雜源極/汲極 19』之後，一種具有低接面漏電（Low Junction Leakage)與低接面電容（Low Junction Capacitance)之N通道金氧半場效電晶體於焉完成。.自然，;發明之方法 也可以延伸到P通道金氧半場效電晶體（PMOSFET)與互補式金氧半場效電晶體 (CMOSFET )積體電路的製造。 所述®第二介電層17』通常是利用低壓化學氣栢沉積法形成之無摻雜的二氧 化砂（Undoped Silicon Dioxide )，其反應氣體是四已基砂酸鹽 (TetraEthOxySilane ; TEOS)，反應溫度介於650到750 °C之間，反應壓力介於 0.2到0.4 t〇lt之間，厚度介於1000到3000埃之間》同樣的，對所述『第二介電 層17』之垂直單向性的回蝕刻，可以利用磁場增強式活性離子式電漿蝕刻技術或是 電子迴旋共振電獎触刻技術，或是傳統的活性離子式電漿触刻技術，而在次微米技 術領域，通常是利用磁場增強式活性離子式電漿鈾刻，其電漿反應氣體是CF4和 CHF3等氟類氣體搭配少量的氬氣氣體（Argon)。所述『N+濃摻雜源極/汲極 19』貝丨堤利用砷原子(As75)，其離子佈値劑量介於1E15到5E16原子/平方公分 之間’離子佈値能量則介於30到100 Kev之間。8. Article 12 A7 B7 Printed by the Central Ministry of Economic Affairs, the Central Government, and the Consumers' Cooperatives. V. Description of Invention () Now refer to Figure IX. Then, a gate oxide layer 7 (Gate Oxide) of the metal-oxide half field-effect transistor is formed, and then the first dielectric layer 5 ′ is used as an ion implantation protection mask (Ion Implantation Protection Mask), and ion implantation is used. (Ionlmplantat 丨 on) performs "Channel Doping" in the "groove to form a doping region 11 to adjust the threshold voltage of the metal oxide half field effect transistor (Threshold Voltage) »The" gate oxide layer! 7 "is formed by thermally oxidizing the surface of the P-type sand semiconductor wafer 1 with an oxidation temperature between 900 and 1000 ° C. Its thickness is between 80 and 160 Angstroms. The 111 channel is miscellaneous 9 ″, its ion type is boron atom (Bll), its ion cloth dose is between 1E11 and 1E13 atoms / cm 2, and its ions The cloth energy is between 10 and 30 Kev. Now refer to Figure 10, Figure 11 and Figure 12. Next, a layer of polysilicon 13 (Polysilicon) is deposited. The f groove 6 ′ is shown in Figure 10. Then, in a high temperature environment The "multicrystalline silicon 13" on the surface of the first dielectric layer j is thermally oxidized to form a "polysilicon dioxide 14", and in the "groove 1 6" Inside, there is retained -Γ part of the non-oxidized Γ polycrystalline silicon 13A ". The thermal oxidation temperature of polycrystalline silicon is between 750 and '900 ° C, and it is performed in a wet oxygen environment. It is a conventional technique. -The thickness of the dielectric layer is between 2000 'and 4000 Angstroms, the transistor channel width is between 1S00 and 4000 Angstroms, and the thickness of the deposited polycrystalline silicon is between 1000 and 3000 Angstroms by controlling thermal oxidation Temperature and time, we can completely oxidize the polycrystalline silicon outside the groove, while the polycrystalline silicon in the groove is oxidized by 500 to 1000 angstroms, and the thickness of the retained polycrystalline silicon is about 1500 to Between 3000 Angstroms-"polycrystalline silicon 13A". Then the "polycrystalline silicon oxide 14" is removed using a hydrofluoric acid etching solution, and the "polycrystalline silicon" is retained in the "groove 6" 13A "to form a buried polycrystalline sand gate 13A (RecessedPolysiliconGate) 'as shown in Figure Η ^ 1. Then, the solution is etched with hydrofluoric acid immediately Liquid to remove the "polycrystalline silicon oxide ΗAA" 'and retain the "polycrystalline silicon 13A" in the "groove 6" to form a buried polycrystalline sand gate of a metal-oxygen half field effect transistor极 13Α (Recessed Polysilicon Gate) 'As shown in Figure 11. The "composite sand 13" is usually formed by the simultaneous doping technique of phosphorus atoms (In-Situ Phosphorus Doped). The reaction method is a low-pressure chemical vapor deposition method. The reaction gas is a mixed gas of PH3, SiH4 and N2, and the reaction temperature. It is between 520 and 580 ° C, and its thickness is between 1000 and 3,000 angstroms, and it is necessary to fill the "groove 6". Now refer to FIG. 13 and FIG. 4. Then 'remove the' dielectric layer 5A 'to expose the' buried polycrystalline sand gate 13Aj, as shown in FIG. 13 'and use ion implantation technology to form N- Lightly doped source / drain 15 'Figure 14 shows. The "first dielectric layer 5A" is usually removed by dilute hydrofluoric acid. The "N_lightly doped source / drain 15 j ion type is phosphorus atom (P3)), the ion cloth dose is between 1EΠ and 3E14 atoms / cm², and the ion cloth energy is between 2 〇 to 40 Kev. 』* ——- • i .1. ^ 1 ϋ— m 11 —ϋ m —if i ^ iim nm— flu I (please read the note in the back of the note before filling in this *) This paper": Deficiency逋 Use China National Standards (0 ^ > Enter 4 specifications (210 > < 297 mm) 8. 12 positive A7 B7 Central Ministry of Economics Standard Samples Printed by Consumers' Cooperatives «. V. Description of Invention () Now Refer to FIG. 9. Then, a gate oxide layer 7 (Gate Oxide) of the metal-oxide half field-effect transistor is formed, and then the first dielectric layer 5 ′ is used as an ion implantation protection mask (Ion Implantation Protection Mask). Ionlmplantation is used to perform “Channel Doping 9” (“Doping Region”) in the groove to form a doping region 11 to adjust the gold-oxygen half field effect power. Threshold Voltage of the crystal »The" gate oxide layer! 7 "is formed by thermally oxidizing the surface of the P-type sand semiconductor wafer 1 with a temperature of 900 to 1000 °. Between C, and its thickness is between 80 and 160 angstroms. The 111 channel is miscellaneous 9 ′, and its ion type is a boron atom. Bll), whose ion cloth dose is between 1E11 and 1E13 atoms / cm 2, and its ion cloth energy is between 10 and 30 Kev. Now refer to FIG. 10, FIG. 11 and FIG. 12. Then, A layer of polysilicon 13 is deposited, and the "polysilicon 13" fills the f-groove 6 "as shown in Fig. 10. Then, the first dielectric layer j is placed in a high temperature environment. The "Multicrystalline Silicon 13" on the surface is thermally oxidized to form a "Polysilicon Dioxide", and a -Γ portion remains in the "Groove 1 6" Oxidized Γ polycrystalline silicon 13A ”. The thermal oxidation temperature of polycrystalline silicon is between 750 and '900 ° C. It is a conventional technique in a wet oxygen environment. The thickness of the first dielectric layer is between 2000 and 2000. 'To 4000 Angstroms, the channel width of the transistor is between 1S00 and 4000 Angstroms, and the thickness of the deposited polycrystalline silicon is between 1000 and 3000 Angstroms. By controlling the temperature and time of thermal oxidation, we can The polycrystalline silicon outside the groove is completely oxidized, while the polycrystalline silicon inside the groove is oxidized by 500 to 1000 angstroms, and the thickness of the polycrystalline silicon remaining is Between about 1500 and 3000 Angstroms-"Silicon Silicon 13A". Then the "Silicon Silicon Oxide 14" is removed by using a hydrofluoric acid etching solution, and the "Slot 6" is retained. The "composite sand 13A" is used to form a buried compound sand gate 13A (RecessedPolysiliconGate). Then, the "polycrystalline silicon oxide is relatively high" is immediately removed by using a hydrofluoric acid etching solution, and the "polycrystalline silicon 13A" is retained in the "groove 6" to form a gold-oxygen half field effect electricity Recessed Polysilicon Gate 13A (Recessed Polysilicon Gate) 'As shown in Figure 11. The "composite sand 13" is usually formed by the simultaneous doping technique of phosphorus atoms (In-Situ Phosphorus Doped). The reaction method is a low-pressure chemical vapor deposition method. The reaction gas is a mixed gas of PH3, SiH4 and N2, and the reaction temperature. It is between 520 and 580 ° C, and its thickness is between 1000 and 3,000 angstroms, and it is necessary to fill the "groove 6". Now refer to FIG. 13 and FIG. 4. Then 'remove the' dielectric layer 5A 'to expose the' buried polycrystalline sand gate 13Aj, as shown in FIG. 13 'and use ion implantation technology to form N- Lightly doped source / drain 15 'Figure 14 shows. The "first dielectric layer 5A" is usually removed by dilute hydrofluoric acid. The "N_lightly doped source / drain 15 j ion type is phosphorus atom (P3)), the ion cloth dose is between 1EΠ and 3E14 atoms / cm², and the ion cloth energy is between 2 〇 to 40 Kev. 』* ——- • i .1. ^ 1 ϋ— m 11 —ϋ m —if i ^ iim nm— flu I (please read the note in the back of the note before filling in this *) This paper": Deficiency逋 Use Chinese National Standard (0 ^ > Into 4 specifications (210 > < 297mm) Printed by the Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs A7 B7 5. Description of the invention () (3). Brief description of the invention The main object of the present invention is to provide a method for manufacturing a metal-oxide half field-effect transistor with low junction leakage and low junction capacitance. Another object of the present invention is to provide a metal oxide A method for manufacturing a local channel doping (half field effect transistor) is described below. The main method of the present invention is as follows. First, a conventional shallow trench isolation technology (Shallow Trench Isolation; STI) is formed on a sand semiconductor wafer. Isolate the thick oxide layer (FieldOxide) required for the "metal oxide half field effect transistor". Then 'form a first dielectric layer (First Dielectric), and use lithography and plasma etching technology to etch away the first dielectric Layer to form a groove ). The lithographic photoresist pattern forming the "groove" is a traditional pattern for forming a reverse pattern between metal oxide half field effect transistors (Reversed-Tone). Then, a gate of the metal oxide half field effect transistor is formed. Gate Oxide, and then using the "first dielectric layer" as an ion implantation protection mask (Ion Implantation Protection Mask), and using the ion implantation technology to perform "channel doping" in the groove, To adjust the threshold voltage of the metal-oxide half-field effect transistor. Next, a layer of polysilicon is deposited, and the polysilicon fills the "groove". Then, in a high-temperature environment, the The "multilayer silicon" surface of the "first dielectric layer" is thermally oxidized to form a polycrystalline silicon oxide (PolysiliconDioxide), and a part of the "groove" is not oxidized. The polycrystalline silicon is immediately removed by using a hydrofluoric acid etching solution, and the polycrystalline silicon is retained in the I groove to form a buried polycrystalline silicon. Gate (Recessed Polysilicon Gate) The first dielectric layer is removed, and an N_lightly doped source / drain is formed using ion implantation technology, a second dielectric layer (SecondDielectric) is formed, and a plasma is used. The second dielectric layer is subjected to a vertical unidirectional uranium etch back by an etching technique to form a second dielectric layer spacer (SecondDielectric Spacer) on the side of the gate. Finally, an ion implantation technique is used to form the second dielectric layer. N + Heavily Doped Source / Drain, an N-channel metal-oxygen half field effect transistor with low junction leakage and low junction capacitance . The size of this paper applies to China National Standards (CNS.) A4 specifications _. (210X.297 mm) (Please read the precautions on the back before filling out this page) Order the Central Government Bureau of the Ministry of Economic Affairs Consumer Cooperatives Seal 4 A7 B7 V. Description of the invention () (4). Brief description of the diagrams Figures 1 to 6 are process cross sections of a traditional method for manufacturing a metal-oxide-semiconductor field-effect transistor (MOSFET). 7 to 16 are schematic cross-sectional views of a manufacturing process according to an embodiment of the present invention. _ Figure 1 is a schematic diagram of the manufacturing process after forming the field oxide layer required for isolating the metal oxide half field effect transistor: Figure 2 is a gate oxide layer forming the metal oxide half field effect transistor and performing the metal oxide half field effect transistor Channel Doping 'to adjust the Threshold Voltage of the gold gas half field effect transistor; Figure 3 is a layer of polysilicon, and uses lithography technology Schematic cross-sectional view of the process after forming the gate electrode of the metal-oxide half-field-effect transistor with the plasma etching technology to desaturate the compound silicon; _Fourth is the N · lightly doped source electrode of the metal-oxide half-field-effect transistor. Figure 5 is a schematic cross-sectional view of the process after the drain electrode; Figure 5 is a one-layer silicon dioxide (Silicon Dioxide) is formed, and the silicon dioxide is subjected to vertical unidirectional etch back (Anisotropic Etchback), in order to The cross section of the process after the formation of siliC0n Dioxide Spacer on both sides is not intended; Figure 6 shows the cross section of the process after N + concentrated doped source / drain electrodes are formed by ion implantation to form a gold-oxygen half field effect transistor. Figure 7, Figure 7 is a schematic cross-sectional view of the process after forming a first dielectric layer (FirstDielectric) on a semiconductor wafer, and Figure 8 is a photolithography and plasma etching technology to remove the first dielectric layer to form A schematic cross-sectional view of the manufacturing process after the groove (Clinch) is formed; FIG. 9 is a gate oxide layer (GateOxide) of the metal-oxygen half field effect transistor, and the groove is used as an ion, and a protective cover (Ion ImpJ_ ^ tion Protection) is formed Mask), which is a schematic cross-sectional view of the process after the famous channel is made in the groove by using ion implantation technology; FIG. 10 is a schematic cross-sectional view of the process after the polysilicon; The “groove” is described in FIG. 11. The compound crystal is oxidized (CThermal Oxidation) on the surface of the “first dielectric layer” in a high-temperature environment to form a polycrystalline sand oxide (PolygiliconDioxide). A schematic cross-sectional view of the subsequent process, and a part of the "polycrystalline silicon" that has not been oxidized remains in the "groove". The twelve is to remove the "polycrystalline silicon oxide" using a hydrogen hafnium etching solution. Process section after silicon It is intended that the polycrystalline silicon is retained in the f-groove "to form a buried polysilicon gate;-Figure 13 is after removing the first dielectric layer Schematic cross-sectional view of the process; Figure 14 is a schematic cross-sectional view of the process after the N-lightly doped source / drain is formed by using ion implantation technology; Figure 15 is a second dielectric layer formed using electrical generation A schematic cross-sectional view of a manufacturing process after performing vertical unidirectional etch-back on the f-th dielectric layer to form a second dielectric layer side wall (I: Second Dielectric Spacer) on the side of the gate; The sixth is a schematic cross-sectional view of the process after the N + heavily doped source / drain is formed using ion implantation technology. This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) — called ___ ^ --- f ^ ------ order ----.-- C: 2-(Please read first Note on the back, please fill in this page again) A7 B7 Printed by the Central Bureau of the Ministry of Economic Affairs of the Central Bureau of Quasi-Consumer Co-operative Consumers Co., Ltd. 5. Description of the invention () (V). Detailed description of the invention The method of the present invention is described, but the method of the present invention can also be extended to P-channel metal-oxide-semiconductor field-effect transistor (PMOS) and complementary metal-oxide-semiconductor field-effect transistor (Complementary Metal Oxide Semiconductor Field Effect Transistor; CMOSFET) integrated circuit Manufacturing. Refer to Figure 7 first. The conventional shallow groove isolation technology (ShallowTrench Isolation; STI) is used to form a thick oxide layer (FieldOxide) required for isolating the metal-oxide half field-effect transistor on a P-type sand semiconductor wafer (100) in the lattice direction (100). The thickness of the thick oxide layer is between 3000 angstroms and 8000 angstroms. The thick oxide layer is not shown in FIG. Next, a first dielectric layer 5 (FirstDielectric) is deposited, as shown in FIG. 7. Reference is now made to FIG. Then, the first dielectric layer 5 is etched away using a photolithography technique and a plasma etching technique to form a trench 6 (see FIG. 8). The plasma etching is terminated on the surface of the P-type silicon semiconductor wafer 1. The width of the "groove 6" depends on the design principles of the integrated circuit. In the deep sub-micron field, the width of the "groove 6" is between about 0.18 and 0.4 microns. Generally, the "first dielectric layer 5" is a miscellaneous doped silicon dioxide or undoped dioxide formed by using a low pressure chemical vapor deposition (LPCVD) method. Sand (Undoped Silicon Dioxide), the reaction gas is TetraEthOxySilane (TEOS) or Silane, the reaction temperature is between 650 and 750 ° C, and the reaction pressure is between 0.2 and 0.4 torr The thickness is between P 2000 and 4000 Angstroms. It should be particularly noted that the Lithography Photoresist Pattern forming the 1 ** groove 6 ′ is a traditional Reversed-Tone pattern that forms the _pole of a metal-oxygen half field effect transistor. For the plasma etching of the "first dielectric layer 5", magnetic field enhanced active ion plasma uranium engraving technology (Magnetic Enhanced Reactive Ion-Etching; MERIE) or electron cyclotron resonance electrowinning can be used. _ (Electron_Cyclotron. Resonance ΈΟΙ), or the traditional Reactive Ion Etching (RIE) technology, in the field of sub-micron technology or deep sub-micron field, generally use magnetic field enhanced active ion type Plasma uranium engraving, the plasma reaction gas is fluorine-based gases such as CF4 and CHF3 with a small amount of argon gas (Argon). b— II —ί i- ··. I1-ί-I --- 11 Is I—I 1 — 1- · * '* (Please read the precautions on the back before filling this page) The paper size is in China National rate (CNS). A4 specifications. (.210 X_ 2 + 97 mm :) A7 B7 Consumer Cooperation Du Yin of the Central Bureau of Standards of the Ministry of Economic Affairs. 5. Description of Invention () Now refer to Figure 9. Then, a gate oxide layer 7 (Gate Oxide) of the metal oxide half field effect transistor is formed. Next, the first dielectric layer 5 ′ is used as an Ion Implantation Protection Mask, and ion implantation is used. Technology (Ion Implantation) performs "Channel Doping 9" in the "groove 6" to form a doping region 11 to adjust the threshold voltage of the gold-oxygen half field effect transistor (Threshold Voltage). The "gate oxide layer 7" is formed by thermally oxidizing the surface of the P-type silicon semiconductor wafer 1 with an oxidation temperature between 900 and 1000 ° C and a thickness between 80 to 160 angstroms. In the "channel doping 9", the ion species is boron atom (Bll), the ion cloth dose is between 1E11 and 1E13 atoms / cm2, and the ion cloth energy is between 10 and 30 Kev. . Reference is now made to FIGS. 10, 11 and 12. Next, a layer of polysilicon 13 and a titanium metal layer 14 (Metal) are deposited, and the "polysilicon 13" fills the "groove 6", as shown in FIG. Then, the "multicrystalline silicon 13" on the surface of the "first dielectric layer" is thermally oxidized in a high temperature environment to form a polysilicon dioxide 14. There is a portion of the "polycrystalline silicon 13A" which is not oxidized in the groove 6 ", and the hydrofluoric acid etching solution is used to remove the ^ polycrystalline silicon oxide 14", and in the 1r groove 0 "" Is retained in the "complex silicon 13A" to form a buried complex crystal gate 13A (Recessed Polfsilicon Gate), as shown in Figure 1 ~ 1. Next, the "polycrystalline silicon oxide 14A" is removed by using a hydrofluoric acid etching solution immediately, and the "1 polycrystalline silicon 13A" is retained in the "groove 6" to form a gold-oxygen half field effect electricity The buried polysilicon gate 13A (Recessed Polysilicon Gate) is shown in Figure 12. The "composite sand 13" is usually formed by the In-Situ Phosphorus Doped technology. The reaction method is a low-pressure chemical vapor deposition method. The reaction gas is a mixed gas of PH3, SiH4 and N2. The temperature is between 520 and 580 ° C, and the thickness is between 1000 and 3000 angstroms. .-Now refer to Figures 13 and 14. Next, the first dielectric layer 5Aj is removed to expose the "buried polycrystalline silicon gate 13A", as shown in FIG. 13, and an N-light of a gold-oxygen half field-effect transistor is formed by using ion implantation technology. Connect the lightly doped source / drain 15 as shown in Figure 14. The "first dielectric layer 5A" is usually removed by using a dilute hydrogen acid. The ion type of the "N-lightly doped source / drain 15" is phosphorus atom (P31), the ion cloth dose is between 1E13 and 3E14 atoms / cm2, and the ion cloth energy is between 20 and Between 40 Kev. (Please read the precautions on the back before filling in this page.) The size of the paper used for this edition must be in accordance with China's National Standard (CNS) A4 (210X297 mm). Printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs B7 V. Description of the invention () Now refer to Figure 15 and Figure 16. Next, a second dielectric layer 17 (Second Dielectric) is formed, and the "second dielectric layer 17" is subjected to vertical unidirectional etch-back using a plasma etching technique to A second dielectric layer sidewall 17 (Second Dielectric Spacer) is formed on the side of the multi-layered silicon gate 13A ″, as shown in FIG. 15. Finally, the N + heavily doped source / drain 19 of the metal-oxide half field-effect transistor is formed by ion implantation technology, as shown in Figure 16. The method disclosed in the present invention utilizes the conventional concept of polycrystalline silicon thermal oxidation (CMnnal Oxidation), and cooperates with the method of p groove 6 ′ to form a buried polysilicon gate 13A (Recessed Polysilicon Gate). The "channel doping" is limited to the channel region (ChannelRegion). Therefore, when a deep sub-micron metal-oxide half field effect transistor is manufactured and a very high doping concentration is required in the "channel region", the silicon semiconductor outside the channel region The impurity concentration of the wafer will not increase, so the junction leakage and junction capacitance can be reduced, and a gold-oxygen half field-effect transistor with a more electric property is obtained. Therefore, after the formation of the "N + heavily doped source / drain 19", an N-channel metal-oxygen half-field-effect transistor with low junction leakage (Low Junction Leakage) and low junction capacitance (Low Junction Capacitance) is formed. The crystals were completed in osmium. Naturally, the method of the invention can also be extended to the manufacture of integrated circuits of P-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) and complementary metal-oxide-semiconductor half-field-effect transistor (CMOSFET). The second dielectric layer 17 ′ is usually an undoped silicon dioxide (Undoped Silicon Dioxide) formed by a low-pressure chemical vapor deposition method, and the reaction gas is TetraEthOxySilane (TEOS), The reaction temperature is between 650 and 750 ° C, the reaction pressure is between 0.2 and 0.4 tOlt, and the thickness is between 1000 and 3000 Angstroms. The same applies to the "second dielectric layer 17" Vertical unidirectional etchback can use magnetic field-enhanced reactive ion plasma etching technology or electron cyclotron resonance electrowinning etching technology, or traditional reactive ion plasma etching technology, and in the field of sub-micron technology Usually, magnetic field-enhanced active ion plasma uranium engraving is used, and the plasma reaction gas is fluorine-based gases such as CF4 and CHF3 with a small amount of argon gas (Argon). The "N + heavily doped source / drain 19" uses arsenic atoms (As75), and its ion cloth dose is between 1E15 and 5E16 atoms / cm², and its ion cloth energy is between 30 and Between 100 Kev.
本紙》;尺束多用:中固國家，择準.(..CNS A4说資（.210X.297公釐.V (請先閲讀背面之注意事項再填寫本頁) -'5 A7 B7 五、發明説明（） 完成所述金氧半場效電晶體的製造後，可以巧用標準製程形成接觸窗（Contact Hole)、第一層金屬連線（First Level Metallnterconnection)、介層孔（Via Hole) 和第二層金屬連線（Second Level Metal Interconnection)，以形成金氧半場效電晶體 積體電路。所述第一層金屬連線通常是以鈦、氮化鈦、鎢和鋁合金爲材料，並且， 所述『第一層金屬連線』跨過所述接觸窗跟所述金氧半場效電晶體之源極/汲極 (Source/Drain)作電性接觸。所述第二層金屬連線通常也是以鈦、氮化欽、鶴和 鋁合金爲材料，並且，『第二層金屬連線』跨過所述介層孔跟所述第一層金屬連線 作電性接觸》"Paper"; multi-purpose ruler: Zhonggu country, select the right (..CNS A4 said capital (.210X.297mm.V (please read the precautions on the back before filling out this page) -'5 A7 B7 V. Description of the invention () After the fabrication of the metal-oxide half-field effect transistor is completed, a standard process can be used to form a contact hole, a first level metal connection, a via hole, and a via hole. The second layer of metal connection (Second Level Metal Interconnection) to form a metal oxide half field effect transistor body circuit. The first layer of metal connection is usually made of titanium, titanium nitride, tungsten and aluminum alloy, and The "first layer metal connection" makes electrical contact with the source / drain of the metal-oxygen half field effect transistor across the contact window. The second layer metal connection It is usually also made of titanium, titanium nitride, crane, and aluminum alloy, and the "second layer metal connection" makes electrical contact with the first layer metal connection across the interlayer hole. "
以上係利用最佳實施例來闌述本發明，而非限制本發明，並且，熟知半導於坊 藝之人士皆能明瞭，適當而作些微的改變及調整，仍將不失本發明之g義所 不脫離本發明之精神和範圍。 JiS (请先閱讀背面之注意事項再填寫本頁) M濟部中失樣準局貝工消費合作社印» 本纸張尺度適用中國國家標準(CNS ) A4规格(2丨〇><297公則The above is a description of the present invention by using the best embodiment, rather than limiting the present invention, and those who are familiar with semi-conducted arts will understand that appropriate changes and adjustments will still be made without losing the g of the present invention. The meaning does not depart from the spirit and scope of the present invention. JiS (Please read the precautions on the back before filling out this page) Printed by the Ministry of Economic Affairs of the People's Republic of China Sample Printing Co., Ltd. Shellfish Consumer Cooperatives »This paper size applies to China National Standard (CNS) A4 specifications (2 丨 〇 > < 297 Rule