JPS6027133A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6027133A JPS6027133A JP58135561A JP13556183A JPS6027133A JP S6027133 A JPS6027133 A JP S6027133A JP 58135561 A JP58135561 A JP 58135561A JP 13556183 A JP13556183 A JP 13556183A JP S6027133 A JPS6027133 A JP S6027133A
- Authority
- JP
- Japan
- Prior art keywords
- gold
- semiconductor substrate
- junction
- heavy metal
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 229910001385 heavy metal Inorganic materials 0.000 claims abstract description 13
- 238000010438 heat treatment Methods 0.000 claims abstract description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 19
- 239000010931 gold Substances 0.000 abstract description 19
- 229910052737 gold Inorganic materials 0.000 abstract description 19
- 238000009792 diffusion process Methods 0.000 abstract description 14
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 5
- 238000007740 vapor deposition Methods 0.000 abstract description 5
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 239000013078 crystal Substances 0.000 abstract 1
- 239000010453 quartz Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thyristors (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体装置の製造方法にかかシ、々くにＰＮ
接合のライフタイムを容易に制御できる。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to a method for manufacturing a semiconductor device.
Bond lifetime can be easily controlled.
製法に関する。Regarding the manufacturing method.
従来よシ高速スイッチング用の半導体装置を製ｉするに
轟たシ、ベース層のライフタイムを制御することが必要
である。この２イアタイムの制御を実現するため、ＰＮ
接合を形成した後に、例えば、半導体基板の表面に金を
蒸着して熱処理して金を拡散し、ライフタイムを制御し
ていた。しかしながら、このような半導体装置の製法で
は、ＰＮ接合形成後に酸化膜除去、全被着、金拡散、王
水処理というめんどうな工程を実施する必要があった。Conventionally, in order to manufacture semiconductor devices for high-speed switching, it is necessary to control the lifetime of the base layer. In order to realize this two-ear time control, the PN
After forming a bond, for example, gold is deposited on the surface of a semiconductor substrate and heat treated to diffuse the gold, thereby controlling the lifetime. However, in such a method for manufacturing a semiconductor device, it is necessary to perform the troublesome steps of oxide film removal, full deposition, gold diffusion, and aqua regia treatment after forming the PN junction.
本発明の目的は、かかる手間を省いた有効な半導体装置
の製造方法を提供することにある。An object of the present invention is to provide an effective method for manufacturing a semiconductor device that eliminates such labor and effort.
本発明の特徴は、少なくとも一つのＰＮ接合を有し、か
つ重金属拡散を伴なう半導体装置を製造する際、ＰＮ接
合を有する半導体基板のとなシに、重金属を被着させた
別の半導体基板を並べて熱処理することによシ、前記Ｐ
Ｎ接合を有する半導体基板に重金属拡散したことにある
。A feature of the present invention is that when manufacturing a semiconductor device having at least one PN junction and accompanied by heavy metal diffusion, a semiconductor device having a heavy metal deposited on the side of a semiconductor substrate having a PN junction is manufactured. By arranging the substrates and heat-treating them, the P
This is due to the diffusion of heavy metals into a semiconductor substrate having an N junction.
これにより、ＰＮ接合を形成する拡散層、特にベース層
の２イフタイムを５〜２０ ｐｓｅｃに制御することが
でき、かつ全被着、王水処理の工程を省くことができる
。Thereby, the 2-if time of the diffusion layer forming the PN junction, especially the base layer, can be controlled to 5 to 20 psec, and the entire deposition and aqua regia treatment steps can be omitted.
以下、図面によシ本発明を説明する。The present invention will be explained below with reference to the drawings.
第１図（ａ）７いし第１図（ｆ）は従来の半導体装置の
製造方法を工程順に示すもので、第１図（ａ）において
、Ｎ型半導体基板１を準備する。第１図（ｂ）において
、不純物の拡散によシ、Ｎ型半導体基板１にｒ層２と絶
層２′とを形成した後、表面に酸化膜３を形成する。次
に第１図（Ｃ）において、酸化膜３を除去後、半導体基
板１の例えばＰ土層主表面に金４を蒸着する。次に第１
図（ｄ）において、熱処理を施こして金拡散を行いベー
ス層に金５を拡散すると共に、王水処理を行い表面に付
着した残シの金４を除去する。次に第１図（ｅ）で、再
び半導体基板１の全面を酸化膜６で被覆し、第１図（ｆ
）でＰＲ技術によシミ極を設ける部分の酸化膜６を除去
する。FIGS. 1(a) to 1(f) show a conventional method for manufacturing a semiconductor device in order of steps. In FIG. 1(a), an N-type semiconductor substrate 1 is prepared. In FIG. 1(b), after an r layer 2 and an insulating layer 2' are formed on an N-type semiconductor substrate 1 by diffusion of impurities, an oxide film 3 is formed on the surface. Next, in FIG. 1C, after removing the oxide film 3, gold 4 is deposited on the main surface of the P soil layer of the semiconductor substrate 1, for example. Next, the first
In Figure (d), heat treatment is performed to diffuse gold into the base layer, and at the same time, aqua regia treatment is performed to remove residual gold 4 adhering to the surface. Next, as shown in FIG. 1(e), the entire surface of the semiconductor substrate 1 is again covered with an oxide film 6, and as shown in FIG.
), the oxide film 6 in the portion where the stain electrode is to be provided is removed by PR technology.
第２図は従来の半導体装置の製造工程中の重金属拡散の
実施状態の略図を示すもので、既に拡散法によ多形成さ
れたＰＮ接合を有し、かつｔ面に金蒸着された半導体基
板７を石英製ボート８に並べて石英製炉芯管９の中に挿
入して熱処理して金拡散をしている。Figure 2 shows a schematic diagram of the implementation state of heavy metal diffusion during the manufacturing process of a conventional semiconductor device, and shows a semiconductor substrate that already has multiple PN junctions formed by the diffusion method and has gold vapor deposited on the t-plane. 7 are arranged in a quartz boat 8, inserted into a quartz furnace core tube 9, and heat-treated to diffuse gold.
第３図は本発明一実施例による重金属拡散の実施状態の
略図を示すもので、第３図においては、既に拡散法によ
シ形成され、かつ酸化膜除去された半導体基板７′とあ
らかじめ金蒸着して用意された半導体基板７′と同径の
半導体基板１０を交互に並べて、石英製炉芯管９の中に
挿入して熱処理して金拡散をしている。FIG. 3 shows a schematic diagram of a state in which heavy metal diffusion is carried out according to an embodiment of the present invention. In FIG. Semiconductor substrates 7' prepared by vapor deposition and semiconductor substrates 10 having the same diameter are arranged alternately, inserted into a quartz furnace core tube 9, and heat-treated to diffuse gold.
本発明での重金属拡散により、ＰＮ接合を有する半導体
基板への金蒸着を実施するととなく、ＰＮ接合ベース層
のライフタイムを５〜２０μｓｅｃに制御することがで
き、かつ金拡散後の王水処理も省くことができ、極めて
製造工程が簡略にできる。Due to heavy metal diffusion in the present invention, the lifetime of the PN junction base layer can be controlled to 5 to 20 μsec without performing gold vapor deposition on a semiconductor substrate having a PN junction, and aqua regia treatment after gold diffusion is performed. This can greatly simplify the manufacturing process.
第１図（ａ）ないし第１図（ｆ）は従来の半導体装置の
製造方法を工程率に示したものである。第２図は従来の
半導体装置の製造工程中の重金属拡散の実施状態を示し
た図である。第３図は本発明一実施例による重金属拡散
の実施状態を示した図である。
１・・・・・・半導体基板、２・・・・・・を層、２′
・・・・・・炉層、３・・・・・・酸化膜、４・・・・
・・金蒸着層、５・・・・・・金、６・・・・・・酸化
膜、７・・・・・・金蒸着層付き半導体基板、７′・・
・・・・半導体基板、８・・・・・・石英製ボート、９
・・・・・・石英製炉芯管、１０・・・・・・金蒸着層
付き半導体基板。
第１図 第２図FIGS. 1(a) to 1(f) show the process rate of a conventional semiconductor device manufacturing method. FIG. 2 is a diagram showing the implementation state of heavy metal diffusion during the manufacturing process of a conventional semiconductor device. FIG. 3 is a diagram showing an implementation state of heavy metal diffusion according to an embodiment of the present invention. 1... Semiconductor substrate, 2... Layer, 2'
... Furnace layer, 3 ... Oxide film, 4 ...
...Gold vapor deposited layer, 5...Gold, 6...Oxide film, 7...Semiconductor substrate with gold vapor deposited layer, 7'...
... Semiconductor substrate, 8 ... Quartz boat, 9
...Quartz furnace core tube, 10...Semiconductor substrate with gold vapor deposition layer. Figure 1 Figure 2
Claims (1)
拡散を行なう半導体装置の製造方法において、前記ＰＮ
接合を有した半導体基板のとなわに、重金属を被着した
別の半導体基板を並べて熱処理して重金属を前記半導体
基板に拡散することを特徴とする半導体装置の製造方法
。In a method of manufacturing a semiconductor device in which heavy metal is diffused into a semiconductor substrate having at least one PN junction, the PN junction
1. A method of manufacturing a semiconductor device, which comprises arranging another semiconductor substrate coated with a heavy metal next to a semiconductor substrate having a bond and subjecting the semiconductor substrate to heat treatment to diffuse the heavy metal into the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58135561A JPS6027133A (en) | 1983-07-25 | 1983-07-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58135561A JPS6027133A (en) | 1983-07-25 | 1983-07-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6027133A true JPS6027133A (en) | 1985-02-12 |
Family
ID=15154685
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58135561A Pending JPS6027133A (en) | 1983-07-25 | 1983-07-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6027133A (en) |
-
1983
- 1983-07-25 JP JP58135561A patent/JPS6027133A/en active Pending
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