JPH02208929A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH02208929A
JPH02208929A JP2946789A JP2946789A JPH02208929A JP H02208929 A JPH02208929 A JP H02208929A JP 2946789 A JP2946789 A JP 2946789A JP 2946789 A JP2946789 A JP 2946789A JP H02208929 A JPH02208929 A JP H02208929A
Authority
JP
Japan
Prior art keywords
oxide layer
doped oxide
substrate
impurity
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2946789A
Other languages
Japanese (ja)
Inventor
Kazuki Kakuno
客野 和樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP2946789A priority Critical patent/JPH02208929A/en
Publication of JPH02208929A publication Critical patent/JPH02208929A/en
Pending legal-status Critical Current

Links

Landscapes

  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To assure the impurity diffused amount on a silicon semiconductor substrate while thinning a protective film by a method wherein the impurity is diffused in the state of a doped oxide layer covered with a covering layer. CONSTITUTION:An opening part 3 is formed in an oxide film 12 formed on the surface of a silicon semiconductor substrate 11 and then a doped oxide layer 14 containing phosphorus as an impurity is formed in the thickness required for attaining the specified diffusion amount. Next, a covering layer 20 containing no impurity is formed and then heat-treated to form a diffused region 15 in the substrate 11. At this time, the doped oxide layer 14 being covered with the covering layer 20, sufficient amount of phosphorus is diffused in the substrate 11. Furthermore, during the process removing the later covering layer 20 as well as the doped oxide layer 14 and the oxide film 12 in the opening part 13 by etching process, the effect of side etching in the etching process after diffusion can be lessened due to the relatively thin protective film 19 comprising the oxide film 12 and the doped oxide layer 14.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は半導体装置の製造工程における不純物の拡散技
術に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to impurity diffusion technology in the manufacturing process of semiconductor devices.

[従来の技術] 半導体装置の製造中にはシリコン半導体基板の所定部分
にリン等の不純物を拡散させる拡散工程があり、その拡
散技術としてはドープトオキサイト層を基板上に形成し
てこれを拡散ソースとして用いる方法が知られている。
[Prior art] During the manufacture of semiconductor devices, there is a diffusion process in which impurities such as phosphorus are diffused into predetermined portions of a silicon semiconductor substrate.The diffusion technique involves forming a doped oxide layer on the substrate and diffusing it. A method of using it as a source is known.

すなわち、第3図に示すように、S i 02膜2を一
部除去して開口部3が形成されたSi基板1上にリンを
含有したドープトオキサイト層4を形成し、この後熱処
理によりドープトオキサイト層4中のリンを拡散させS
i基板1に拡散領域5を形成し、この後開口部3のオキ
サイド層4をエツチング処理により除去していた。
That is, as shown in FIG. 3, a doped oxide layer 4 containing phosphorus is formed on a Si substrate 1 in which an opening 3 is formed by partially removing the Si 02 film 2, and then a doped oxide layer 4 containing phosphorus is formed by heat treatment. By diffusing phosphorus in the doped oxide layer 4, S
A diffusion region 5 was formed on the i-substrate 1, and then the oxide layer 4 in the opening 3 was removed by etching.

[発明が解決しようとする課題] 上記したような拡散技術にあっては、熱処理を施したと
きにドープトオキサイト層4から雰囲気中へ多量にリン
が拡散してしまうため、基板1へのリンの拡散量を所定
の量に維持しようとするにはドープトオキサイト層4を
厚くし、ドープトオキサイト層40基板界面近傍部分か
らの基板1中への拡散を保障しなければならなかった。
[Problems to be Solved by the Invention] In the above-described diffusion technology, a large amount of phosphorus diffuses into the atmosphere from the doped oxide layer 4 when heat treatment is performed, so that phosphorus is not absorbed into the substrate 1. In order to maintain the amount of diffusion at a predetermined level, it was necessary to increase the thickness of the doped oxide layer 4 to ensure that the doped oxide layer 40 diffuses into the substrate 1 from the vicinity of the substrate interface.

このため、シリコン基板lの保護膜9(Si02膜2及
びオキサイド層4)が必要以上に厚くなってしまうとい
う問題があった。
Therefore, there was a problem in that the protective film 9 (Si02 film 2 and oxide layer 4) of the silicon substrate 1 became thicker than necessary.

また、保護膜9が厚くなってしまう結果、拡散後のエツ
チング処理においてサイドエツチングの影響が大きくな
って、第4図に示すように、保護層9の開口部3の周縁
のステップカバレージが悪くなり、以後の製造工程にお
いて積層層の段切れの原因となってしまうという問題が
あった。この現象は不純物をリンとした場合には特に顕
著である。すなわち、リンの拡散後の酸化膜2とオキサ
イド層4とのリン含有濃度は、オキサイド層4と酸化膜
2との界面部分(第4図中の網目線部分6)が高くなり
、酸化膜2の基板界面側部分(第4図中の部分7)は基
板1中への拡散によフて低く、また、オキサイド層4の
表面側部分(第4図中の部分8)は雰囲気中への拡散に
よって低くなっている。このため、公知のようにリン含
有のガラス層はその含有量に応じてエツチング速度が大
きくなることから、より一層ステップカバレージの悪化
が顕著となる。
Furthermore, as a result of the thicker protective film 9, the influence of side etching increases in the etching process after diffusion, resulting in poor step coverage around the periphery of the opening 3 in the protective layer 9, as shown in FIG. However, there is a problem in that it may cause breakage of the laminated layers in the subsequent manufacturing process. This phenomenon is particularly remarkable when the impurity is phosphorus. That is, the phosphorus content concentration of the oxide film 2 and the oxide layer 4 after phosphorus diffusion becomes higher at the interface between the oxide layer 4 and the oxide film 2 (the mesh line part 6 in FIG. 4), and The portion on the substrate interface side (portion 7 in FIG. 4) is low due to diffusion into the substrate 1, and the surface side portion of the oxide layer 4 (portion 8 in FIG. 4) is low due to diffusion into the atmosphere. It is lowered due to diffusion. For this reason, as is well known, the etching rate of a glass layer containing phosphorus increases depending on its content, so that the deterioration of step coverage becomes even more remarkable.

本発明は上記従来の事情に鑑みなされたもので、従来の
問題を合理的に解決する半導体装置の製造方法を提供す
ることを目的とする。
The present invention has been made in view of the above-mentioned conventional circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor device that rationally solves the conventional problems.

[課題を解決するための手段] 本発明に係る半導体装置の製造方法は、シリコン半導体
基板の酸化膜に開口部を形成する工程と、当該酸化膜上
から不純物を含むドープトオキサイト層を形成する工程
と、当該ドープトオキサイト層上から不純物を含まない
被覆層を形成する工程と、熱処理を施してドープトオキ
サイト層中の不純物を開口部からシリコン半導体基板中
に拡散させる工程と、被覆層を除去した後にエツチング
処理を行って開口部分のドープトオキサイト層及び酸化
膜を除去する工程とを備えたことを特徴とする。
[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes a step of forming an opening in an oxide film of a silicon semiconductor substrate, and forming a doped oxide layer containing an impurity on the oxide film. a step of forming an impurity-free covering layer on the doped oxide layer; a step of performing heat treatment to diffuse the impurities in the doped oxide layer into the silicon semiconductor substrate from the opening; and a step of forming the covering layer. The method is characterized by comprising a step of performing an etching process after removing the doped oxide layer and the oxide film in the opening portion.

[作用コ 熱処理を施してドープトオキサイト層中の不純物をシリ
コン半導体基板中に拡散させる工程において、このドー
プトオキサイト層を被覆層で覆って両者の界面側への拡
散を抑制し、これによって基板側への拡散を従来に比し
て大幅に促進する。
[Operation] In the step of diffusing impurities in the doped oxide layer into the silicon semiconductor substrate by applying heat treatment, this doped oxide layer is covered with a coating layer to suppress diffusion toward the interface between the two, thereby This greatly promotes sideward diffusion compared to conventional methods.

そして、これによって酸化膜とオキサイド層とからな多
基板の保護膜を薄いものとしてサイドエツチングの影響
を少なくすると共に、保護膜中の不純物含有濃度を基板
界面から離れるにしたがって高いものとしてエツチング
速度が基板界面から離れるにしたがって大きくなるよう
にし、開口部周縁のステップカバレージを良好なものと
する。
As a result, the protective film for multiple substrates consisting of oxide films and oxide layers is thinned to reduce the effects of side etching, and the impurity concentration in the protective film increases as it moves away from the substrate interface, increasing the etching rate. It increases in size as it moves away from the substrate interface to provide good step coverage around the periphery of the opening.

[実施例コ 本発明に係る半導体装置の製造方法を第1図及び第2図
に示す実施例に基づいて具体的に説明する。
[Example 2] A method for manufacturing a semiconductor device according to the present invention will be specifically explained based on an example shown in FIGS. 1 and 2.

まず、シリコン半導体基板110表面に生成した酸化膜
(Si02膜)12の所望の部分にレジストを設けてエ
ツチングし、5i02膜12に開口部13を形成する。
First, a resist is provided on a desired portion of the oxide film (Si02 film) 12 formed on the surface of the silicon semiconductor substrate 110 and etched to form an opening 13 in the 5i02 film 12.

次いで、CVD法等の公知の方法によりSiO2膜12
上から不純物としてリンを含むドープトオキサイ)!1
4を所定の拡散量を得るに必要な厚さだけ形成し、この
ドープトオキサイト層14により開口部13及び5i0
2PA12を覆う。
Next, the SiO2 film 12 is formed by a known method such as the CVD method.
Doped Oxai containing phosphorus as an impurity from above)! 1
4 is formed to a thickness necessary to obtain a predetermined amount of diffusion, and this doped oxide layer 14 forms openings 13 and 5i0.
Cover 2PA12.

次いで、CVD法等の公知の方法によりドープトオキサ
イト層14上に不純物を含まない被覆層(例えば、Si
O2層)20を形成する。
Next, an impurity-free coating layer (for example, Si
An O2 layer) 20 is formed.

次いで、熱処理を施してドープトオキサイト層14中の
リンを開口部13からシリコン半導体基板11中に拡散
させ、基板11中に拡散領域16を形成する。このとき
、ドープトオキサイト層14は被覆層20で覆われてい
るため基板11側への拡散が促進され、基板11中には
十分な量のリンが拡散する。そして、リンはドープトオ
キサイト層14中にも残留すると共に5i02膜12中
にも拡散するが、被覆層20の界面側では拡散が抑制さ
れ、基板11の界面側では拡散が自由になされるため、
5i02膜12とオキサイドFi14とから成る保護膜
19に含有されるリンの濃度は基板11の界面から離れ
るにしたがって高くなる。
Next, heat treatment is performed to diffuse phosphorus in the doped oxide layer 14 into the silicon semiconductor substrate 11 from the opening 13, thereby forming a diffusion region 16 in the substrate 11. At this time, since the doped oxide layer 14 is covered with the coating layer 20, diffusion toward the substrate 11 is promoted, and a sufficient amount of phosphorus is diffused into the substrate 11. Phosphorus remains in the doped oxide layer 14 and also diffuses into the 5i02 film 12, but the diffusion is suppressed on the interface side of the coating layer 20 and is allowed to diffuse freely on the interface side of the substrate 11. ,
The concentration of phosphorus contained in the protective film 19 composed of the 5i02 film 12 and the oxide Fi 14 increases as the distance from the interface of the substrate 11 increases.

次いで、フッ酸溶液等による全面エツチングで被覆層2
0を除去する。
Next, the covering layer 2 is etched using a hydrofluoric acid solution or the like.
Remove 0.

次いで、開口部13を除いた部分にレジストを設けてエ
ツチング処理を行い、開口部分13のドープトオキサイ
ト層14及び5i02膜12を除去する。このとき、5
i02膜12とオキサイド層14とから成る保護膜19
は比較的薄いためサイドエツチングの影響は少なく、且
つ、保護膜19に含有されるリンの濃度分布により基板
11の界面から離れるにしたがって大きな速度でエツチ
ングされ、開口部13の固締のステップカバレージが第
2図に示すように表面側に開いた良好なものとなる。
Next, a resist is provided in the area other than the opening 13 and an etching process is performed to remove the doped oxide layer 14 and the 5i02 film 12 in the opening 13. At this time, 5
A protective film 19 consisting of an i02 film 12 and an oxide layer 14
Since the protective film 19 is relatively thin, the influence of side etching is small, and due to the concentration distribution of phosphorus contained in the protective film 19, it is etched at a higher rate as it moves away from the interface of the substrate 11, and the step coverage of the fixing of the opening 13 is reduced. As shown in FIG. 2, the result is a good one with an open surface.

そしてこの後、半導体装置の製造に必要な工程を行い、
所定の層を積層する。
After this, the steps necessary for manufacturing the semiconductor device are performed.
Stack predetermined layers.

[効果コ 本発明によれば、被覆層で覆った状態で不純物拡散を行
うため、ドープトオキサイト層を比較的薄くしてもシリ
コン半導体基板への不純物拡散量を十分確保することが
でき、シリコン半導体基板の保護膜を薄くすることがで
きる。このため、拡散後のエツチング処理においてサイ
ドエツチングの影響を減少させることができ、更にまた
、不純物としてリンを用いた場合には基板界面から離れ
るにしたがってエツチング速度を高めることができ、段
切れが生じない良好なステップカバレージを得ることが
できる。
[Effects] According to the present invention, since impurity diffusion is performed while covered with a coating layer, a sufficient amount of impurity diffusion into the silicon semiconductor substrate can be ensured even if the doped oxide layer is made relatively thin. The protective film of the semiconductor substrate can be made thinner. For this reason, the influence of side etching can be reduced in the etching process after diffusion, and furthermore, when phosphorus is used as an impurity, the etching rate can be increased as the distance from the substrate interface increases, causing step breaks. Not able to get good step coverage.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例に係る断面図、第2図はその
要部の断面図、第3図は従来例に係る断面図、第4図は
その要部の断面図である。 11はシリコン半導体基板、 12は5i02膜、 13は開口部、 14はドープトオキサイト層、 15は拡散領域、 20は被覆層である。
FIG. 1 is a sectional view of an embodiment of the present invention, FIG. 2 is a sectional view of a main part thereof, FIG. 3 is a sectional view of a conventional example, and FIG. 4 is a sectional view of a main part thereof. 11 is a silicon semiconductor substrate, 12 is a 5i02 film, 13 is an opening, 14 is a doped oxide layer, 15 is a diffusion region, and 20 is a covering layer.

Claims (1)

【特許請求の範囲】[Claims] シリコン半導体基板の酸化膜に開口部を形成する工程と
、当該酸化膜上から不純物を含むドープトオキサイト層
を形成する工程と、当該ドープトオキサイト層上から不
純物を含まない被覆層を形成する工程と、熱処理を施し
てドープトオキサイト層中の不純物を開口部からシリコ
ン半導体基板中に拡散させる工程と、被覆層を除去した
後にエッチング処理を行って開口部分のドープトオキサ
イト層及び酸化膜を除去する工程とを備えたことを特徴
とする半導体装置の製造方法。
A step of forming an opening in an oxide film of a silicon semiconductor substrate, a step of forming a doped oxide layer containing an impurity over the oxide film, and a step of forming a covering layer not containing an impurity over the doped oxide layer. Then, heat treatment is performed to diffuse impurities in the doped oxide layer from the opening into the silicon semiconductor substrate, and after the covering layer is removed, etching is performed to remove the doped oxide layer and oxide film in the opening. A method for manufacturing a semiconductor device, comprising the steps of:
JP2946789A 1989-02-08 1989-02-08 Manufacture of semiconductor device Pending JPH02208929A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2946789A JPH02208929A (en) 1989-02-08 1989-02-08 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2946789A JPH02208929A (en) 1989-02-08 1989-02-08 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02208929A true JPH02208929A (en) 1990-08-20

Family

ID=12276907

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2946789A Pending JPH02208929A (en) 1989-02-08 1989-02-08 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02208929A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5485034A (en) * 1992-04-28 1996-01-16 Kabushiki Kaisha Toshiba Semiconductor device including bipolar transistor having shallowed base

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52153373A (en) * 1976-06-15 1977-12-20 Toshiba Corp Preparation of semiconductor device
JPS6417425A (en) * 1987-07-13 1989-01-20 Matsushita Electronics Corp Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52153373A (en) * 1976-06-15 1977-12-20 Toshiba Corp Preparation of semiconductor device
JPS6417425A (en) * 1987-07-13 1989-01-20 Matsushita Electronics Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5485034A (en) * 1992-04-28 1996-01-16 Kabushiki Kaisha Toshiba Semiconductor device including bipolar transistor having shallowed base

Similar Documents

Publication Publication Date Title
US5397733A (en) Method for the construction of field oxide film in semiconductor device
JPH01199456A (en) Manufacture of semiconductor integrated circuit
US4030952A (en) Method of MOS circuit fabrication
JPH02208929A (en) Manufacture of semiconductor device
JPS5976472A (en) Manufacture of semiconductor device
US3807038A (en) Process of producing semiconductor devices
JPH0258252A (en) Manufacture of semiconductor device
JPS6387741A (en) Manufacture of semiconductor device
JPS6224617A (en) Epitaxial growth method
JPH027558A (en) Semiconductor device and manufacture thereof
JPH0587016B2 (en)
KR100364416B1 (en) Isolation method of semiconductor device
JP3282242B2 (en) Method for diffusing impurities and method for controlling reflow of doped oxide film
JPH06163450A (en) Manufacture of semiconductor device
JP3282265B2 (en) Method for manufacturing semiconductor device
JPS6074613A (en) Manufacture of semiconductor device
JPH01135016A (en) Manufacture of semiconductor device
JPH05291167A (en) Manufacture of semiconductor device
JPS5965448A (en) Manufacture of semiconductor device
JPH0542817B2 (en)
JPH03253033A (en) Manufacture of semiconductor device
JPH0334322A (en) Manufacture of semiconductor device
JPH01283820A (en) Manufacture of semiconductor device
JPH04162675A (en) Semiconductor device and manufacture thereof
JPS61170024A (en) Manufacture of semiconductor device