JPS60263473A - Field effect transistor - Google Patents

Abstract

PURPOSE:To realize adjustable threshold voltages and to ensoure optimum, easy operation for each chip by a method wherein a p<+> type semiconductor layer of excellent conductivity implanted with a high concentration of acceptor ions is provided, with the intermediary of a thin semi-insulating layer, on a two-dimensional electron accumulation layer along its surface interfacing with a substrate. CONSTITUTION:Electrons in an n<+> Al0.3Ga0.7As layer 5 doped with Si by modulation are diffused into an undoped GaAs layer 7, to be accumulated therein in the form of two-dimensional gas 8 of electrons. When a field is generated parallel to an interface of said layer 5 by application of a voltage across a source electrode 9 and drain electrode 10, the two-dimensional gas 8 of electrons starts travelling as high-mobility electrons. The rate of the flow of the conductive particles is subject to the voltage applied to a gate electrode 11. Application of the substrate bias voltage for a p<+> GaAs substrate 3 doped with B to the positive or negative side increases or decreases the flow rate and shifts the threshold voltage to the negative or positive side. Accordingly, the best threshold voltage for a chip may be easily chosen to ensure optimum operating conditions for the chip.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention makes it possible to adjust the threshold voltage using the substrate bias voltage. This field-effect transistor has a high-mobility two-dimensional electron layer as a channel.

(Prior Art) High electron mobility transistors using modulation doping have been proposed. Among these transistors, a field effect transistor whose threshold voltage can be adjusted by a substrate bias voltage is shown in cross-section in FIG.

In this conventional structure, 21 is an AuGe electrode for substrate bias, 22 is a semi-insulating GaAs substrate with a thickness of about 400 km, and 23 is an undoped (hereinafter referred to as undoped) AQ+p! Ga, 7AS layer, 24
Si is added to about lx10cm-3 and the thickness is about 15O
A's E M,,3Ga,,7AsR125 has a thickness of about 1
000A undoped GaAs layer 26, in this undoped GaAs layer 25, ri'-mo, 3G ao,
7 A two-dimensional electron gas accumulated at the bonding interface with the s layer 24, 27 and 28 are source and drain electrodes made of AuGe electrode layers, and 29 is a re-AQ layer below these source and drain electrodes 27 and 28. □、3 Gao、
7 A region is obtained by diffusing AuGe up to the As layer 24, and 30 is a gate electrode made of a Ti electrode layer.

In this conventionally structured field effect transistor, AQ. ,
The electrons in the 3GaO, 7As layer 24 are undoped with GaAs
The two-dimensional electron gas 26 is diffused into the layer 25 and accumulated there as a two-dimensional electron gas 2B.
A parallel electric field is applied to the interface between the undoped layer 25 and the ri''-MO, 3Ga6.7As layer 24 by applying a voltage between the drain electrode 28 and the electrons are conducted as electrons with high mobility.

In this conventional field effect transistor, the flow of conduction electrons is adjusted by the voltage applied to the gate electrode, but by applying a positive or negative bias voltage to the A II G e electrode 21 for substrate bias. This has the advantage that the flow rate of conduction electrons can be increased or decreased, and the threshold voltage can be shifted to the negative or positive side.

(Problems to be Solved by the Invention) By the way, since the semi-insulating GaAs substrate 22 is as thick as about 400 p-m as described above, the threshold voltage is set to 0. I
A bias voltage of about 200V was required to change the voltage. However, such high voltages
Since it is not suitable for integrated circuits that handle signals of the following minute voltages, field effect transistors with this conventional structure cannot be incorporated into integrated circuits and have the disadvantage of being impractical.

An object of the present invention is to provide a high electron mobility field effect transistor having a structure in which a threshold voltage can be adjusted by a substrate bias voltage as small as a power supply voltage.

(Means for Solving the Problems) The main point of this invention is to provide a V type in which a thin semi-insulating semiconductor layer is sandwiched between the substrate side of a two-dimensional electron storage layer and a highly conductive acceptor ion is added at a high concentration. The point is that a semiconductor layer is provided.

Therefore, according to the field effect transistor of the present invention, a first semiconductor layer having a large electron affinity and doped with acceptor-type impurities is provided on the upper side of the substrate, and a first semiconductor layer having a small electron affinity and containing no impurities is provided on the first semiconductor layer. a second semiconductor layer, a third semiconductor layer provided on the second semiconductor layer and doped with donor-type impurities, a fourth semiconductor layer provided above the third conductor layer and doped with no impurities; A source electrode, a drain electrode, and a gate electrode are provided on a fourth semiconductor layer, the first semiconductor layer is used as an electrode for applying a substrate bias, and the thickness of the second semiconductor layer is controlled by a minute substrate bias voltage. The fourth semiconductor layer is thin enough to accumulate two-dimensional electron gas, and the accumulated two-dimensional electrons are used as n-channel carriers.

(Function) According to the field effect transistor having such a structure, the first semiconductor layer is a highly conductive semiconductor layer doped with acceptor ions at a high concentration, and this semiconductor layer is used as an electrode for applying a substrate bias. The two semiconductor layers are thin semi-insulating semiconductor layers, and the first, second and third semiconductor layers are
Since the n-structure is formed, the thickness from the first semiconductor layer to the fourth semiconductor layer where the two-dimensional electron gas accumulates is thin, and the substrate bias voltage, which is as small as a power supply voltage of, for example, 0.5 V, can be applied to O, t V. The threshold voltage can be adjusted to a certain extent.

Furthermore, according to this structure, since the substrate bias voltage can be applied uniformly within the plane by the first semiconductor layer, it is possible to adjust the threshold voltage for each chip, and by this adjustment, the threshold voltage can be adjusted for each chip. can easily perform optimal operation.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1(A) is a cross-sectional view showing one embodiment of a field effect transistor of the present invention, and FIG. 1(B) is a diagram showing its energy band structure.

As shown in FIG. 1(A), 2 is a substrate, for example, a semi-insulating GaAs substrate. 2 is an undoped layer laminated on the substrate 11, and is, for example, an undoped GaAs layer with a thickness of about 2000 Å. 3 is a first semiconductor layer laminated on this undoped layer 2, which has high electron affinity and is doped with acceptor type impurities, and has good conductivity.
The thickness with about 3 x 10 c+a-3 added is about 5
This is a p''-GaAs layer of 00OA. This first semiconductor layer 3 is used as an electrode for applying a substrate bias as described later. 4 is laminated on this first semiconductor layer 3 and is a p"-GaAs layer with a small electron affinity. Two semiconductor layers, e.g. about 1p thick
It is a doped layer of 6°, . 5 is a third semiconductor layer (modulation doping layer) laminated on the second semiconductor layer 4 and doped with donor-type impurities having low electron affinity;
In this case, this layer 5 is made of Si with I x 10 cm-3
-AQ, Ga with a thickness of about 200A
6,7A 5 layers. Further, a layer laminated on this layer 5- is a spacer layer 6, which has a thickness of about 8 OA.
, 5 Ga, , 7 As layers. Furthermore, 7
is a fourth semiconductor layer laminated on this spacer layer 6 and having a high electron affinity; in this case, this layer 7 is an undoped GaAs layer having a thickness of about 1000 Å. Furthermore, 8 is in the undoped GaAs which is the fourth semiconductor layer 7.
This is two-dimensional electron gas accumulated on the third semiconductor layer 5 side, that is, at the junction interface with the undoped AQ o, 3Ga, 7As layer constituting the spacer layer 6. Also, 9 and l
O is an undoped GaAs layer constituting the fourth semiconductor layer 7.
2 are source and drain electrodes made of an AuGe electrode layer, and 11 is a gate electrode provided on the undoped GaAs layer 7 and made of a Ti electrode layer. Further, 12 is a high impurity concentration region provided under the source electrode 9 and the drain electrode 1O so as to reach the third semiconductor layer 5, for example, an n+- region provided by diffusing AuGe.

The energy band structure of such a structure is shown in Figure 1 (B).
Shown below. In this figure, layers corresponding to the layers shown in FIG. 1(A) are given the same numbers. As can be understood from this figure, the modulation doping layer re -Mo3
Ga,, 7 As layer electrons are undoped GaAs
The electrons are diffused into the layer 7 and accumulated as a two-dimensional electron gas 8. Therefore, in this case as well, when a voltage is applied between the source and drain electrodes 9 and 10 to apply an electric field parallel to the interface of this layer 5, this two-dimensional electron gas 8 has a high mobility. The flow rate of the conduction electrons is controlled by the gate voltage applied to the goo I electrode 11, and can be increased or Since the threshold voltage can be decreased to 11, the threshold voltage can be shifted to the negative or positive side.

This adjustment was achieved by making the thickness of the undoped second semiconductor layer 4, which is the second semiconductor layer, so thin that two-dimensional electron gas 8 is accumulated in the fourth semiconductor layer 7 even with a small substrate bias voltage, and by making the thickness of this layer 4 - n”-AQo, 3Ga provided under L
Since the 7As layer 5 and the p''-GaAs layer 3 form a pin structure, the threshold voltage of about 0.1 layer can be adjusted with a very small bias voltage of about 0.5 layer, which is about the same as the substrate voltage. You can.

In addition, in this structure, P'- which constitutes one layer in the multilayer structure
Since the GaAs layer 3 is used as the electrode for applying substrate bias, the substrate bias voltage can be applied uniformly within the surface of the semiconductor layer, so that the above-mentioned adjustment can be performed individually for each chip. Therefore, the optimum operating conditions, that is, the threshold voltage, can be easily and easily adjusted for each chip.

Note that this invention is not limited only to the embodiments described above. For example, undoped AQ, ), 3Ga, 7A
The spacer layer 6 made of the s-layer is constructed so that the two-dimensional electron gas 8 conducted in the undoped layer 7 undergoes Coulomb scattering by the Si donor ions formed in the n''-Mo30a6.7As layer 5, and its mobility decreases. Since this is a layer to avoid this, it is not necessarily a necessary layer and may be omitted.

Furthermore, the above-mentioned GaAs and AQ, , Ga0,7A
s material combination, In033Gtn7As/
InP, Ga0471n6,53As/ADo,4
．． yI nO, (1AS material may be substituted. In that case, GaAs is replaced with I n6.53Gos7A s or Ga
6.4.71n6) 3As, AQ, Gao, 7
As may be replaced with InP or AQ In As.

(Effects of the Invention) As is clear from the above description, according to the field effect transistor of the present invention, the first semiconductor layer is a highly conductive semiconductor layer doped with acceptor ions at a high concentration. It is used as an electrode for applying a substrate bias, and since the second semiconductor layer is thin and the first, second, and third semiconductor layers form a pin structure, a substrate bias voltage of about 0.5 V, for example, the power supply voltage can be applied. 0.1v
The threshold voltage can be adjusted to a certain degree.

Furthermore, according to this structure, it is possible to apply a substrate bias voltage uniformly within the plane of the first semiconductor layer, so that the threshold voltage can be adjusted for each chip, and this Optimal operation can be easily performed for each chip through adjustment.

Therefore, the field effect transistor of the present invention is suitable for use in integrated circuits such as GaAs heterojunction field effect transistors whose threshold voltages are difficult to adjust.

[Brief explanation of the drawing]

FIGS. 1(A) and 1(B) are a linear cross-sectional view showing an embodiment of a field-effect transistor of the present invention and a diagram showing its energy band structure. FIG. 2 is a sectional view showing a conventional field effect transistor whose threshold voltage can be adjusted by a substrate bias voltage. l... Substrate, 2... Impurity-free layer 3... First semiconductor layer, 4... Second semiconductor layer 5... Third semiconductor layer, 6... Spacer layer 7... Fourth semiconductor layer, 8...
Two-dimensional electron gas 9...source electrode, lO...drain electrode 11...gate electrode, 12...high impurity concentration region. Oral procedure amendment (voluntary) December 29, 1980 Manabu Shiga, Commissioner of the Patent Office 1 Display of the case 1983 Patent Application No. 119819 2 Name of the invention Field effect transistor 3 Relationship with the case of the person making the amendment Patent Applicant address (〒-105) 1-7-12 Toranomon, Minato-ku, Tokyo Name (029) Oki Electric Industry Co., Ltd. Representative Nankai Hashimoto 4 Agent 〒170 Award (98B) 5583 Address 1 Higashiikebukuro, Toshima-ku, Tokyo 20-5 Ikebukuro White House Building No. 805 Specification, Claims column, Detailed description of the invention column 6 Contents of amendments As shown in Attachment (1), the claims of the specification are as follows: correct. “Claim 1: a first semiconductor layer having a large electron affinity and doped with acceptor-type impurities on the upper side of the substrate; and a second semiconductor layer having a small electron affinity and containing no impurities, which is provided on the second semiconductor layer. , a third semiconductor layer provided on the second semiconductor layer and doped with a donor type impurity; and a third semiconductor layer provided on the upper side of the third conductor layer; a fourth semiconductor layer to which no impurities are added; and a source electrode, a drain electrode, and a gate electrode provided on the fourth semiconductor layer, the first semiconductor layer being an electrode for applying a substrate bias, and the second semiconductor layer A field effect transistor characterized in that the thickness of the fourth semiconductor layer is made thin enough to accumulate two-dimensional electron gas in the fourth semiconductor layer using a minute substrate bias voltage, and the accumulated two-dimensional electron gas is used as an n-channel carrier. 2. The field effect transistor according to claim 1, wherein the second and fourth semiconductor layers are made of GaAs, and the second and third semiconductor layers are made of GaAs. The field effect transistor according to claim 1 or 2, characterized in that the thickness of the second semiconductor layer is IILm or less.'' (2), page 5, line 12 of the same, ``Providing Correct "provided" to "J, which has a small electron affinity," and corrected "provided," in line 13 of the same page, to "J, which has a large electron affinity." (3), rAQ In As on page 11, line 5 is corrected to FMI, QzIn, L52Asj.

Claims (1)

[Claims] 1. A first semiconductor layer having a large electron affinity and doped with acceptor-type impurities on the upper side of the substrate, and a second semiconductor layer provided on the second semiconductor layer and having a small electron affinity and containing no impurities. a third semiconductor layer provided on the second semiconductor layer and doped with donor-type impurities; a fourth semiconductor layer provided above the third conductor layer and not added with impurities; and the fourth semiconductor layer. a source electrode, a drain electrode, and a gate electrode provided above, the first semiconductor layer is used as an electrode for applying a substrate bias, and the thickness of the second semiconductor layer is controlled by a minute substrate bias voltage to the fourth semiconductor layer. A field effect transistor characterized by being thin enough to accumulate two-dimensional electron gas and using the accumulated two-dimensional electron gas as an n-channel carrier. 2. The field effect transistor according to claim 1, wherein the first and fourth semiconductor layers are made of GaAs, and the second and third semiconductor layers are made of AQ GaAs. 3. The field effect transistor according to claim 1 or 2, wherein the second semiconductor layer has a thickness of 1 gm or less.