JPS6386575A - Hetero junction field effect transistor - Google Patents

Abstract

PURPOSE:To make a hetero junction field effect transistor to hold a favorable current cut-off characteristic and high mutual conductance even when gate length is short by a method wherein a first conductor layer of large electron affinity containing substantially no impurity, and a second conductor layer of small electron affinity are laminated on a semi-insulating substrate, and a thin layer region containing p-type impurities at the specified face density is formed in the neighborhood of the interface between the semiinsulating substrate and the semiconductor layer adjoining thereto. CONSTITUTION:A p-type GaAs layer 12 containing B by concentration of about 1X10<18>cm<-3> is grown at about 100Angstrom thickness on a non-doped semiinsulating GaAs substrate 11. Then a non-doped GaAs layer 13 added with no impurity is grown thereon, and an n-type Al0.3Ga0.7 As layer 14 containing Si as an impurity by 2X10<18>cm<3>, and moreover an n-type GaAs layer 15 containing Si as an impurity by about 2X10<18>cm<-3> are grown at thickness of about 300Angstrom , 500Angstrom respectively thereon. After wafer growth is completed, interelement isolation is performed excluding an element region. After then, source and drain electrodes 16, 17 are formed using metals of AuGe group, and by removing a part of the n-type GaAs layer and the n-type Al0.3Ga0.7As layer under the gate resist pattern formed by using the electron beam exposure method, a recess shape is formed. A gate electrode 18 consisting of Al/Ti is formed in the recess region thereof.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) This invention is directed to an electric field that uses a two-dimensional electron accumulation layer as a conductive channel, which is induced by a difference in electron affinity at a heterojunction interface. The present invention relates to effect transistors, and particularly to device structures that exhibit excellent current saturation characteristics and current cutoff characteristics (pinch-off characteristics) even with a short channel length.

(Prior art) A semiconductor layer containing n-type impurities and having low electron affinity;
When a heterojunction is formed between substantially impurity-free semiconductor layers with high electron affinity, a two-dimensional electron accumulation layer is formed at the heterojunction interface due to the difference in electron affinity between the two. A field effect transistor that uses this electron storage layer as a conductive channel is a high electron mobility transistor (
It is known as HEMT) or selectively doped field effect transistor (MODFET), and has superior high frequency characteristics compared to ordinary metal-semiconductor field effect transistors (MESFET).

Normally, high electron mobility transistors are as shown in Figure 4.
A non-doped semiconductor layer 42 with high electron affinity (e.g. GaA) is disposed on a semi-insulating substrate 41 (e.g. GaAs).
) is epitaxially grown to a specific M layer thickness (~1 .mu.m), and a semiconductor layer 43 containing n-type impurities and having low electron affinity (for example, AtGaAs) is epitaxially grown thereon. A tiger with a structure like this/
・Although it has been experimentally verified that Zostar exhibits good high-frequency characteristics, when devices with short channel lengths are fabricated, the saturation characteristics in the current saturation region are not necessarily good, and the current cut-off characteristics are poor. was often insufficient.

FIG. 4 shows drain current-f-) voltage characteristics when the gate length is changed in the device shown in FIG. The characteristics shown in Figure 4 are the impurity concentration 2X of the A4GaAs layer.
10 crn was obtained for a 200× thick device of AtGaAs under a dart electrode. Gate length LG is 0.
It can be seen that when the drain current becomes short to 2511 m, the drain current no longer exhibits a clear pinch-off characteristic, and at the same time, the mutual co-inductance gm (=minus t) becomes small in a range where the drain current is not very large. Such deterioration of characteristics becomes a serious problem when applying a high mobility transistor as an amplifier in the microwave band, and significantly impairs the effect of improving characteristics by shortening the gate length.

(Problems to be Solved by the Invention) As described above, in high electron mobility transistors based on the prior art, the gate length is shortened.

There was a problem in that the pinch-off characteristics deteriorated, the mutual conductance decreased in the low current operation region, etc., and the expected characteristic improvement effect was not necessarily obtained.

An object of the present invention is to solve this problem and provide a heterojunction field effect transistor that can maintain good current blocking characteristics and high mutual conductance even when the gate length is short.

[Structure of the Invention] (Means for Solving the Problems) In order to solve the above-mentioned technical problems, the present invention provides p-type impurities near the interface between a semi-insulating substrate and a semiconductor layer formed thereon. One of the features is to insert a thin layer region containing ~ functional. As will be described later, this p-type semiconductor layer suppresses the effect of the source-drain current protruding from the heterojunction interface toward the substrate side when a drain voltage is applied, resulting in improvements in pinch-off characteristics and mutual conductance values. . Since this p-type semiconductor layer plays the role of fixing the potential on the substrate side, its impurity density needs to be high. This is undesirable as it may lead to a decrease in current, leakage current, increase in capacity, etc. As described later, the areal density (sheet impurity concentration) of impurities in the p-type layer is I x 10" an-2
It is desirable to set the layer thickness to 1×10 13 cnv 2 and to make the layer thickness as thin as possible.

Additionally, as the channel length decreases, it is necessary to shorten the distance between the conductive channel and the p-type layer. In this case, p-type impurities are diffused during wafer formation.

In order to prevent this from reaching the vicinity of the channel, it is effective to provide a buffer layer with a superlattice structure above the p-type layer or so as to include the p-type layer.

(Function) Hereinafter, the reason why the element structure according to the present invention improves the pinch-off characteristics and the like will be explained in detail with reference to the results of precise computer simulation.

Figure 6 shows f,) current distribution, and (b) potential distribution inside the device when a high electron mobility transistor with a conventional structure with a gate length of 0.25 μm operates near pinch-off. . In this calculation, a non-doped GaAs layer (
Residual accessor: lXl0"m'), 2X10
It is assumed that the device is composed of an n-type AtGaA+ layer doped with cm2. However, the semi-insulating substrate portion is omitted in FIG. 6. As can be seen from Figure 6 (&), under the dart electrode, the current does not flow at the heterojunction interface;
It flows through the GaAs and extends to the substrate side. This shows that even though the original channel at the heterojunction interface is depleted and in a pinch-off state due to the dart voltage, the drain current is flowing due to the current going around to the substrate side. . The deterioration of the pinch-off characteristics as the dart length is shortened is due to this current loop. The leakage of the drain current to the substrate side is caused by the two-dimensional potential distribution inside the element.

That is, as shown in FIG. 6(b), in the element of the conventional structure, Q&A! Since the residual impurities in the first layer are extremely small and the concentration of impurities (consisting of deep donors and shallow acceptors) in the semi-insulating substrate is also low, the potential can be increased even in the deep part of the pGaAs layer by a positive voltage applied to the drain electrode. is lifted, and at the same time, the influence of the drain voltage extends to just below the source-side end of the dirt electrode. Therefore, electrons are easily injected from the source electrode into the GILA II layer, resulting in deterioration of the pinch-off characteristics.

By providing a p-type thin layer region adjacent to a semi-insulating substrate, the device according to the present invention has a structure in which the influence of drain voltage is difficult to reach the lower part of the source side end of the dirt electrode.

Figure 7 (&) l (b) shows that the thickness of the p-type semiconductor layer is 1
6(a) and (b) of the conventional example, the current distribution and potential distribution inside the device according to the present invention are shown with 00X and a sheet impurity concentration of 1×10 12 cIR−2. p
It can be seen that as a result of the potential on the substrate side of the GaAs layer being fixed by the type semiconductor, the influence of the drain voltage does not reach deep into the GaAs layer. As a result, the current flowing around to the substrate side is also suppressed to a shallow extent.

FIG. 8 is a diagram showing drain current-f-) voltage characteristics in comparison with a conventional structure when the thickness of the p-type semiconductor layer is fixed at 100XK and the sheet impurity concentration LA is varied. As the sheet impurity concentration of the p-type semiconductor layer increases, the pinch-off characteristics improve, but as lXl0 cm
Sufficient improvement can be obtained at a value of 1X10 cm or more, and no change is observed at 1X10 cm or more.

The current value when the transistor is fully turned on decreases as the sheet concentration of p-type impurities increases. Therefore,
Introducing impurities of 1×10 cm or more only reduces the current carrying capacity of the device and does not improve the device characteristics. Therefore, in order to fully expect the effects of the present invention, the p-type sheet impurity concentration should be l
2 to I x 10" cm-2.

(Embodiment) FIG. 1 is a structural sectional view of a heterojunction field effect transistor according to a first embodiment of the present invention.

This element is manufactured as follows. First, Be was added as an impurity onto a non-doped semi-insulating GaAa substrate using molecular beam epitaxy.
A p-type GaAs layer 12 containing a concentration of 100 mm thick is grown. The sheet impurity concentration of this p-type GaAs layer is 1×10
It becomes cIn. Next, a non-doped GaAs layer 13 to which no impurity is consciously added is formed to a thickness of about 1 μm, and on top of that is an n-type Atq layer containing 2×10 2 of Si as an impurity.
An n-type GaAs layer 15 containing 3Ga (1,7AIl I@14 and 2X1018d3 as an impurity) is grown by molecular beam epitaxial growth to a thickness of 300x and 500x, respectively.
．． Mesa etching of 3 μm is performed to isolate the elements.

Thereafter, source and drain electrodes 16 and 17 are formed using an AuGe-based metal by a normal lift-off process.

The distance between the source and drain electrodes is 3 μm. Then,
A gate resist glossy turn with a width of 0.25 μm is formed using an electron beam exposure method, and a recess shape is created by removing part of the nGaAs layer and nAt(1,50io,yAl1 layer) under this pattern by an etching process. A dart electrode 18 made of At/TI is formed in this recess region by a lift-off method to complete the device fabrication.

The device thus prepared with a dart width of 200 .mu.m exhibited good pinch-off characteristics at a dart voltage of -0.2 V and also exhibited a high mutual conductance value. FIG. 2 shows the results of measuring the relationship between the mutual conductance value and drain/current. In particular, the practical operating current for a microwave low noise amplifier, tD, is around 50 mA.
The fact that a high mutual conductance of ~60 m5 was obtained indicates the effectiveness of the present invention. Furthermore, the drain conductance in the current saturation region was suppressed to a low value of 3 to 4 mS over a wide current range. From this, it was confirmed that the device of the present invention also brought about a significant improvement in current saturation characteristics.

FIG. 3 is a structural sectional view of a heterojunction field effect transistor according to a second embodiment of the present invention. In this device, a sheet with a concentration of 1×10 12
! -2, a p-type head region 22 with a thickness of 100X is formed, and a superlattice layer 23 made of At□, 5GaO, 7A8, and GaAs is further formed thereon. Each layer in the superlattice is 100X thick.

On this superlattice layer 23, a non-doped GaAs layer 24 with a thickness of about 0.2 μm, an n-type Ato, 5GaO, 7A1 layer 25 containing 2×101” cm of Si and a 300X layer,
n-type GaAs containing 2 x 10” cm-’ of Si
The device is fabricated using wafer having a layer 26 of 500×. The manufacturing process of the source and drain electrodes 27 and 28 and the dirt electrode 29 is the same as in the first embodiment. The dart length was 0.1 μm. A superlattice layer 23 formed within the wafer is used to prevent upward diffusion of impurities from the substrate as well as upward diffusion of impurities from the p-type layer.

Although this element had an extremely short dart length of 0.1 μm, extremely good pinch-off characteristics were obtained, confirming the effectiveness of the present invention.

In the above embodiments, GaAg is used as the semiconductor combination.
and AtGaAs, but the structure according to the invention can also be applied to other material combinations, such as InP and InGaAs, GaA
It goes without saying that this method is equally effective for elements made of ++, AtGaSb, and the like.

[Effects of the Invention] As described above, if the element structure of the present invention is used,
It is possible to realize a heterojunction field-effect transformer that has good current cutoff characteristics (pinch-off characteristics) and current saturation characteristics even with a short dart length, and at the same time can maintain high mutual conductance even during low current operation.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of the structure of a heterojunction field effect transistor according to the first embodiment of the present invention, FIG. 2 is a diagram showing the dependence of the mutual conductance on drain current, and FIG. A cross-sectional view of the structure of a heterojunction field effect transistor as an example, FIG. 4 is a diagram schematically showing the structure of a conventional high electron mobility transistor, and FIG. 5 is a diagram showing the drain of a conventional high electron mobility transistor. Voltage-r voltage characteristics, Figure \(,) (b) is a diagram showing the current distribution and potential distribution inside the high electron mobility transistor of the conventional technology, Figure 7 (,) (b) is this diagram. FIG. 8 is a diagram showing the current distribution and potential distribution inside the device according to the invention, and is a diagram showing how the pinch-off characteristics are improved when the sheet concentration of the Pm semiconductor thin layer is changed in the invention. 1... Semi-insulating GaAs substrate, 12..."p-type Ga
As thin layer, 13...non-doped GaAg layer, 14-n
Type Ato, 3GILO, 7A8 layers, 15 = n-type Ga
Ag layer, 16... Source electrode, 17... Drain electrode, 18... f-) electrode, 21... Semi-insulating Ga
A+s substrate, 22- p-type GaAs thin layer, 23...
Superlattice J-124-...Non-doped GaAg layer, 25-
n-type AZ, ), 5GaO, 7μm layer, 26...n
type GaAg layer, 27- source electrode, 28... drain electrode, 29... dirt electrode. Applicant's representative Patent attorney Takehiko Suzue; Is Figure 1 Figure 4

Claims (3)

[Claims] (1) A first semiconductor layer having a high electron affinity and substantially containing no impurities and a second semiconductor layer having a low electron affinity stacked on a semi-insulating substrate, the first semiconductor layer and the first semiconductor layer having a low electron affinity. 2 induced along the heterojunction interface of the semiconductor layer of 2
In a field effect transistor that uses a dimensional electron accumulation layer as a conductive channel, a layer of 1 x 10^1^2 cm^-^2 to 1 x 10^1^ is placed near the interface between a semi-insulating substrate and an adjacent semiconductor layer. A heterojunction field effect transistor characterized in that a thin layer region containing p-type impurities with an areal density of 3 cm^-^2 is formed. (2) A superlattice layer consisting of a plurality of repeating layers having different band gaps is formed between the p-type thin layer region and the first semiconductor layer.
1) The heterojunction field effect transistor according to item 1). (3) The p-type thin layer region is formed by being included in a superlattice layer consisting of a plurality of repeating layers having different band gaps. heterojunction field effect transistor.