JPS60261162A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60261162A
JPS60261162A JP11706284A JP11706284A JPS60261162A JP S60261162 A JPS60261162 A JP S60261162A JP 11706284 A JP11706284 A JP 11706284A JP 11706284 A JP11706284 A JP 11706284A JP S60261162 A JPS60261162 A JP S60261162A
Authority
JP
Japan
Prior art keywords
bed
width
semiconductor chip
plane
inner leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11706284A
Other languages
Japanese (ja)
Inventor
Yuichi Yuki
幸　友一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP11706284A priority Critical patent/JPS60261162A/en
Publication of JPS60261162A publication Critical patent/JPS60261162A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To mount a large semiconductor chip, by shifting the surface of a bed, on which a semiconductor chip is mounted, from the plane of inner leads, making the interval between both surface in a plane zero, thereby increasing the area of the bed. CONSTITUTION:The surface of a bed 21, on which a semiconductor chip is mounted, is shifted from a plane formed by inner leads 24 by an interval (d). The interval between the inner leads 24 and the bed 21 is made to be zero in a plane. Therefore, a width P of the bed 21 can be made large in comparison with the width of a conventional bed, and the chip to be mounted can be made large. When the width P of the bed 21 is made intact as the conventional width, a size Q of each lead 24 can be made large conversely. Therefore, adhesion strength between a molding resin and the leads 24 can be improved.

Description

【発明の詳細な説明】 ［発明の技術分野］ 本発明は半導体装置に係り、特に２５６にビットのダイ
ナミックＲＡＭ以上の大型チップが適用されるリードフ
レームのパターンの改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to an improvement in the pattern of a lead frame to which a large chip larger than a 256-bit dynamic RAM is applied.

［発明の技術的背景及びその問題点］ 従来、半導体装置に於けるリードフレームのパターン形
状は、例えば第１図に示寸ようになっている。同図に於
いて、１１は半導体チップ（図示せず）がマウン１−さ
れるベッド（幅：Ｐ）である。[Technical Background of the Invention and Problems Therewith] Conventionally, the pattern shape of a lead frame in a semiconductor device is as shown in FIG. 1, for example. In the figure, 11 is a bed (width: P) on which a semiconductor chip (not shown) is mounted.

このベッド１１は吊りビン１２．１３により支持されて
おり、第２図に示すようにこれら吊りピン１２．１３の
なす面よりやや低く設定されている。ヘッド１１の周囲
には、長辺部に対向（間隔°Ｓ）して複数のインナーリ
ード（幅：Ｑ）１４．１４・・・、短辺部に対向（間隔
：Ｒ）して複数のインナーリード１５．１５・・・がそ
れぞれ配設されている。なお、一点鎖線はモールド領域
（幅：Ｏ）を示づ−もので、Ｌはこのモールド領域１６
の周縁部とインナーリード１４．１４・・・の各平行部
１４ａとの間隔を示すものである。This bed 11 is supported by hanging pins 12.13, which are set slightly lower than the plane formed by these hanging pins 12.13, as shown in FIG. Around the head 11, there are a plurality of inner leads (width: Q) 14.14 facing the long sides (interval °S), and a plurality of inner leads (width: Q) facing the short sides (interval: R). Leads 15, 15, . . . are arranged respectively. Note that the dashed line indicates the mold area (width: O), and L indicates this mold area 16.
The distance between the peripheral edge of the inner lead 14, 14, and each parallel portion 14a of the inner lead 14, 14, . . .

しかしながら、上記のような構造では、ベッド１１上に
マウントする半導体チップが２５６にダイナミックＲＡ
Ｍのように大きくなると、従来のモールド金型を使用で
きない欠点があった。すなわち、上記構造では、リード
部の（Ｓ十〇＋Ｒ）の寸法に制約があるために、半導体
チップに対応してベッド１１の幅Ｐが大きくなると、従
来の３００　ｍｉｌパッケージのモールド幅Ｏの中に入
らない状況となるものである。However, in the above structure, the semiconductor chip mounted on the bed 11 is connected to the dynamic RA 256.
When the size is as large as M, there is a drawback that conventional molds cannot be used. In other words, in the above structure, since there is a restriction on the dimension (S10+R) of the lead part, when the width P of the bed 11 increases to correspond to the semiconductor chip, the width of the mold width O of the conventional 300 mil package increases. This is a situation that does not fit into the category.

「発明の目的〕 本発明は上記実情に鑑みてなされたもので、その目的は
、従来のパッケージ寸法を変更することなく、大型化し
た半導体チップを適用することのできる半導体装置を提
供することにある。"Object of the Invention" The present invention has been made in view of the above-mentioned circumstances, and its purpose is to provide a semiconductor device to which an enlarged semiconductor chip can be applied without changing the conventional package dimensions. be.

［発明の概要］ すなわち、本発明は、ベッドと、このベッドにマウント
される半導体チップと、前記ベッドに対向して配設され
、それぞれ前記半導体チップの電極と電気的に接続され
る複数のインナーリードとを有する半導体装置に於いて
、フレーム状態から前記ベッド及びリードフレームを切
離す際に、ベベッドの長辺と前記インナーリードの各対
向辺とを平面パターン状態で一致させ、かつ前記ベッド
面と前記インナーリードのなす面との間に所定の間隔を
設けるものである。[Summary of the Invention] That is, the present invention provides a bed, a semiconductor chip mounted on the bed, and a plurality of inners arranged facing the bed and electrically connected to electrodes of the semiconductor chip. In a semiconductor device having a lead, when the bed and lead frame are separated from the frame state, the long side of the bed and each opposing side of the inner lead are aligned in a planar pattern state, and the bed surface and A predetermined distance is provided between the inner lead and the surface formed by the inner lead.

［発明の実施例］ 以下、図面を参照して本発明の一実施例を説明する。第
３図に於いて、２１は半導体チップ（図示せず）がマウ
ントされるベッドである。このベッド２１は吊りピン２
２．２３により支持されており、第２図に示したと同様
にこれら吊りピン２２．２３のなす面よりやや低く設定
されている。ヘッド２１の周囲には、長辺部に対向して
複数のインナーリート（幅：Ｑ）２４．２４・・、短辺
部に対向（間隔：Ｒ）して複数のインナーリード２５．
２５・・・がそれぞれ配設されている。上記インナーリ
ート２４．２４・・・はそれぞれ吊りピン２２．２３の
なす面と同一面上にあり、従ってベッド１１面は第４図
に示すようにインナーリード２４．２４・・・のなす面
より低く（間隔：ｄ）設定されている。このリードフレ
ームパターンは、ヘッド２１とインナーリード２４．２
４・・・とを切り離すと同時に、ヘッド２１を押し下げ
ることにより形成される。[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In FIG. 3, 21 is a bed on which a semiconductor chip (not shown) is mounted. This bed 21 has hanging pins 2
2.23, and is set slightly lower than the plane formed by these hanging pins 22.23, as shown in FIG. Around the head 21, there are a plurality of inner leads (width: Q) 24.24 facing the long sides, and a plurality of inner leads 25.24 facing the short sides (interval: R).
25... are arranged respectively. The inner leads 24, 24, etc. are on the same plane as the hanging pins 22, 23, so the bed 11 surface is lower than the plane of the inner leads 24, 24, as shown in FIG. It is set low (interval: d). This lead frame pattern consists of a head 21 and an inner lead 24.2.
4... are formed by pressing down the head 21 at the same time.

すなわち、上記構造にあっては、ベッド２１面とインナ
ーリード２４．２４・・・のなす面との面間隔をずらし
、両者の平面間隔（従来はＳ）を零としたものであり、
このため次のような効果が得られるものである。That is, in the above structure, the plane spacing between the bed 21 surface and the planes formed by the inner leads 24, 24, etc. is shifted, and the plane spacing between the two (conventionally S) is set to zero,
Therefore, the following effects can be obtained.

（１）　ベラ１〜２１の幅Ｐを従来に比べて２８（約０
．５〜０．（３ｍ）だけ大きく取れるため、モールド幅
Ｏを変更しなくても、２５６にダイナミックＲＯＭ以上
の大型チップを従来のパッケージに収めることができる
。(1) Width P of bellows 1 to 21 has been increased to 28 (approx.
．． 5-0. (3 m), it is possible to fit a large chip larger than 256 dynamic ROM into a conventional package without changing the mold width O.

（２）　ベッド２１の幅を従来のままにすると、逆にイ
ンナーリード２４．２４・・・の各寸法をＳだけ大きく
することができるため、モールド樹脂とインナーリード
２４．２４・・・との密着力が向上し、その結果耐湿性
が向上する。(2) If the width of the bed 21 is kept the same as before, each dimension of the inner leads 24, 24... can be increased by S, so that the difference between the mold resin and the inner leads 24, 24... Adhesion is improved, resulting in improved moisture resistance.

［発明の効果］ 以上のように本発明によれば、パッケ〜シ全体の外形寸
法を変えることなく、半導体チップの大型化を図ること
のできる半導体装置を提供できる。[Effects of the Invention] As described above, according to the present invention, it is possible to provide a semiconductor device in which the size of the semiconductor chip can be increased without changing the external dimensions of the entire package.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の半導体装置に於けるリードパターンを示
す平面図、第２図は同パタニンに於けるベッド部の横断
面図、第３図は本発明の一実施例に係るリードパターン
を示す平面図、第４図は同パターンに於けるベラ１〜部
の縦断面図である。 ２１・・・ヘット、２２．２３・・・吊りピン、２４．
２５・・・インナーリート。 出願人代理人　弁理士　鈴江武彦FIG. 1 is a plan view showing a lead pattern in a conventional semiconductor device, FIG. 2 is a cross-sectional view of a bed portion in the same pattern, and FIG. 3 is a lead pattern according to an embodiment of the present invention. The plan view and FIG. 4 are longitudinal sectional views of the tongue 1 to part in the same pattern. 21...Het, 22.23...Hanging pin, 24.
25... Inner Reed. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

【特許請求の範囲】[Claims] ベッドと、このベッドにマウン１〜される半導体チップ
と、前記ベッドに対向して配設され、それぞれ前記半導
体チップの電極と電気的に接続される複数のインナーリ
ードとを有する半導体装置に於いて、少なくとも前記ベ
ッドの長辺と前記インナーリードの各対向辺とが平面パ
ターン状態で一致し、かつ前記ヘッド面と前記インナー
リードのなす面との間に所定の間隔を有することを特徴
とする半導体装置。A semiconductor device comprising a bed, a semiconductor chip mounted on the bed, and a plurality of inner leads arranged opposite to the bed and electrically connected to electrodes of the semiconductor chip, respectively. , a semiconductor characterized in that at least the long side of the bed and each opposing side of the inner lead match in a planar pattern, and there is a predetermined interval between the head surface and the surface formed by the inner lead. Device.
JP11706284A 1984-06-07 1984-06-07 Semiconductor device Pending JPS60261162A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11706284A JPS60261162A (en) 1984-06-07 1984-06-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11706284A JPS60261162A (en) 1984-06-07 1984-06-07 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60261162A true JPS60261162A (en) 1985-12-24

Family

ID=14702480

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11706284A Pending JPS60261162A (en) 1984-06-07 1984-06-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60261162A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03160749A (en) * 1989-11-20 1991-07-10 New Japan Radio Co Ltd Lead frame and its manufacture
JPH0468560A (en) * 1990-07-10 1992-03-04 Toshiba Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03160749A (en) * 1989-11-20 1991-07-10 New Japan Radio Co Ltd Lead frame and its manufacture
JPH0468560A (en) * 1990-07-10 1992-03-04 Toshiba Corp Semiconductor device

Similar Documents

Publication Publication Date Title
JPS60261162A (en) Semiconductor device
JPS589585B2 (en) Dense hinge lead frame
JPH05114671A (en) Semiconductor device
JPH01205456A (en) Multi-pin case for lsi
JP2788196B2 (en) IC board for IC card
JPS607152A (en) Semiconductor device
JPH0529527A (en) Semiconductor device
JPS6366959A (en) Multiple lead frame
JPH06260583A (en) Semiconductor package
JPS6346844U (en)
JPH04186755A (en) Lead frame
JPH0268452U (en)
JPS646038U (en)
JPS6166955U (en)
JPS5933254U (en) semiconductor equipment
JPS5889953U (en) hybrid circuit
JPH044747U (en)
JPH0794657A (en) Lead frame and resin sealed semiconductor employing it
JPS5954938U (en) Multi-stage structure of leadless package
JPS60174254U (en) Power semiconductor equipment
JPH04162463A (en) Lead frame for ic
JPS61150255A (en) Semiconductor device and manufacture thereof
JPH0256356U (en)
JPH02278742A (en) Semiconductor device
JPH03196555A (en) Semiconductor package