JPS60257625A - Counter circuit - Google Patents

Abstract

PURPOSE:To output a count value of a clock signal while dividing it N-time by x-bit each by inputting an AND value of carry outputs of the 1st-(i-1)th counters to the 2nd enable terminal of the 1-th counter. CONSTITUTION:A value of an output signal 7 of a counter A is ''0'' when a 1/3 frequency division signal 2 is at a low level. When the 1/3 frequency division signal 2 goes to a high level, ''0'' is loaded, and the counter a counts up and the value of the output signal 7 of the counter A changes from ''0'' to ''1''. Since the 1/3 frequency division signal 2 goes to a low level during two clocks afterward, the value of the output signal 7 of the counter A remains ''0'' and unchanged. When the 1/3 frequency division signal 2 goes to a high level, a value ''1'' of the preceding output signal 7 is fed back and becomes an input to the counter A, loaded and then counted up, then the value of the output signal of the counter A changes from ''1'' to ''2''. Then the counter is counted up at three clocks each.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a counting circuit that counts clock signals.

In particular, if the number of hits of the count value is greater than the number of output nodes of the counting circuit.
In the case of L, divide y into X bit units 0 times and output it for the count value ny (y <2"・X, y, x are natural numbers) using a simple circuit without using a select circuit. Regarding counting circuits.

[Conventional technology]

When counting clocks and outputting the counted value, if the output of the counting circuit is limited to Must. In other words, if the counting circuit is equipped with n X-bit output counters, the number of pins of the count value is at most n'
x hits, and the select circuit sets each x bit to 0.
It can be divided into parts and output. In such a circuit, when the value of n becomes large, it becomes necessary to divide the count value into many parts, and the selection circuit becomes complicated.

[Problem that the invention seeks to solve]

SUMMARY OF THE INVENTION An object of the present invention is to provide a counting circuit that divides a count value of a clock signal into 0 times by X bits and 0 times and outputs the divided values without using a select circuit.

[Means for Solving the Problems] The present invention provides pulse generation means for generating pulse signals in response to rising and falling edges of an input clock signal;
A frequency dividing means for generating a signal obtained by dividing the frequency of the clock signal by 1/n (n is an integer of 2 or more) and an output signal of the pulse generating means are respectively connected to a clock terminal, and the output signal of the frequency dividing means is connected to a clock terminal. n counters each connected to a first enable terminal and having a clock signal respectively connected to a load terminal;
The count output of the first d1 counter is connected to the output terminal and branched to the parallel load input of the n-th counter among the n counters. Count outputs of the first counter (i is an integer from 2 to n) of the counters are respectively connected to parallel load inputs of the i-1th counter, and The output signal of the frequency dividing means is connected to the second enable terminal of -h, and the second enable terminal of the i-th counter (j is an integer from 2 to n) is connected to the output signal of the frequency dividing means. The logical product of the carry outputs of the respective counters up to the number i-]th number l] is connected, and each of the n counters is enabled by the logical product of the first enable terminal and the second enable terminal. It is characterized by being configured so that.

[For production]

In the present invention, in n X-bit/7-bit counters, when the clock signal input to the load terminal is low level, the first The output signal of the counter is loaded to the n-th counter and the output signals of the counters other than the first are loaded to the counters in the previous stage. When the clock signal input to the rotor terminal is high level, at the timing of the rise of the pulse signal input to the clock terminal, the 1/n minute input to the first and second enable terminals of the counter 1] When the frequency signal is high level, the value loaded into the first counter is counted up, and the 1/n frequency divided signal input to the first enable terminal of the counters other than the first and the first If the logical product of the carry signals of the counters from the first to the previous stage inputted to the enable terminal of the counter is both high level, the value loaded into the counter is counted up. As mentioned above, the pulse signal is converted into a counter and one count is 1.
By counting the /n frequency-divided signal as a period and circulating the counted value between each counter, the counted value can be divided 0 times by X bits from the first counter and output.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block block diagram of a counting circuit according to an embodiment of the present invention, and shows the case where there are three counters and the output number is 4. A clock signal 1 for counting is connected to the rotor ends 7-1- of each of the counters A, B and C, and also to a 1/3 frequency divider circuit and a pulse generator circuit E. 1/3
The frequency divider circuit divides the clock signal 1 into a 1/3 frequency signal.
The clock signal width divided by 1/3 signal 2 is sent to counters A, B, and C.
are connected to the enable terminals EP of the terminals, respectively, and are also connected to the enable terminals F and T of the digitizer. Pulse signals 3 corresponding to the rising and falling edges of clock signal 1 from pulse generation circuit E are sent to clock ends 7 of counters A, R, and C.
- Connected to CK. 4 from carry terminal CY of counter A
- Yari signal 4 is connected to enable input ET of counter B and to one input of AND circuit F; A carry signal 5 from the carry terminal CY of the counter B is connected to the other input of the ant circuit F.

The output signal 6 of the AND circuit F is connected to the enable terminal ET of the counter C. The output signal 7 to the counter is output outside the figure, and is also branched and connected to the counter hG. The output signal 8 of counter B is connected to counter A, and the output signal 9 of counter C is connected to counter B.

The operation of the counting circuit having such a configuration will be explained. In FIG. 1, clock signals 1, ], /3 frequency-divided signals 2, and pulse signals 3 are input to counters A to C, respectively, and counter A receives an output signal 8 of counter B, and counter B The output signal 9 of the counter C and the carry signal 4 from the multiplier A are input to the counter C, and the output signal 7 of the counter A and the output signal 6 of the AND circuit are input to the counter C. In this counting circuit, when the January of the rotor terminal I7 is at a low level, the clock v
=At the timing of the rising edge of the child GK signal, the output signals 7, 8, and 9 of each counter A, C are loaded into the preceding stage counters C, A, and B, respectively, and the signal at the load terminal becomes For high levels, black.

If the signals at the enable terminals BP and ET of counters A, B, and C are all at high level at the rising timing of the signal at terminal CK, the values loaded into each counter △, B, and C are counted up. Ru.

In Fig. 1, focusing on the counter, while the 1z3 frequency division signal 2 is low level, the value of the output signal 7 to the 51 counter will be Ono (hexadecimal expression), and the 1z3 frequency division signal 2 will be high. When the level is reached, 0□ is loaded at timing (1), and at timing (2), it is counted up and counted R'.
The value of the output signal 7 of AA changes from Ofil to 1 (H). For the next two clocks, the 1z3 frequency division signal 2 is at low level, so the value of January 7 output to the counter is 0 (Ill
It remains unchanged. Next, when the 1z3 frequency division signal 2 becomes high level, the value ILIL of the previous output signal 7 is fed back and becomes the input to the counter A, and at timing (3), 1ol is loaded and counted up. Therefore, the value of output signal 7 of counter A is 1. From Hl, it becomes 2□. Since it continues to be counted up every three clocks, the value of the output signal 7 to the counter is as follows: (IO・0 (old, followed by 0 <s+;'-.

Next, the carrying by tl\I units B and C will be explained. FIG. 3 is a time chart of the signals of each part when the counter (T3) has a repeat of -1. In FIG. 3, when F++n is loaded into counter A, carry No. 18 of counter A is output and enable terminal E of counter B is output.
Since T becomes high level, the value of the output signal 7 of the counter A changes from F (Hl to ofllll), and at the same time, the value of the output signal 8 of the counter B also changes from O(Ml to l (Ill
will be counted up.

FIG. 4 is a time chart of the signals of each part when there is a carry in the 31 number unit (C). In FIG. 4, as mentioned above, when counters A and B are loaded with F(Ill), each counter A and B outputs a carry signal of 4.5, so the enable terminal ET of counter C is becomes high level, and the value of the output signal 7.8 of counters A and B becomes F(
Ill to 00. . At the same time, the value of the output signal 9 of the counter C also changes to 0 (.

From 1. ,) is counted and amplified.

As mentioned above, the values counted by each counter A, B, and C are 1. Since the values are fed back every 1 count, the output signal 7 to the counter is 1/2 The timing of the falling edge of signal 1 If you look at it, 1 on, 0 (old On(); 2 no, Of
F (Ill, OfIl
l, O(Hl+0 (Ill, I (Ill, O
no:;F (111,F (1゜,OfIll;O
On, it becomes 1+H, and a signal in which the output is counted up every three clocks can be obtained.

〔Effect of the invention〕

As explained above, the present invention allows the total v! , the value can be divided N times by X hits and output. Therefore, there is an advantage that the circuit can be simplified.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a counting circuit according to an embodiment of the present invention. FIG. 2 shows time charts 1 to 1 of the signals in each part. FIG. 3 is a time chart of the signals of each part when there is a carry in the counter (B). Figure 4 is a time chart of the signals of each part when the counter (C) has an overrun. 1... Clock signal, 2... 1/3 frequency divided signal, 3...
... Pulse signal, 4.5... Carry signal, 6... AND circuit output signal, 7... Output signal to counter, 8.
... Output signal of counter B, 9... Output signal of counter C, A, B, C... counter, D... 1/3 frequency divider circuit,
E...Pulse generation circuit. Patent ratio) Applicant: Hiki Electric Co., Ltd. Representative Patent attorney: Naotaka Ide

Claims (1)

[Claims] (1) Pulse generating means that generates pulse signals in response to the rising and falling edges of an input clock signal, and a pulse generating means that generates a signal obtained by dividing the frequency of the clock signal by 1/n (n is an integer of 2 or more). The frequency dividing means and the output signals of the pulse generating means are each connected to a clock terminal, the output signals of the frequency dividing means are each connected to a first enable terminal, and the black and red signals are respectively connected to a load terminal. n counters, the counting output of the first counter of the n counters is connected to the output terminal and branched to the n-th counter of the n counters. is connected to the parallel load input of the old counter of ``hole-hole n counters (i is 2
The counting outputs of the (integers from to n) are respectively connected to the parallel load input of the i-1th 81 counter, and the output signal of the frequency dividing means is connected to the second enable terminal of the first counter. is connected to the second enable terminal of the i-th counter (i is an integer from 2 to n), and the logic of the carry output of each of the first to i-1th counters is connected to the second enable terminal of the i-th counter (i is an integer from 2 to n). A counting circuit characterized in that products are connected, and each of the n'' n1 counters is configured to be enabled by a logical product of a first enable terminal and a second enable terminal.