JPH04287420A - Digital circuit for dividing frequency into odd number fraction - Google Patents

Abstract

PURPOSE:To easily form the odd number frequency divider circuit by providing a 1st counter circuit, a 2nd counter circuit and a logic circuit so as to attain odd number frequency division without use of a multiplier. CONSTITUTION:The circuit is provided with an original oscillation input signal terminal 1, an input terminal 3 at '1' and an input terminal 2 at '0' receiving respectively an integral part '2' of a quotient resulting from halving a frequency division value '5', and an inverter buffer 4 inverting the original oscillation input signal, and also a 1st counter circuit 5 counting the repetitive number of the input signal whose duty ratio is 50% and outputting a 1st carry signal at the rising of the input signal with the integral part of a quotient resulting from halving a frequency division value, a 2nd counter circuit 6 counting the repetitive number of the input signal and outputting a 2nd carry signal at the falling of the input signal with the integral part of a quotient resulting from halving a frequency division value, and a logic circuit outputting a frequency division signal with the 1st carry signal and the 2nd carry signal.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an odd frequency divider circuit constructed of digital circuits.

0002

[Prior Art] A conventional odd number frequency divider circuit doubles the frequency of an input signal using a multiplier or a differentiating circuit, and then divides the frequency by an even number using a counter or a T-flip-flop. I was going.

0003

[Problem to be solved by the invention] This conventional odd frequency divider circuit requires a multiplier that doubles the frequency of the input signal in order to obtain an output signal with a duty ratio of 50%, but this is difficult to implement in a digital circuit. There was a problem that.

0004

[Means for Solving the Problems] A digital odd number frequency divider circuit according to the present invention counts the number of repetitions of an input signal with a duty ratio of 50%, and calculates the value of the integer part of the quotient obtained by dividing the frequency division value into half. a first counting circuit that outputs a first carry signal at the rising edge of the input signal; a second counting circuit that counts the number of repetitions of the input signal; A second counting circuit outputs a carry signal at the falling edge of an input signal, and a logic circuit outputs a frequency-divided signal based on the first carry signal and the second carry signal.

[0005]

[Operation] The present invention can realize odd frequency division using a digital circuit.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram showing an embodiment of a digital odd frequency divider circuit according to the present invention, and shows a digital 5 frequency divider circuit as an example. In the figure, 1 is the input terminal of the original oscillation input signal shown in Fig. 2(a), and 2 and 3 are the frequency division value "5".
Correction value "1" of 1 of the integer part "2" of the quotient which is halved
, “0” are input to the “1” input terminal and “0” respectively.
” input terminal, 4 is an inverter that inverts the original input signal.
In buffer 5, the correction value "1" is input to the data terminal D0, the correction value "0" is input to the data terminal D1, the original oscillation input signal is input to the clock terminal C, and the following second signal is input to the load terminal L. When the carry signal output from the terminal CRY of the bit counter is input, the counting operation is performed as shown in FIG. 2(b), and the synchronous load type bit counter outputs the carry signal shown in FIG. 1 2-bit counter,
6, the correction value "1" is input to the data terminal D0, the correction value "0" is input to the data terminal D1, the output signal of the inverter buffer 4 is input to the clock terminal C, and the load terminal L
When the carry signal output from the terminal CRY of the first 2-bit counter 5 is inputted to the first 2-bit counter 5, the counting operation is performed as shown in FIG. 2(d), and the carry signal shown in FIG. 2(e) is output from the terminal CRY. A synchronous load type second 2-bit counter 7 is set by the carry signal of the first 2-bit counter 5 inputted to the terminal S, and reset by the carry signal of the second 2-bit counter 6 inputted to the terminal R. , is an R-S flip-flop that outputs a frequency-divided signal shown in FIG. 2(f) from terminal Q.

Next, the operation of the digital odd frequency divider circuit having the above configuration will be explained. First, when the original input signal shown in FIG. 2(a) is input to the clock terminal C of the first 2-bit counter 5 via the input terminal 1, the input signal shown in FIG. When a full count is reached, a carry signal shown in FIG. 2(c) is output from the terminal CRT at the rising edge of the original input signal. This carry signal is the load terminal L of the second 2-bit counter 6.
is input to initialize the second 2-bit counter 6, and is also input to the set terminal S of the R-S flip-flop 7 to set the R-S flip-flop 7, as shown in FIG. 2(f). The frequency division signal shown rises. On the other hand, when the inverted signal of the original oscillation input signal is input to the clock terminal C of the second 2-bit counter 6, as shown in FIG.
The counting operation is performed as shown in (d), and when the full count is reached, the rise of the original oscillation input signal from the terminal CRT causes the counting to occur as shown in Fig. 2 (e).
The carry signal shown in is output. This carry signal is input to the load terminal L of the first 2-bit counter 5 to initialize the first 2-bit counter 6, and at the same time, the R-S
The signal is input to the reset terminal L of the flip-flop 7 to reset the R-S flip-flop 7, and the divided signal shown in FIG. 2(f) falls. Odd frequency division can be obtained by repeating the above operations alternately.

[0008]

[Effects of the Invention] As explained in detail above, according to the digital odd number frequency divider circuit according to the present invention, odd number frequency division can be realized without using a multiplier, and the odd number frequency divider circuit can be easily implemented. It has the advantage of being configurable.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of a digital odd frequency divider circuit according to the present invention.

FIG. 2 is a waveform diagram of each signal.

[Explanation of symbols]

1 Input terminal 2, 3 Input terminal 4 Inverter buffer 5 First 2-bit counter 6 Second 2-bit counter 7 R-S flip-flop

Claims (1)

[Claims] 1. A first carry signal that counts the number of repetitions of an input signal with a duty ratio of 50% and outputs a first carry signal at the rising edge of the input signal based on the value of the integer part of the quotient obtained by halving the frequency division value. 1 counting circuit, and a second circuit that counts the number of repetitions of the input signal and outputs a second carry signal at the falling edge of the input signal based on the value of the integer part of the quotient obtained by halving the frequency division value. A digital odd frequency divider circuit comprising: a counting circuit; and a logic circuit that outputs a frequency-divided signal based on the first carry signal and the second carry signal.