JPS60254753A - Mounting package of eprom chip - Google Patents

Mounting package of eprom chip

Info

Publication number
JPS60254753A
JPS60254753A JP11167784A JP11167784A JPS60254753A JP S60254753 A JPS60254753 A JP S60254753A JP 11167784 A JP11167784 A JP 11167784A JP 11167784 A JP11167784 A JP 11167784A JP S60254753 A JPS60254753 A JP S60254753A
Authority
JP
Japan
Prior art keywords
sapphire
cap
eprom chip
eprom
mounting package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11167784A
Other languages
Japanese (ja)
Other versions
JPH031836B2 (en
Inventor
Yoshitaka Fukuoka
義孝 福岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP11167784A priority Critical patent/JPS60254753A/en
Publication of JPS60254753A publication Critical patent/JPS60254753A/en
Publication of JPH031836B2 publication Critical patent/JPH031836B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • G11C16/18Circuits for erasing optically

Landscapes

  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To improve heat resistance and moisture resistance, by coating EPROM chips, which are mounted on a ceramic wiring substrate with a metal cap comprising sapphire having a window in an airtight manner. CONSTITUTION:A metallized layer 8, which is formed by burning molybdenum, tungsten paste or the like, and a nickel and gold plated layer 9 are laminated and formed sequentially at the peripheral part of a ceramic wiring substrate 6 so as to surround mounting parts of EPROM chips 7. On the nickel and gold plated layer 9, a cap 11 made of Cobal, which comprises a thin plate 10 of sapphire and has ultraviolet-ray transmitting window, is bonded by solder 12 in an airtight manner. As the metallic cap, sapphire and the metal, whose thermal expansion coefficient is approximately equal to that of the ceramic substrate, are used. Therefore, moisture resistance and resistance against heat shock can be improved.

Description

【発明の詳細な説明】 [発明の技術分野] 本発明はEPROMチップをセラミック配線基板上に搭
載してなるパッケージに関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a package in which an EPROM chip is mounted on a ceramic wiring board.

[発明の技術的背景とその問題点J [FROMチップ搭載パッケージは、書込まれたメモリ
データを紫外線を照射して消去するため、EPROM上
を紫外線透過性のガラス板により気密に覆って構成され
ている。
[Technical background of the invention and its problems J] [A FROM chip mounting package is constructed by covering the EPROM hermetically with an ultraviolet-transparent glass plate in order to erase the written memory data by irradiating it with ultraviolet rays. ing.

第2図は、このような従来のEPROM搭載パッケージ
を示すもので、EPROMチップ1を搭載したセラミッ
ク配線基板2上にセラミックリング3を接着剤4で接着
し、その上に紫外線透過ガラス5を接着剤4で接着して
構成されている。
FIG. 2 shows such a conventional EPROM mounting package, in which a ceramic ring 3 is bonded with an adhesive 4 on a ceramic wiring board 2 on which an EPROM chip 1 is mounted, and an ultraviolet transmitting glass 5 is bonded on top of the ceramic ring 3. It is configured by adhering with agent 4.

なお接着剤4としては、一般にエポキシ樹脂のような有
機接着剤が用いられている。
Note that as the adhesive 4, an organic adhesive such as an epoxy resin is generally used.

ところで、従来セラミックリング3および紫外線透過ガ
ラス5の接着に用いられていたエポキシ1脂のような有
機接着剤は、完全な気密性を有していないので、このよ
うにして構成されたパッケージは耐湿性に乏しい難点が
あった。
By the way, organic adhesives such as epoxy 1, which have been conventionally used to bond the ceramic ring 3 and the ultraviolet-transmissive glass 5, are not completely airtight, so the package constructed in this way is moisture resistant. There was a drawback of lack of sex.

またこのような接着剤は、ガラスやセラミックとの熱膨
張係数の差が大きいので、使用可能温度はO℃以以上7
0程程までの間に限定されてしまうという難点もあった
In addition, such adhesives have a large difference in thermal expansion coefficient from glass and ceramics, so the usable temperature is 70°C or higher.
There was also the drawback that it was limited to about 0.

したがって従来のEPROMチップ搭載パッケージは、
さらに厳しい耐湿性や温度特性を要求される例えばMI
L規格等を満足させることは不可能であった。
Therefore, the conventional EPROM chip package is
For example, MI, which requires even stricter moisture resistance and temperature characteristics.
It was impossible to satisfy L standards and the like.

[発明の目的] 本発明は上記の点に対処してなされたもので、耐熱性と
耐湿性を飛躍的に向上させたEPROMチップ搭載パッ
ケージを提供することを目的とするものである。
[Object of the Invention] The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide an EPROM chip mounting package that has dramatically improved heat resistance and moisture resistance.

[発明の概要] すなわち本発明のEPROMチップ搭載パッケージは、
セラミック配線基板上に搭載されたEPROMチップを
サファイヤからなる窓を有する金属キャップで気密に覆
って成ることを特徴としている。
[Summary of the invention] That is, the EPROM chip mounting package of the present invention has the following features:
It is characterized in that an EPROM chip mounted on a ceramic wiring board is hermetically covered with a metal cap having a window made of sapphire.

[発明の実施例] 第1図は、本発明のEPROMチップ搭載パッケージの
実施例の横断面図である。
[Embodiment of the Invention] FIG. 1 is a cross-sectional view of an embodiment of an EPROM chip mounting package of the present invention.

第1図において、セラミック配線基板6上には複数個の
EPROMチップ7が搭載されている。
In FIG. 1, a plurality of EPROM chips 7 are mounted on a ceramic wiring board 6. As shown in FIG.

セラミック配線基板6の周縁部にはモリブデンあるいは
タングステンペースト等の焼成によるメタライズ層8と
ニッケル及び金メッキ層9とがEPROMデツプ7搭載
部を囲んで順に積層形成されている。
On the periphery of the ceramic wiring board 6, a metallized layer 8 made of molybdenum or tungsten paste, etc., and a nickel and gold plating layer 9 are laminated in order surrounding the EPROM depth 7 mounting area.

このニッケル及び金メツキ層9上には、サファイヤの薄
板10からなる紫外線透過窓を有するコバール製キャッ
プ11が気密にハンダ12により接合されている。
On this nickel and gold plating layer 9, a cap 11 made of Kovar and having an ultraviolet transmitting window made of a thin sapphire plate 10 is hermetically bonded with solder 12.

なお、コバール製キャップ11とセラミック配線基板6
との接合は、一旦上記した方法によりコバールウェルド
リングをセラミック配線基板6上に銀ろう付けし、この
上にコバール製キャップ11をレーザ溶接することによ
り行なってもよい。
In addition, the Kovar cap 11 and the ceramic wiring board 6
The bonding may be performed by first silver-brazing the Kovar weld ring onto the ceramic wiring board 6 using the method described above, and then laser welding the Kovar cap 11 thereon.

上述したサファイヤの薄板10は、コバール製キャップ
11の中央に打抜き孔を設けてその周縁部を凹陥させ、
この凹陥部に接合させることによリコバール製キャップ
11に固着されている。
The thin sapphire plate 10 described above has a punched hole in the center of the Kovar cap 11 and its peripheral edge is recessed.
It is fixed to the Ricovar cap 11 by joining this concave portion.

コバール製キャップ11とサファイヤの薄板10との接
合は、サファイヤの薄板10の周辺部に予めタングステ
ンペースト等によるメタライズ層とニッケルメッキ層と
を順に形成しておき、それをコバール製キャップ11の
打抜き孔の凹陥部に載せて銀ろう13付けすることによ
り行なわれる。
To join the Kovar cap 11 and the sapphire thin plate 10, a metallized layer made of tungsten paste or the like and a nickel plating layer are formed in advance on the periphery of the sapphire thin plate 10 in this order, and then the sapphire thin plate 10 is connected to a punched hole in the Kovar cap 11. This is done by placing it on the concave part and attaching silver solder 13 to it.

なお、この実施例に示したように、金属性キャップとし
てコバールのようなサファイヤ及びセラミック基板と熱
膨張係数がほぼ等しい金属性のものを使用すればヒート
ショックに対する耐性が向上する。
Note that, as shown in this embodiment, resistance to heat shock is improved by using a metal cap such as Kovar, which has approximately the same coefficient of thermal expansion as the sapphire or ceramic substrate.

第1図に示した実施例においては、コバール製キャップ
11の中央上面に1枚の大きなサフアイヤの薄板10か
らなる紫外線透過窓を設けた例について説明したが、本
発明はかかる実施例に限定されるものではなく、各EP
ROMに対応させて複数個のサファイヤ窓を形成するよ
うにしてもよい。
In the embodiment shown in FIG. 1, an example was explained in which an ultraviolet transmitting window made of one large thin sapphire plate 10 was provided on the upper center surface of the cap 11 made of Kovar, but the present invention is not limited to such an embodiment. each EP, not the
A plurality of sapphire windows may be formed corresponding to the ROM.

第1図と其通ずる部分に同一符号を付した第3図は、こ
のような実施例を示すもので、コバール製キャップ11
の上面にEPROMチップ7の1個毎に、これに紫外線
を照射するのに十分な大きさの打抜き孔を設け、この打
抜き孔にサファイヤの薄板10をそれぞれ第1図に示し
た実施例と同様にして気密に接合した例である。
FIG. 3, in which parts common to those in FIG. 1 are given the same reference numerals, shows such an embodiment.
A punching hole large enough to irradiate each EPROM chip 7 with ultraviolet rays is provided on the top surface of each EPROM chip 7, and a thin sapphire plate 10 is inserted into each of the punching holes, similar to the embodiment shown in FIG. This is an example of an airtight joint.

なお、例えば2個ずつ近接して多数のE P R0Mチ
ップが搭載しであるパッケージにおいては、EPROM
チップ2個に対してサファイヤ製キャップを1個設ける
というように適宜サファイヤ窓の数を変更してもよい。
For example, in a package in which a large number of EPROM chips are mounted two in close proximity, the EPROM
The number of sapphire windows may be changed as appropriate, such as providing one sapphire cap for two chips.

このようにサファイヤの薄板からなる紫外線透過窓の1
個の大きさを小さくした場合には、ヒートショックに対
する耐性がさらに向上する。
In this way, one of the ultraviolet transmitting windows made of a thin sapphire plate
When the size of the particles is reduced, resistance to heat shock is further improved.

[発明の効果] 以上説明したように、本発明のEPROMチップ搭載パ
ッケージは、銀ろう付けの可能なサフィヤで紫外線透過
窓を形成したので、耐熱性および耐湿性を著しく向上さ
せることができる。またサファイヤはセラミックあるい
はコバールとの熱膨張係数の差が小さいので、ヒートシ
ョックに対する耐性も著しく向上している。特に金属キ
ャップとしC、サファイヤと熱膨張係数がほぼ等しいコ
バールを用いた場合には、ヒートショックに対する信頼
性は一55℃から+150℃の温痩範囲で充分維持する
ことができる。
[Effects of the Invention] As explained above, in the EPROM chip mounting package of the present invention, the ultraviolet transmitting window is formed of sapphire that can be soldered with silver, so that heat resistance and moisture resistance can be significantly improved. Furthermore, since sapphire has a small difference in coefficient of thermal expansion from ceramic or Kovar, it has significantly improved resistance to heat shock. In particular, when the metal cap is made of C or Kovar, which has a coefficient of thermal expansion almost equal to that of sapphire, reliability against heat shock can be sufficiently maintained in the temperature range of -55°C to +150°C.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明のEPROMチップ搭載パッケージの実
施例の横断面図、第2図は従来のEPROMチップ搭載
パッケージの横断面図、第3図は本発明の他の実施例の
EPROMチップ搭載パッケージの上面図である。 1.7・・・・・・EPROMチップ 2.6・・・・・・セラミック配線基板4・・・・・・
・・・・・・接着剤 8・・・・・・・・・・・・メタライズ層9・・・・・
・・・・・・・ニッケル及び金メッキ層10・・・・・
・・・・・・・サファイヤの薄板11・・・・・・・・
・・・・コバール製キャップ代理人弁理士 須 山 佐
 − 第3図
FIG. 1 is a cross-sectional view of an embodiment of an EPROM chip-mounted package of the present invention, FIG. 2 is a cross-sectional view of a conventional EPROM chip-mounted package, and FIG. 3 is a cross-sectional view of an EPROM chip-mounted package of another embodiment of the present invention. FIG. 1.7... EPROM chip 2.6... Ceramic wiring board 4...
...Adhesive 8...Metalized layer 9...
...Nickel and gold plating layer 10...
・・・・・・Sapphire thin plate 11・・・・・・・・・
・・・Kobar Cap Representative Patent Attorney Sa Suyama - Figure 3

Claims (3)

【特許請求の範囲】[Claims] (1)セラミック配線基板上に搭載されたEPROMチ
ップをサファイヤからなる窓を有する金属キャップで気
密に覆って成ることを特徴とするEPROMチップ搭載
パッケージ。
(1) An EPROM chip mounting package characterized in that an EPROM chip mounted on a ceramic wiring board is hermetically covered with a metal cap having a window made of sapphire.
(2)金属キャップがコバールから成る特許請求の範囲
第1項記載のEPROMチップ搭載パッケージ。
(2) The EPROM chip mounting package according to claim 1, wherein the metal cap is made of Kovar.
(3)サフアイヤからなる窓が、コバール製キャップに
設けた打抜き孔の周囲にメタライズ層およびニッケルメ
ッキ層を順に形成し、この:ツルメッキ層上にサフアイ
ヤの薄板を銀ろう付けして構成され°【いる特許請求の
範囲第1項または第2項記載のEPROMチップ搭載パ
ッケージ。
(3) The window made of sapphire is constructed by sequentially forming a metallized layer and a nickel plating layer around the punched hole in the Kovar cap, and then silver-brazing a thin plate of sapphire onto the vine plating layer. An EPROM chip mounting package according to claim 1 or 2.
JP11167784A 1984-05-31 1984-05-31 Mounting package of eprom chip Granted JPS60254753A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11167784A JPS60254753A (en) 1984-05-31 1984-05-31 Mounting package of eprom chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11167784A JPS60254753A (en) 1984-05-31 1984-05-31 Mounting package of eprom chip

Publications (2)

Publication Number Publication Date
JPS60254753A true JPS60254753A (en) 1985-12-16
JPH031836B2 JPH031836B2 (en) 1991-01-11

Family

ID=14567382

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11167784A Granted JPS60254753A (en) 1984-05-31 1984-05-31 Mounting package of eprom chip

Country Status (1)

Country Link
JP (1) JPS60254753A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58158950A (en) * 1982-03-16 1983-09-21 Nec Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58158950A (en) * 1982-03-16 1983-09-21 Nec Corp Semiconductor device

Also Published As

Publication number Publication date
JPH031836B2 (en) 1991-01-11

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