JPH031836B2 - - Google Patents
Info
- Publication number
- JPH031836B2 JPH031836B2 JP59111677A JP11167784A JPH031836B2 JP H031836 B2 JPH031836 B2 JP H031836B2 JP 59111677 A JP59111677 A JP 59111677A JP 11167784 A JP11167784 A JP 11167784A JP H031836 B2 JPH031836 B2 JP H031836B2
- Authority
- JP
- Japan
- Prior art keywords
- eprom chip
- kovar
- wiring board
- eprom
- cap body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 20
- 239000000919 ceramic Substances 0.000 claims description 20
- 229910000833 kovar Inorganic materials 0.000 claims description 19
- 229910052594 sapphire Inorganic materials 0.000 claims description 17
- 239000010980 sapphire Substances 0.000 claims description 17
- 229910052759 nickel Inorganic materials 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 238000007747 plating Methods 0.000 claims description 8
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 4
- 238000005219 brazing Methods 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 239000004332 silver Substances 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 description 8
- 230000001070 adhesive effect Effects 0.000 description 8
- 239000011521 glass Substances 0.000 description 6
- 238000007789 sealing Methods 0.000 description 6
- 230000035939 shock Effects 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- MUJOIMFVNIBMKC-UHFFFAOYSA-N fludioxonil Chemical compound C=12OC(F)(F)OC2=CC=CC=1C1=CNC=C1C#N MUJOIMFVNIBMKC-UHFFFAOYSA-N 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/18—Circuits for erasing optically
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明はEPROMチツプをセラミツク配線基板
上に搭載して成るパツケージに係り、特に耐熱性
など要求される環境での使用に適するEPROMチ
ツプ搭載パツケージに関する。[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to a package in which an EPROM chip is mounted on a ceramic wiring board, and is particularly suitable for use in an environment where heat resistance is required. Regarding packages equipped with suitable EPROM chips.
（従来の技術）
EPROMチツプ搭載パツケージは、書込まれた
メモリデータを紫外線の照射によつて消去するた
め、EPROM上を紫外線透過性のガラス板により
気密に覆つて構成されている。(Prior Art) A package equipped with an EPROM chip is configured such that the EPROM is hermetically covered with an ultraviolet-transparent glass plate in order to erase the written memory data by irradiating it with ultraviolet rays.
第２図は、このような従来のEPROM搭載パツ
ケージを示すもので、EPROMチツプ１を搭載し
たセラミツク配線基板２上にセラミツクリング３
を接着剤４で接着し、その上に紫外線透過ガラス
５を接着剤４で接着して構成されている。 Figure 2 shows such a conventional EPROM mounting package, in which a ceramic ring 3 is mounted on a ceramic wiring board 2 on which an EPROM chip 1 is mounted.
is adhered with an adhesive 4, and an ultraviolet transmitting glass 5 is adhered thereon with an adhesive 4.
なお接着剤４としては、一般にエポキシ樹脂の
ような有機接着剤もしくは低融点ガラスが用いら
れている。 Note that as the adhesive 4, an organic adhesive such as an epoxy resin or a low melting point glass is generally used.
（発明が解決しようとする課題）
ところで、従来セラミツクリング３および紫外
線透過ガラス５の接着に用いられていたエポキシ
樹脂のような有機接着剤は、完全な気密性を有し
ていないので、このようにして構成されたパツケ
ージは耐湿性に乏しい難点があつた。(Problem to be Solved by the Invention) By the way, organic adhesives such as epoxy resins conventionally used for bonding the ceramic ring 3 and the ultraviolet-transmitting glass 5 do not have perfect airtightness. The package cage constructed in this way had the disadvantage of poor moisture resistance.
またこのような有機接着剤は、ガラスやセラミ
ツクとの熱膨張係数の差が大きく、また耐熱性も
劣るので、使用可能温度は０℃以上70℃程度まで
の間に限定されてしまうという難点もあつた。 Additionally, organic adhesives have a large difference in thermal expansion coefficient from glass and ceramics, and they also have poor heat resistance, so they have the disadvantage that their usable temperature is limited to between 0°C and 70°C. It was hot.
一方、低融点ガラスを接着剤として用いた場合
は、気密封止性ないし耐湿性など改善されるが、
耐熱性の点で問題がある。つまり、この種の
EPROMチツプ搭載パツケージは、航空機搭載用
あるいは放送衛星搭載用の電子機器類など特殊な
環境でも多用されつつある。しかして、このよう
な特殊分野などにおいては、前記気密性だけでな
く、封止機構についての耐熱性も要求される。 On the other hand, when low melting point glass is used as an adhesive, airtightness and moisture resistance are improved, but
There is a problem with heat resistance. That is, this kind of
Packages equipped with EPROM chips are increasingly being used in special environments such as electronic equipment mounted on aircraft or broadcasting satellites. Therefore, in such special fields, not only the above-mentioned airtightness but also heat resistance of the sealing mechanism is required.
しかしながら、従来のEPROMチツプ搭載パツ
ケージは、前記のようなさらに厳しい耐湿性や温
度特性を要求されるたとえばMIL規格などを満
足させることは不可能であつた。 However, it has been impossible for conventional EPROM chip-mounted packages to satisfy the above-mentioned MIL standards, which require even more stringent moisture resistance and temperature characteristics.
本発明は上記の点に対処してなされたもので、
耐熱性と耐湿性を飛躍的に向上させたEPROMチ
ツプ搭載パツケージを提供することを目的とする
ものである。 The present invention has been made in response to the above points, and
The objective is to provide a package equipped with an EPROM chip that has dramatically improved heat resistance and moisture resistance.
［発明の構成］
（課題を解決するための手段）
本発明に係るEPROMチツプ搭載パツケージ
は、セラミツク配線基板と、このセラミツク配線
基板面上に搭載されたEPROMチツプと、この
EPROMチツプを封止するように一方の開口部が
前記セラミツク配線基板面上にメタライズ層およ
びニツケルメツキ層系を介して気密に配設された
コバール製金属キヤツプ本体と、このコバール製
金属キヤツプ本体の他方の開口部をメタライズ層
およびニツケルメツキ層系を介して銀ロー付けに
よつて気密に封止し紫外線を前記封装された
EPROMチツプ面に導光するサフアイヤ製窓とを
具備して成ることを特徴とする。[Structure of the Invention] (Means for Solving the Problems) An EPROM chip mounting package according to the present invention includes a ceramic wiring board, an EPROM chip mounted on the surface of the ceramic wiring board, and an EPROM chip mounted on the surface of the ceramic wiring board.
A metal cap body made of Kovar, one opening of which is airtightly disposed on the surface of the ceramic wiring board via a metallized layer and a nickel plating layer system so as to seal the EPROM chip, and the other metal cap body made of Kovar. The opening is hermetically sealed by silver brazing through the metallized layer and the nickel metal layer system, and ultraviolet rays are passed through the sealed area.
It is characterized by being equipped with a sapphire window that guides light to the EPROM chip surface.
（作用）
本発明においては、EPROMチツプを封止する
キヤツプ本体としてコバール製を用い、セラミツ
ク配線基板面に対しては、メタライズ層およびニ
ツケルメツキ層を介在させ封止したことによつ
て、良好な耐湿性および耐熱性を保持した気密封
止が達成される。また、紫外線を封装された
EPROMチツプ面に導光する窓としてサフアイヤ
を用いかつ、この端縁部を予め打抜かれたキヤツ
プ本体の開口端縁部に銀ロー付けしたことによつ
て、良好な耐湿性および耐熱性を保持した構成を
維持する。しかも、前記封止部は互いに封止に関
与する材料の熱膨脹係数も比較的近似しているた
め、熱的な作用による封止構造の破損ないし気密
性低下の恐れもない。(Function) In the present invention, Kovar is used as the cap body for sealing the EPROM chip, and the ceramic wiring board surface is sealed with a metalized layer and a nickel plating layer, which provides good moisture resistance. A hermetic seal is achieved that maintains properties and heat resistance. It is also UV sealed
By using sapphire as the window that guides light to the EPROM chip surface, and by silver brazing the edge of this to the edge of the opening of the cap body, which has been punched out in advance, it maintains good moisture resistance and heat resistance. Maintain configuration. Moreover, since the thermal expansion coefficients of the materials involved in sealing are relatively similar to each other in the sealing portions, there is no fear of damage to the sealing structure or deterioration of airtightness due to thermal effects.
（実施例）
第１図は、本発明のEPROMチツプ搭載パツケ
ージの実施例の横断面図である。(Embodiment) FIG. 1 is a cross-sectional view of an embodiment of an EPROM chip mounting package of the present invention.
第１図において、セラミツク配線基板６上には
複数個のEPROMチツプ７が搭載されている。 In FIG. 1, a plurality of EPROM chips 7 are mounted on a ceramic wiring board 6.
セラミツク配線基板６の周縁部にはモリブデン
あるいはタングステンペーストなどの焼成による
メタライズ層８とニツケルおよび金のメツキ層９
とがEPROMチツプ７搭載部を囲んで順に積層形
成されている。 A metallized layer 8 made of molybdenum or tungsten paste and a plating layer 9 of nickel and gold are formed on the periphery of the ceramic wiring board 6.
are stacked in order surrounding the EPROM chip 7 mounting section.
このニツケルおよびび金のメツキ層９上には、
サフアイヤの薄板１０からなる紫外線透過（導
光）窓を有するコバール製キヤツプ本体１１の開
口端部が気密にハンダ１２により接合されてい
る。 On this plating layer 9 of nickel and gold,
The open end of a Kovar cap main body 11 having an ultraviolet light transmitting (light guiding) window made of a thin sapphire plate 10 is hermetically joined with solder 12.
なお、コバール製キヤツプ本体１１とセラミツ
ク配線基板６との接合は、一旦上記した方法によ
りコバールウエルドリングをセラミツク配線基板
６上に銀ろう付けし、この上にコバール製キヤツ
プ本体１１の開口端部をレーザ溶接することによ
り行なつてもよい。 Note that the Kovar cap body 11 and the ceramic wiring board 6 are joined together by first silver-brazing the Kovar weld ring onto the ceramic wiring board 6 using the method described above, and then attaching the open end of the Kovar cap body 11 on top of this. This may also be done by laser welding.
上述したサフアイヤの薄板１０は、コバール製
キヤツプ本体１１の中央に打抜き孔（他の開口
部）を設け、その周縁部を凹陥させ、この凹陥部
に接合させることによりコバール製キヤツプ本体
１１に固着されている。ここで、コバール製キヤ
ツプ本体１１とサフアイヤの薄板１０との接合
は、サフアイヤの薄板１０の周辺部に予めタング
ステンペーストなどによるメタライズ層とニツケ
ルメツキ層とを順に形成しておき、それをコバー
ル製キヤツプ本体１１の打抜き孔の凹陥部に載せ
て銀ろう１３付けすることにより行なわれる。 The thin saphire plate 10 described above is fixed to the Kovar cap body 11 by providing a punched hole (another opening) in the center of the Kovar cap body 11, recessing the peripheral edge of the hole, and bonding it to this recess. ing. Here, in order to join the Kovar cap body 11 and the thin sapphire plate 10, a metallized layer of tungsten paste or the like and a nickel plating layer are formed in advance on the periphery of the sapphire thin plate 10, and then the Kovar cap body 11 and the sapphire thin plate 10 are joined together. This is done by placing silver solder 13 on the recessed part of the punched hole 11.
なお、この実施例に示したように、金属性キヤ
ツプ本体としてコバールのようなサフアイヤおよ
びセラミツク基板と熱膨張係数がほぼ等しい金属
性のものを使用すればヒートシヨツクに対する耐
性が向上する。 As shown in this embodiment, resistance to heat shock is improved if a metal material such as Kovar, which has a coefficient of thermal expansion approximately equal to that of the sapphire or ceramic substrate, is used as the metal cap body.
第１図に示した実施例においては、コバール製
キヤツプ本体１１の中央上面に１枚の大きなサフ
アイヤの薄板１０からなる紫外線透過窓を設けた
例について説明したが、本発明はかかる実施例に
限定されるものではなく、各EPROMに対応させ
て複数個のサフアイヤ窓を形成するようにしても
よい。 In the embodiment shown in FIG. 1, an example was explained in which an ultraviolet transmitting window made of one large thin sapphire plate 10 was provided on the upper center surface of the cap body 11 made of Kovar, but the present invention is limited to such an embodiment. Instead, a plurality of sapphire windows may be formed corresponding to each EPROM.
第１図と共通する部分に同一符号を付した第３
図は、このような実施例を示すもので、コバール
製キヤツプ本体１１の上面にEPROMチツプ７の
１個毎に、これに紫外線を照射するのに十分な大
きさの打抜き孔（開口部）を設け、この打抜き孔
にサフアイヤの薄板１０をそれぞれ第１図に示し
た実施例と同様にして気密に接合した例である。 3. Parts common to those in Figure 1 are given the same reference numerals.
The figure shows such an embodiment, in which a punched hole (opening) large enough to irradiate each EPROM chip 7 with ultraviolet rays is formed on the top surface of the Kovar cap body 11. This is an example in which a thin sapphire plate 10 is hermetically joined to the punched hole in the same manner as in the embodiment shown in FIG.
なお、たとえば２個ずつ近接して多数の
EPROMチツプが搭載してあるパツケージにおい
ては、EPROMチツプ２個に対してサフアイヤ製
キヤツプを１個設けるというように適宜サフアイ
ヤ窓の数を変更してもよい。 In addition, for example, if a large number of
In a package equipped with EPROM chips, the number of sapphire windows may be changed as appropriate, such as providing one sapphire cap for two EPROM chips.
このようにサフアイヤの薄板からなる紫外線透
過窓の１個の大きさを小さくした場合には、ヒー
トシヨツクに対する耐性がさらに向上する。 When the size of each ultraviolet transmitting window made of a thin sapphire plate is reduced in this way, the resistance to heat shock is further improved.
［発明の効果］
以上説明したように、本発明のEPROMチツプ
搭載パツケージは、銀ろう付けの可能なサフイヤ
で紫外線透過窓を形成しかつ、それらの封止部を
メタライズ層およびニツケルメツキ層など介在さ
せて構成したので、耐熱性および耐湿性を著しく
向上させることができる。つまり、前記サフアイ
ヤはセラミツクあるいはコバールとの熱膨張係数
の差が小さいので、ヒートシヨツクに対する耐性
も著しく向上している。また、金属キヤツプ本体
を、サフアイヤと熱膨張係数がほぼ等しいコバー
ルを用いたことにより、ヒートシヨツクに対する
信頼性も−55℃から＋150℃の温度範囲で充分維
持することができる。[Effects of the Invention] As explained above, the EPROM chip mounting package of the present invention has an ultraviolet transmitting window formed of sapphire that can be soldered with silver, and a metallized layer, a nickel plating layer, etc. interposed between the sealing portions. Since the structure is configured as follows, heat resistance and moisture resistance can be significantly improved. In other words, since the sapphire has a small difference in coefficient of thermal expansion from ceramic or kovar, its resistance to heat shock is significantly improved. Furthermore, by using Kovar, which has a coefficient of thermal expansion almost equal to that of sapphire, for the metal cap body, reliability with respect to the heat shock can be maintained sufficiently in the temperature range of -55°C to +150°C.
かくして、本発明に係るEPROMチツプ搭載パ
ツケージは、良好な気密封止性と耐熱性ないし耐
ヒートシヨツク性を兼備している点から、たとえ
ば航空機や放送衛星などの搭載に適するものとい
える。 Thus, the EPROM chip-mounted package according to the present invention has both good hermetic sealability and heat resistance or heat shock resistance, and is therefore suitable for mounting on aircraft, broadcasting satellites, etc., for example.
第１図は本発明のEPROMチツプ搭載パツケー
ジの実施例の横断面図、第２図は従来のEPROM
チツプ搭載パツケージの横断面図、第３図は本発
明の他の実施例のEPROMチツプ搭載パツケージ
の上面図である。
１，７……EPROMチツプ、２，６……セラミ
ツク配線基板、４……接着剤、８……メタライズ
層、９……ニツケルおよび金メツキ層、１０……
サフアイヤの薄板、１１……コバール製キヤツ
プ。
Figure 1 is a cross-sectional view of an embodiment of the EPROM chip-mounted package of the present invention, and Figure 2 is a cross-sectional view of a conventional EPROM chip package.
FIG. 3 is a cross-sectional view of the chip mounting package, and FIG. 3 is a top view of the EPROM chip mounting package according to another embodiment of the present invention. 1, 7... EPROM chip, 2, 6... Ceramic wiring board, 4... Adhesive, 8... Metallized layer, 9... Nickel and gold plating layer, 10...
Saphire thin plate, 11... Kovar cap.
Claims (1)
基板面上に搭載されたEPROMチツプと、この
EPROMチツプを封止するように一方の開口部が
前記セラミツク配線基板面上にメタライズ層およ
びニツケルメツキ層系を介して気密に配設された
コバール製金属キヤツプ本体と、このコバール製
金属キヤツプ本体の他方の開口部をメタライズ層
およびニツケルメツキ層系を介して銀ロー付けに
よつて気密に封止し紫外線を前記封装された
EPROMチツプ面に導光するサフアイヤ製窓とを
具備して成ることを特徴とするEPROMチツプ搭
載パツケージ。1 A ceramic wiring board, an EPROM chip mounted on the ceramic wiring board, and
A metal cap body made of Kovar, one opening of which is airtightly disposed on the surface of the ceramic wiring board via a metallized layer and a nickel plating layer system so as to seal the EPROM chip, and the other metal cap body made of Kovar. The opening is hermetically sealed by silver brazing through the metallized layer and the nickel metal layer system, and ultraviolet rays are passed through the sealed area.
An EPROM chip-mounted package characterized by comprising a sapphire window that guides light onto the EPROM chip surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11167784A JPS60254753A (en) | 1984-05-31 | 1984-05-31 | Mounting package of eprom chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11167784A JPS60254753A (en) | 1984-05-31 | 1984-05-31 | Mounting package of eprom chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60254753A JPS60254753A (en) | 1985-12-16 |
| JPH031836B2 true JPH031836B2 (en) | 1991-01-11 |
Family
ID=14567382
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11167784A Granted JPS60254753A (en) | 1984-05-31 | 1984-05-31 | Mounting package of eprom chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60254753A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58158950A (en) * | 1982-03-16 | 1983-09-21 | Nec Corp | Semiconductor device |
-
1984
- 1984-05-31 JP JP11167784A patent/JPS60254753A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58158950A (en) * | 1982-03-16 | 1983-09-21 | Nec Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60254753A (en) | 1985-12-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0421005B1 (en) | Process of assembling an electronic package | |
| JP2943760B2 (en) | Hermetic sealing method and hermetic sealing structure for optical fiber introduction section | |
| EP0089044A2 (en) | A semiconductor device having a container sealed with a solder of low melting point | |
| US4992628A (en) | Ceramic-glass integrated circuit package with ground plane | |
| CA1242520A (en) | Package for optical element | |
| US5258575A (en) | Ceramic glass integrated circuit package with integral ground and power planes | |
| US4229758A (en) | Package for semiconductor devices with first and second metal layers on the substrate of said package | |
| US5134246A (en) | Ceramic-glass integrated circuit package with integral ground and power planes | |
| JPH031836B2 (en) | ||
| JP2970723B2 (en) | Semiconductor package and manufacturing method thereof | |
| US5063435A (en) | Semiconductor device | |
| JP2668995B2 (en) | Semiconductor device | |
| JPS59111350A (en) | Semiconductor device | |
| JP2002313973A (en) | Package for optical communication | |
| JP2002228891A (en) | Package for optical communication and method for manufacturing the same | |
| JP2669310B2 (en) | Semiconductor integrated circuit device and mounting method thereof | |
| JPS61152112A (en) | Surface acoustic wave device | |
| JPH0287655A (en) | Semiconductor device | |
| JP2728585B2 (en) | Package for storing semiconductor elements | |
| JP3051225B2 (en) | Package for integrated circuit | |
| JPH043499Y2 (en) | ||
| JPH03285348A (en) | Hybrid ic | |
| KR100673645B1 (en) | A chip package and manufacturing method thereof | |
| JPS6043660B2 (en) | semiconductor equipment | |
| JPS5880846A (en) | Solid state image pickup device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |