JPH05315626A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05315626A JPH05315626A JP4117303A JP11730392A JPH05315626A JP H05315626 A JPH05315626 A JP H05315626A JP 4117303 A JP4117303 A JP 4117303A JP 11730392 A JP11730392 A JP 11730392A JP H05315626 A JPH05315626 A JP H05315626A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- electrode portion
- optical semiconductor
- semiconductor element
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、光電変換機能を有す
る半導体素子（以下、「光半導体素子」という。）を基
板に一体化させた半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor element having a photoelectric conversion function (hereinafter referred to as "optical semiconductor element") is integrated with a substrate.
【０００２】[0002]
【従来の技術】従来、高密度実装を要求される産業機器
には、図５に示す半導体装置が用いられている。図５は
従来の半導体装置の構成を示す断面図である。図５にお
いて、１は上面および下面に電極部２，８を有した光半
導体素子、３０はＡｕ線からなるワイヤ、４０はリー
ド、５０は表面に所定パターン形状の引出し電極部６０
を有した基板、７０は半田、１００は樹脂である。2. Description of the Related Art Conventionally, a semiconductor device shown in FIG. 5 has been used for industrial equipment which requires high-density mounting. FIG. 5 is a sectional view showing the structure of a conventional semiconductor device. In FIG. 5, 1 is an optical semiconductor element having electrode portions 2 and 8 on the upper and lower surfaces, 30 is a wire made of Au wire, 40 is a lead, and 50 is a lead electrode portion 60 having a predetermined pattern on the surface.
Board 70, solder 70, and resin 100.
【０００３】図５に示すように、光半導体素子１の上面
に形成した電極部２（アノード電極）と、リード４０と
はワイヤ３０により電気的に接続されている。また、リ
ード４０は、基板５０に形成された引出し電極部６に半
田７０により電気的に接続されている。また、光半導体
素子１の下面の電極部８０は、リード４０の素子搭載部
９にマウントされている。そして、光半導体素子１の周
囲を樹脂１００で封止することで、ワイヤ３０等を保護
している。As shown in FIG. 5, an electrode portion 2 (anode electrode) formed on the upper surface of the optical semiconductor element 1 and a lead 40 are electrically connected by a wire 30. Further, the lead 40 is electrically connected to the extraction electrode portion 6 formed on the substrate 50 by the solder 70. The electrode portion 80 on the lower surface of the optical semiconductor element 1 is mounted on the element mounting portion 9 of the lead 40. Then, the wire 30 and the like are protected by sealing the periphery of the optical semiconductor element 1 with the resin 100.
【０００４】このように従来の半導体装置は、光半導体
素子１の電極部８をリード４０に電気的に接続し、かつ
基板５０上に形成した引出し電極部６０に、ワイヤ３０
およびリード４０を介して電極部２を電気的に接続し、
さらに樹脂１００により封止したものである。As described above, in the conventional semiconductor device, the electrode portion 8 of the optical semiconductor element 1 is electrically connected to the lead 40, and the lead electrode portion 60 formed on the substrate 50 is connected to the wire 30.
And electrically connecting the electrode portion 2 via the lead 40,
Further, it is sealed with resin 100.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、このよ
うに構成された従来の半導体装置では、光半導体素子１
の上面の電極部２と、基板５０上の引出し電極部６０を
電気的に接続するために、リード４０およびワイヤ３０
が必要となるため、電極部２の数すなわち電極数をあま
り多くすることができず、また、ワイヤ３０を保護する
ために樹脂１００が必要となり、小型化および薄型化が
困難であるという問題があった。However, in the conventional semiconductor device having such a configuration, the optical semiconductor element 1 is used.
In order to electrically connect the electrode part 2 on the upper surface of the substrate and the extraction electrode part 60 on the substrate 50,
Therefore, the number of electrode portions 2, that is, the number of electrodes cannot be increased so much, and the resin 100 is required to protect the wire 30, which makes it difficult to reduce the size and thickness. there were.
【０００６】この発明の目的は、上記問題点に鑑み、高
密度実装に適した小型で薄型の半導体装置を提供するこ
とである。In view of the above problems, an object of the present invention is to provide a small and thin semiconductor device suitable for high density mounting.
【０００７】[0007]
【課題を解決するための手段】請求項１記載の半導体装
置は、上面および下面に第１および第２の電極部を有す
る光半導体素子と、光を透過し所定間隔を設けて素子搭
載部および所定パターン形状の引出し電極部を有した基
板とを備え、素子搭載部上に光半導体素子を載置して素
子搭載部に第２の電極部を電気的に接続するとともに、
基板を折り曲げて光半導体素子の上部に引出し電極部を
位置決めして引出し電極部に第１の電極部を電気的に接
続したものである。According to a first aspect of the present invention, there is provided a semiconductor device having an optical semiconductor element having first and second electrode portions on an upper surface and a lower surface, an element mounting portion which transmits light and is provided at a predetermined interval. A substrate having a lead-out electrode portion having a predetermined pattern, and mounting an optical semiconductor element on the element mounting portion to electrically connect the second electrode portion to the element mounting portion,
The substrate is bent, the extraction electrode portion is positioned above the optical semiconductor element, and the extraction electrode portion is electrically connected to the first electrode portion.
【０００８】請求項２記載の半導体装置は、上面および
下面に第１および第２の電極部を有する光半導体素子
と、所定間隔を有して素子搭載部および所定パターン形
状の引出し電極部を有し、かつこの引出し電極部近傍に
開口窓を有した基板とを備え、素子搭載部上に光半導体
素子を載置して素子搭載部に第２の電極部を電気的に接
続するとともに、基板を折り曲げて光半導体素子の上部
に開口窓および引出し電極部を位置決めして引出し電極
部に第１の電極部を電気的に接続したものである。According to a second aspect of the present invention, there is provided a semiconductor device having an optical semiconductor element having first and second electrode portions on an upper surface and a lower surface, an element mounting portion having a predetermined interval and a lead electrode portion having a predetermined pattern shape. And a substrate having an opening window in the vicinity of the extraction electrode portion, an optical semiconductor element is mounted on the element mounting portion to electrically connect the second electrode portion to the element mounting portion, and the substrate Is bent to position the opening window and the extraction electrode portion above the optical semiconductor element, and the first electrode portion is electrically connected to the extraction electrode portion.
【０００９】[0009]
【作用】この発明の構成によれば、基板の素子搭載部上
に光半導体素子を載置して第２の電極部を素子搭載部に
電気的に接続し、基板を折り曲げて光半導体素子の上部
に第１の電極部を位置決めして第１の電極部を引出し電
極部に電気的に接続したため、従来の半導体装置におけ
るリード，ワイヤおよび樹脂が不要となる。According to the structure of the present invention, the optical semiconductor element is placed on the element mounting portion of the substrate, the second electrode portion is electrically connected to the element mounting portion, and the substrate is bent to form the optical semiconductor element. Since the first electrode portion is positioned on the upper portion and the first electrode portion is electrically connected to the extraction electrode portion, the lead, wire and resin in the conventional semiconductor device are unnecessary.
【００１０】[0010]
【実施例】図１はこの発明の第１の実施例の半導体装置
の構成を示す断面図である。図１に示す光半導体素子１
は、チップ厚０．３〔ｍｍ〕のシリコン受光素子であ
り、上面には受光面である光電変換部１３およびＡｕか
らなる第１の電極部（アノード電極）２を有し、下面に
Ａｕからなる第２の電極部８を有したものである。1 is a sectional view showing the structure of a semiconductor device according to a first embodiment of the present invention. Optical semiconductor device 1 shown in FIG.
Is a silicon light receiving element having a chip thickness of 0.3 [mm], has a photoelectric conversion portion 13 which is a light receiving surface and a first electrode portion (anode electrode) 2 made of Au on the upper surface, and is made of Au on the lower surface. The second electrode part 8 is formed.
【００１１】また、基板５ａは、光を透過する厚さ０．
２〔ｍｍ〕のフレキシブル基板であり、赤外光の損失が
１０％以下と小さいものである。表面には、所定間隔を
設けて素子搭載部１１およびＡｕからなる所定パターン
形状の引出し電極部６を有している。このような基板５
ａの素子搭載部１１上に、光半導体素子１の下面を載置
し、熱圧着法により素子搭載部１１と第２の電極部８と
を電気的に接続してある。そして、基板５ａを折り曲げ
て光半導体素子１の第１の電極部２の上部に引出し電極
部６を位置決めし、熱圧着法により引出し電極部６と第
１の電極部２とを電気的に接続したものである。The substrate 5a has a thickness of 0.
It is a flexible substrate of 2 mm and has a small loss of infrared light of 10% or less. On the surface, there are provided lead-out electrode portions 6 having a predetermined pattern shape, which are made of Au and are provided with element mounting portions 11 at predetermined intervals. Such a substrate 5
The lower surface of the optical semiconductor element 1 is placed on the element mounting portion 11 of a, and the element mounting portion 11 and the second electrode portion 8 are electrically connected by thermocompression bonding. Then, the substrate 5a is bent to position the extraction electrode portion 6 on the first electrode portion 2 of the optical semiconductor element 1, and the extraction electrode portion 6 and the first electrode portion 2 are electrically connected by thermocompression bonding. It was done.
【００１２】このように光半導体素子１の下面の第２の
電極部８を基板５ａの素子搭載部１１に固着させて接続
し、基板５ａを折り曲げて光半導体素子１の上面の第１
の電極部２を基板５ａの引出し電極部６に固着させて接
続したことで、従来の半導体装置におけるリード４０，
ワイヤ３０および樹脂１００が不要となる。また、基板
５ａとして赤外光を良好に透過させる材質を用いること
で、光半導体素子１の光電変換部１３での光の損失は小
さなものとなる。In this way, the second electrode portion 8 on the lower surface of the optical semiconductor element 1 is fixedly connected to the element mounting portion 11 of the substrate 5a, the substrate 5a is bent and the first electrode on the upper surface of the optical semiconductor element 1 is bent.
Since the electrode portion 2 of the above is fixedly connected to the lead electrode portion 6 of the substrate 5a, the leads 40 in the conventional semiconductor device,
The wire 30 and the resin 100 are unnecessary. Further, by using a material that transmits infrared light favorably as the substrate 5a, the loss of light in the photoelectric conversion unit 13 of the optical semiconductor element 1 becomes small.
【００１３】次に、図２および図３を参照しながら、こ
の発明の第２の実施例の半導体装置について説明する。
なお、図２は同半導体装置の構成を示す断面図、図３は
同半導体装置の構成を示す斜視図であり、図１と同符号
の部分は同様の部分を示す。図２および図３に示す基板
５ｂは、光を透過しにくいフレキシブル基板であり、光
半導体素子１の光電変換部１３の領域よりも大きな１ｍ
ｍ平方の開口窓１２を有したものである。また、表面に
は、所定間隔を設けて素子搭載部１１およびＡｕからな
る所定パターン形状の引出し電極部６を有している。Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS.
2 is a cross-sectional view showing the structure of the same semiconductor device, FIG. 3 is a perspective view showing the structure of the same semiconductor device, and the same symbols as in FIG. 1 indicate the same parts. The substrate 5b shown in FIGS. 2 and 3 is a flexible substrate that does not easily transmit light, and is 1 m larger than the region of the photoelectric conversion unit 13 of the optical semiconductor element 1.
It has an opening window 12 of m square. Further, on the surface, there are provided lead-out electrode portions 6 each having a predetermined pattern and formed of element mounting portions 11 and Au at predetermined intervals.
【００１４】このような基板５ｂの素子搭載部１１上
に、光半導体素子１の下面を載置し、熱圧着法により素
子搭載部１１と第２の電極部８とを電気的に接続してあ
る。そして、基板５ｂを折り曲げて光半導体素子１の第
１の電極部２の上部に引出し電極部６を位置決めし、か
つ光半導体素子１の光電変換部１３の上部に開口窓１２
を位置決めし、熱圧着法により引出し電極部６と第１の
電極部２とを電気的に接続したものである。この開口窓
１２は外部から光電変換部１３への光の透過経路とな
る。The lower surface of the optical semiconductor element 1 is placed on the element mounting portion 11 of the substrate 5b, and the element mounting portion 11 and the second electrode portion 8 are electrically connected by thermocompression bonding. is there. Then, the substrate 5b is bent to position the extraction electrode portion 6 above the first electrode portion 2 of the optical semiconductor element 1, and the opening window 12 is provided above the photoelectric conversion portion 13 of the optical semiconductor element 1.
Is positioned, and the extraction electrode portion 6 and the first electrode portion 2 are electrically connected by the thermocompression bonding method. The opening window 12 serves as a transmission path of light from the outside to the photoelectric conversion unit 13.
【００１５】このように、光半導体素子１の下面の第２
の電極部８を基板５ｂの素子搭載部１１に固着させて接
続し、基板５ｂを折り曲げて光半導体素子１の上面の第
１の電極部２を基板５ｂの引出し電極部６に固着させて
接続することで、従来の半導体装置におけるリード４
０，ワイヤ３０および樹脂１００が不要となる。また、
光を透過しにくい基板５ｂであっても、基板５ｂに開口
窓１２を設けることで光半導体素子１の光電変換部１３
に良好に受光させることができ、光の損失は小さい。As described above, the second surface of the lower surface of the optical semiconductor element 1 is
The electrode part 8 is fixedly connected to the element mounting part 11 of the substrate 5b, the substrate 5b is bent, and the first electrode part 2 on the upper surface of the optical semiconductor device 1 is fixedly connected to the extraction electrode part 6 of the substrate 5b. By doing so, the lead 4 in the conventional semiconductor device is
No wire 0, wire 30 and resin 100 are required. Also,
Even if the substrate 5b does not easily transmit light, the photoelectric conversion unit 13 of the optical semiconductor element 1 is provided by providing the opening window 12 in the substrate 5b.
The light can be received well, and the light loss is small.
【００１６】次に、図４を参照しながら、この発明の第
３の実施例の半導体装置について説明する。なお、図４
は同半導体装置の構成を示す断面図であり、図２と同符
号の部分は同様の部分を示す。図４において、５ｃは基
板、１４は接着剤となる導電性樹脂である。図４に示す
基板５ｃは、光を透過しにくいフレキシブル基板であ
り、光半導体素子１の光電変換部１３の領域よりも大き
な１ｍｍ平方の開口窓１２および直径０．２〔ｍｍ〕の
スルーホール１５を有したものである。また、表面およ
び裏面には、所定間隔を設けて素子搭載部１１およびス
ルーホール１５を介して形成したＡｕからなる所定パタ
ーン形状の引出し電極部６を有している。Next, a semiconductor device according to a third embodiment of the present invention will be described with reference to FIG. Note that FIG.
FIG. 3 is a cross-sectional view showing the configuration of the same semiconductor device, and the parts having the same reference numerals as those in FIG. In FIG. 4, 5c is a substrate, and 14 is a conductive resin serving as an adhesive. The substrate 5c shown in FIG. 4 is a flexible substrate that does not easily transmit light, and has a 1 mm square opening window 12 and a through hole 15 having a diameter of 0.2 [mm] larger than the area of the photoelectric conversion unit 13 of the optical semiconductor element 1. With. Further, on the front surface and the back surface, there are provided lead-out electrode portions 6 of a predetermined pattern shape made of Au formed through the element mounting portion 11 and the through holes 15 at predetermined intervals.
【００１７】このような基板５ｃの素子搭載部１１上
に、光半導体素子１の下面を載置し、導電性樹脂１４に
より素子搭載部１１と第２の電極部８とを電気的に接続
してある。そして、基板５ｃを折り曲げて光半導体素子
１の第１の電極部２の上部に引出し電極部６を形成した
スルーホール１５を位置決めし、かつ光半導体素子１の
光電変換部１３の上部に開口窓１２を位置決めし、導電
性樹脂１４により引出し電極部６と第１の電極部２とを
電気的に接続したものである。この開口窓１２は外部か
ら光電変換部１３への光の透過経路となる。The lower surface of the optical semiconductor element 1 is placed on the element mounting portion 11 of the substrate 5c, and the element mounting portion 11 and the second electrode portion 8 are electrically connected by the conductive resin 14. There is. Then, the substrate 5c is bent to position the through hole 15 in which the extraction electrode portion 6 is formed above the first electrode portion 2 of the optical semiconductor element 1, and the opening window is provided above the photoelectric conversion portion 13 of the optical semiconductor element 1. 12 is positioned, and the extraction electrode portion 6 and the first electrode portion 2 are electrically connected by the conductive resin 14. The opening window 12 serves as a transmission path of light from the outside to the photoelectric conversion unit 13.
【００１８】このように、光半導体素子１の下面の第２
の電極部８を基板５ｃの素子搭載部１１に固着させて接
続し、基板５ｃを折り曲げて光半導体素子１の上面の第
１の電極部２を基板５ｃの引出し電極部６に固着させて
接続することで、従来の半導体装置におけるリード４
０，ワイヤ３０および樹脂１００が不要となる。また、
光を透過しにくい基板５ｃであっても、基板５ｃに開口
窓１２を設けることで光半導体素子１の光電変換部１３
に受光させることができ、光の損失は小さい。In this way, the second semiconductor layer on the lower surface of the optical semiconductor element 1 is
Electrode portion 8 of the substrate 5c is fixedly connected to the element mounting portion 11 of the substrate 5c, the substrate 5c is bent and the first electrode portion 2 of the upper surface of the optical semiconductor element 1 is fixedly connected to the extraction electrode portion 6 of the substrate 5c. By doing so, the lead 4 in the conventional semiconductor device is
No wire 0, wire 30 and resin 100 are required. Also,
Even if the substrate 5c does not easily transmit light, the photoelectric conversion unit 13 of the optical semiconductor element 1 is provided by providing the opening window 12 in the substrate 5c.
The light loss is small.
【００１９】以上、第１，第２および第３の実施例によ
れば、素子搭載部１１に光半導体素子１を載置して第２
の電極部８を素子搭載部１１に電気的に接続し、基板５
ａ，５ｂまたは５ｃを折り曲げて光半導体素子１の上部
に第１の電極部２を位置決めして第１の電極部２を引出
し電極部６に電気的に接続することで、従来の半導体装
置におけるリード４０，ワイヤ３０および樹脂１００が
不要となる。As described above, according to the first, second and third embodiments, the optical semiconductor element 1 is mounted on the element mounting portion 11 and the second optical semiconductor element 1 is mounted.
Of the substrate 5 by electrically connecting the electrode portion 8 of the
By bending a, 5b or 5c to position the first electrode portion 2 on the optical semiconductor element 1 and electrically connecting the first electrode portion 2 to the extraction electrode portion 6, the conventional semiconductor device The lead 40, the wire 30, and the resin 100 are unnecessary.
【００２０】その結果、従来と比較して光半導体素子１
の電極数の上限が高まり、信頼性が向上するとともに小
型で薄型の半導体装置を得ることができる。なお、第１
の実施例では、光半導体素子１の下面の第２の電極部８
および基板５ａの素子搭載部１１と、光半導体素子１の
上面の第１の電極部２および基板５ａの引出し電極部６
とを熱圧着により電気的に接続したが、第３の実施例の
ように基板５ａの所定位置にスルーホールを形成し、接
着剤となる導電性樹脂１４により固着させて電気的に接
続しても良い。As a result, the optical semiconductor element 1 is different from the conventional one.
The upper limit of the number of electrodes is increased, the reliability is improved, and a small and thin semiconductor device can be obtained. The first
In the embodiment, the second electrode portion 8 on the lower surface of the optical semiconductor element 1 is
And the element mounting portion 11 of the substrate 5a, the first electrode portion 2 on the upper surface of the optical semiconductor element 1, and the extraction electrode portion 6 of the substrate 5a.
Although they were electrically connected by thermocompression bonding, a through hole was formed at a predetermined position of the substrate 5a as in the third embodiment, and the electrically conductive resin 14 serving as an adhesive was used to fix and electrically connect. Is also good.
【００２１】[0021]
【発明の効果】この発明の半導体装置によれば、基板の
素子搭載部上に光半導体素子を載置して第２の電極部を
素子搭載部に電気的に接続し、基板を折り曲げて光半導
体素子の上部に第１の電極部を位置決めして第１の電極
部を引出し電極部に電気的に接続したため、従来の半導
体装置におけるリード，ワイヤおよび樹脂が不要とな
る。According to the semiconductor device of the present invention, the optical semiconductor element is mounted on the element mounting portion of the substrate, the second electrode portion is electrically connected to the element mounting portion, and the substrate is bent to form the optical device. Since the first electrode portion is positioned above the semiconductor element and the first electrode portion is electrically connected to the lead electrode portion, the lead, wire and resin in the conventional semiconductor device are not required.
【００２２】その結果、従来と比較して光半導体素子の
電極数の上限が高まり、信頼性を向上させることができ
るとともに、高密度実装に適応した小型で薄型の半導体
装置を得ることができる。As a result, the upper limit of the number of electrodes of the optical semiconductor element is increased as compared with the conventional one, reliability can be improved, and a small and thin semiconductor device adapted for high-density mounting can be obtained.
【図１】この発明の第１の実施例の半導体装置の構成を
示す断面図である。FIG. 1 is a sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention.
【図２】この発明の第２の実施例の半導体装置の構成を
示す断面図である。FIG. 2 is a sectional view showing the structure of a semiconductor device according to a second embodiment of the present invention.
【図３】同半導体装置の構成を示す斜視図である。FIG. 3 is a perspective view showing a configuration of the same semiconductor device.
【図４】この発明の第３の実施例の半導体装置の構成を
示す断面図である。FIG. 4 is a sectional view showing the structure of a semiconductor device according to a third embodiment of the present invention.
【図５】従来の半導体装置の構成を示す断面図である。FIG. 5 is a cross-sectional view showing a configuration of a conventional semiconductor device.
１ 光半導体素子 ２ 第１の電極部 5a 基板 5b 基板 5c 基板 ６ 引出し電極部 ８ 第２の電極部 11 素子搭載部 12 開口窓 1 Optical Semiconductor Element 2 First Electrode Section 5a Substrate 5b Substrate 5c Substrate 6 Extraction Electrode Section 8 Second Electrode Section 11 Element Mounting Section 12 Opening Window
フロントページの続き (72)発明者 山口 正之 大阪府門真市大字門真1006番地 松下電子 工業株式会社内Front page continued (72) Inventor Masayuki Yamaguchi 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electronics Industrial Co., Ltd.
Claims (2)
部を有する光半導体素子と、光を透過し所定間隔を設け
て素子搭載部および所定パターン形状の引出し電極部を
有した基板とを備え、 前記素子搭載部上に前記光半導体素子を載置して前記素
子搭載部に前記第２の電極部を電気的に接続するととも
に、前記基板を折り曲げて前記光半導体素子の上部に前
記引出し電極部を位置決めして前記引出し電極部に前記
第１の電極部を電気的に接続した半導体装置。1. An optical semiconductor element having first and second electrode portions on its upper and lower surfaces, and a substrate having an element mounting portion and a lead electrode portion having a predetermined pattern and transmitting light and having a predetermined interval. The optical semiconductor element is mounted on the element mounting portion to electrically connect the second electrode portion to the element mounting portion, and the substrate is bent to extend the optical semiconductor element to the upper portion. A semiconductor device in which an electrode portion is positioned and the lead electrode portion is electrically connected to the first electrode portion.
部を有する光半導体素子と、所定間隔を有して素子搭載
部および所定パターン形状の引出し電極部を有し、かつ
この引出し電極部近傍に開口窓を有した基板とを備え、 前記素子搭載部上に前記光半導体素子を載置して前記素
子搭載部に前記第２の電極部を電気的に接続するととも
に、前記基板を折り曲げて前記光半導体素子の上部に前
記開口窓および前記引出し電極部を位置決めして前記引
出し電極部に前記第１の電極部を電気的に接続した半導
体装置。2. An optical semiconductor element having first and second electrode portions on an upper surface and a lower surface, an element mounting portion having a predetermined interval and a lead electrode portion having a predetermined pattern, and the lead electrode portion. A substrate having an opening window in the vicinity thereof, the optical semiconductor element is placed on the element mounting portion to electrically connect the second electrode portion to the element mounting portion, and the substrate is bent. A semiconductor device in which the opening window and the extraction electrode portion are positioned above the optical semiconductor element to electrically connect the first electrode portion to the extraction electrode portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4117303A JPH05315626A (en) | 1992-05-11 | 1992-05-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4117303A JPH05315626A (en) | 1992-05-11 | 1992-05-11 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05315626A true JPH05315626A (en) | 1993-11-26 |
Family
ID=14708417
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4117303A Pending JPH05315626A (en) | 1992-05-11 | 1992-05-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05315626A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0690515A1 (en) * | 1994-06-30 | 1996-01-03 | Eastman Kodak Company | Optoelectronic assembly and methods for producing and using the same |
| CN100449721C (en) * | 2005-08-30 | 2009-01-07 | 南茂科技股份有限公司 | Structure and method for packaging image sensor |
-
1992
- 1992-05-11 JP JP4117303A patent/JPH05315626A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0690515A1 (en) * | 1994-06-30 | 1996-01-03 | Eastman Kodak Company | Optoelectronic assembly and methods for producing and using the same |
| CN100449721C (en) * | 2005-08-30 | 2009-01-07 | 南茂科技股份有限公司 | Structure and method for packaging image sensor |
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