JPS60254674A - Semiconductor photo receptor - Google Patents
Semiconductor photo receptorInfo
- Publication number
- JPS60254674A JPS60254674A JP59109432A JP10943284A JPS60254674A JP S60254674 A JPS60254674 A JP S60254674A JP 59109432 A JP59109432 A JP 59109432A JP 10943284 A JP10943284 A JP 10943284A JP S60254674 A JPS60254674 A JP S60254674A
- Authority
- JP
- Japan
- Prior art keywords
- guard ring
- junction
- semiconductor layer
- avalanche
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 108091008695 photoreceptors Proteins 0.000 title 1
- 230000007423 decrease Effects 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 abstract description 12
- 230000005684 electric field Effects 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 230000031700 light absorption Effects 0.000 description 5
- 239000000758 substrate Substances 0.000 description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- LZZYPRNAOMGNLH-UHFFFAOYSA-M Cetrimonium bromide Chemical compound [Br-].CCCCCCCCCCCCCCCC[N+](C)(C)C LZZYPRNAOMGNLH-UHFFFAOYSA-M 0.000 description 1
- 101100130497 Drosophila melanogaster Mical gene Proteins 0.000 description 1
- 101100345589 Mus musculus Mical1 gene Proteins 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、例えば光通信などに用いられ、アバランシェ
・フォト・ダイオード（ａｖａｌａｎｃｈｅ ｐｈｏｔ
ｏ ｄｉｏｄｅ：ＡＰＤ）と呼ばれている半導体受光装
置の改良に関する。[Detailed Description of the Invention] [Industrial Field of Application] The present invention is used, for example, in optical communications, and is applied to avalanche photo diodes.
This invention relates to an improvement of a semiconductor light receiving device called an APD.
−Ｓに、光通信などで１ 〔μｍ〕波長帯の光を検出す
るのに、ＩｎＧａＡｓ （Ｐ）系ＡＰＤを用いている。-S, an InGaAs (P) based APD is used to detect light in the 1 [μm] wavelength band in optical communications and the like.
このＡＰＤでは、低暗電流化及び低増倍雑音化の為、Ｉ
ｎＧａＡｓ （Ｐ）光吸収層とＩｎＰなだれ増倍層から
なる吸収層・増倍層分離型構造となし、また、信頼性を
向上させる為、ブレーナ構造にしてあり、更にまた、前
記プレーナ構造を採っていることから、所望の部分での
み確実になだれ増倍を発生させる為のガード・リングを
形成する必要がある。In this APD, I
It has a separated absorption layer and multiplication layer structure consisting of an nGaAs (P) light absorption layer and an InP avalanche multiplication layer, and also has a planar structure to improve reliability. Therefore, it is necessary to form a guard ring to ensure that avalanche multiplication occurs only in desired areas.
ところで、現在のＡＰＤに於いて、その特性を左右する
重要事項は、前記ガード・リングの形成である。By the way, in the current APD, an important matter that influences its characteristics is the formation of the guard ring.
従来、このガード・リングを形成するに際して考慮され
ている原理は次のようである。Conventionally, the following principles have been considered when forming this guard ring.
（ｌｌｐｎ接合のなだれ増倍部とガード・リング部とを
禁制帯幅を異にする半導体中に形成し、降伏電界強度の
禁制帯幅に依る差を利用してガード・リング部の耐圧を
大にする。(The avalanche multiplier part and the guard ring part of the llpn junction are formed in semiconductors with different forbidden band widths, and the breakdown voltage of the guard ring part is increased by using the difference in breakdown electric field strength depending on the forbidden band width. Make it.
（２）ｐｎ接合の中央部と周辺部をキャリヤ濃度を異に
する同一半導体中に形成し、キャリヤ濃度の差による降
伏電圧の差異を利用して周辺部分に於ける耐圧を大にす
る。(2) The central part and peripheral part of the pn junction are formed in the same semiconductor having different carrier concentrations, and the breakdown voltage in the peripheral part is increased by utilizing the difference in breakdown voltage due to the difference in carrier concentration.
第７図は前記原理に従って製造されたＡＰＤの要部切断
側面図である。FIG. 7 is a cutaway side view of essential parts of an APD manufactured according to the above principle.
図に於いて、１はＩｎＰ基板、２はｎ型Ｉ ｎＧａＡｓ
光吸収層、３はｎ型１ｎＰなだれ増倍層、４はｎ−型Ｉ
ｎＰガード・リング用半導体層、５はｐ型費光領域、Ａ
Ｂはなだれ増倍部、ＧＲはガード・リング部をそれぞれ
示している。In the figure, 1 is InP substrate, 2 is n-type InGaAs
Light absorption layer, 3 is n-type 1nP avalanche multiplication layer, 4 is n-type I
nP guard ring semiconductor layer, 5 is p-type light-emitting region, A
B indicates an avalanche multiplier, and GR indicates a guard ring.
このＡＰＤで、なだれ増倍層３とガード・リング用半導
体層４とは、図示のように、なだれ増倍層３のキャリヤ
濃度を高く、そして、ガード・リング用半導体層４のそ
れを低くするか、或いは、なだれ増倍層３を構成する半
導体の禁制帯幅を狭く、そして、ガード・リング用半導
体層４のそれを広くするかの何れかである。In this APD, the avalanche multiplication layer 3 and the guard ring semiconductor layer 4 have a high carrier concentration in the avalanche multiplier layer 3 and a low carrier concentration in the guard ring semiconductor layer 4, as shown in the figure. Alternatively, the forbidden band width of the semiconductor constituting the avalanche multiplication layer 3 is narrowed, and that of the guard ring semiconductor layer 4 is widened.
前記の原理を適用して製造された第７図に見られる半導
体受光装置に於けるガード・リング構造は有効であるか
の如くに思われるが、実際には、なだれ増倍部ＡＢ及び
ガード・リング部ＧＲを構成している、禁制帯幅を異に
する或いはキャリヤ濃度を異にする、各半導体の界面に
於けるｐｎ接合の連接形状について何等の考慮も払って
いない為、これが大きな欠点になっている。The guard ring structure in the semiconductor light receiving device shown in FIG. 7 manufactured by applying the above principle seems to be effective, but in reality, the avalanche multiplier AB and the guard ring structure are This is a major drawback because no consideration is given to the connected shape of the pn junction at the interface of each semiconductor, which makes up the ring part GR and has different forbidden band widths or carrier concentrations. It has become.
即ち、ｐｎ接合を得る為のｐ型受光領域５の形成は、不
純物拡散法、イオン注入法、エピタキシャル成長法の何
れを採用しても高温の熱処理工程を必要とすることは明
らかであり、この為、導入された不純物は該熱処理で拡
散されることにな、るが、その場合の不純物拡散の速さ
は、同じ格子定数を有する半導体であれば禁制帯幅が大
である半導体に於ける方が速く、且つ、この拡散に依り
形成される実際のｐｎ接合の位置は同一の半導体中であ
ってもキャリヤ濃度が低いものの方が深くなる。That is, it is clear that the formation of the p-type light-receiving region 5 to obtain a p-n junction requires a high-temperature heat treatment process, regardless of whether the impurity diffusion method, ion implantation method, or epitaxial growth method is adopted. , the introduced impurity will be diffused by the heat treatment, but the speed of impurity diffusion in that case will be faster than that of a semiconductor with a larger forbidden band if the semiconductor has the same lattice constant. is faster, and the actual position of the pn junction formed by this diffusion is deeper in a semiconductor with a lower carrier concentration even in the same semiconductor.
従って、第７図に見られるように、なだれ増倍部ＡＢと
ガード・リング部ＧＲとの界面に於けるｐｎ接合の連接
形状は階段状になってしまう。Therefore, as shown in FIG. 7, the pn junction at the interface between the avalanche multiplier AB and the guard ring GR has a stepped shape.
このような半導体受光装置を動作させた場合、前記階段
状の部分に局所的な電界集中を生じ、その結果、そこで
ブレイク・ダウンを起こすことになる。When such a semiconductor light-receiving device is operated, local electric field concentration occurs in the step-like portion, and as a result, breakdown occurs there.
換言すると、ｐｎ接合の中央部と周辺部では耐圧差が得
られるが、中央部と周辺部の間で局所降伏を生ずるもの
であり、従って、前記ガード・リングは確実な効果を奏
するとは言い難い。In other words, a breakdown voltage difference can be obtained between the center and the periphery of the pn junction, but local breakdown occurs between the center and the periphery. Therefore, it cannot be said that the guard ring has a reliable effect. hard.
本発明は、なだれ増倍部ＡＢとガード・リング部ＧＲと
の界面に於ける構造に簡単な改良を施すことに依り、確
実なガード・リング効果が得られるようにする。The present invention makes it possible to obtain a reliable guard ring effect by simply improving the structure at the interface between the avalanche multiplier AB and the guard ring GR.
本発明の半導体受光装置では、なだれ増倍部を構成する
高濃度或いは狭禁制帯幅である半導体層とガード・リン
グ部を構成する低濃度或いは広禁制帯幅である半導体層
との界面がｐ、ｎ接合面に対して前記ガード・リング部
方向に向かって低下する緩斜面をなし、且つ、前記なだ
れ増倍部に於けるｐｎ接合と前記ガード・リング部に於
けるｐｎ接合とが前記緩斜面に沿って連接された構造に
なっている。In the semiconductor light-receiving device of the present invention, the interface between the high concentration or narrow bandgap semiconductor layer constituting the avalanche multiplier section and the low concentration or wide bandgap semiconductor layer constituting the guard ring section is p. , the n-junction surface has a gentle slope that decreases toward the guard ring part, and the pn junction in the avalanche multiplier part and the pn junction in the guard ring part have a gentle slope that descends toward the guard ring part; The structure is connected along the slope.
第６図は前記〔問題点を解決するための手段〕に記述さ
れた構造を有する半導体受光装置の原理を説明する為の
要部切断側面図であり、第７図に関して説明した部分と
同部分は同記号で指示しである。FIG. 6 is a cutaway side view of a main part for explaining the principle of a semiconductor light receiving device having the structure described in [Means for solving the problem] above, and is the same part as that explained in connection with FIG. 7. is indicated by the same symbol.
図から明らかなように、なだれ増倍部を構成する半導体
層である増倍層３とガード・リング部を構成する半導体
層であるガード・リング用半導体層４との界面ＪＳはｐ
ｎ接合面に対して、ガード・リング部方向に向かって低
下する緩斜面をなしている。As is clear from the figure, the interface JS between the multiplication layer 3, which is a semiconductor layer forming the avalanche multiplication part, and the guard ring semiconductor layer 4, which is a semiconductor layer forming the guard ring part, is p
With respect to the n-junction surface, it forms a gentle slope that descends toward the guard ring part.
このように、緩斜面をなす界面ＪＳに存在するｐｎ接合
には、局所的な電界集中は発生せず、従って、局所降伏
も生じない。尚、緩斜面は、なだらかである方が効果的
であることは勿論である。In this way, no local electric field concentration occurs in the pn junction existing at the interface JS forming a gentle slope, and therefore no local breakdown occurs. Of course, it is more effective if the slope is gentle.
第１図は本発明一実施例を表す要部切断側面図であり、
第６図及び第７図に関して説明した部分と同部分は同記
号で指示しである。FIG. 1 is a cutaway side view of essential parts showing one embodiment of the present invention.
The same parts as those described with reference to FIGS. 6 and 7 are indicated by the same symbols.
図に於いて、６はｎ側電極、７はｎ側電極をそれぞれ示
している。In the figure, 6 indicates an n-side electrode, and 7 indicates an n-side electrode.
この実施例に於いても、なだれ増倍部ＡＢを構成するな
だれ増倍層３とガード・リング部ＧＲを構成するガード
・リング用半導体層４との界面ＪＳは緩斜面をなしてい
る。尚、この実施例では、なだれ増倍層３にはｎ型Ｉｎ
Ｐを、また、ガード・リング用半導体層４にはｎ−型１
ｎＰをそれぞれ用い、キャリヤ濃度の相違を利用する形
式を採っているが、これば、例えば′、なだれ増倍層３
としてｎ型ＩｎＰを、ガード・リング用半導体層４にｎ
型Ａｌ１１ｎＡｓを用い、禁制帯幅の狭広を利用する形
式を採っても同効である。In this embodiment as well, the interface JS between the avalanche multiplier layer 3 forming the avalanche multiplier section AB and the guard ring semiconductor layer 4 forming the guard ring section GR forms a gentle slope. In this embodiment, the avalanche multiplication layer 3 is made of n-type In.
P, and n-type 1 in the guard ring semiconductor layer 4.
nP is used, and the difference in carrier concentration is utilized.
n-type InP as the semiconductor layer 4 for guard ring.
The same effect can be obtained by using Al11nAs type and utilizing a narrow and wide forbidden band.
ところで、本発明に於いては、なだれ増倍層３に緩斜面
を形成することが重要となるが、次に、第１図に示した
半導体受光装置を製造する場合について説明する。By the way, in the present invention, it is important to form a gentle slope in the avalanche multiplication layer 3. Next, a case will be described in which the semiconductor light receiving device shown in FIG. 1 is manufactured.
第２図乃至第５図は第１図に示した実施例を製造する場
合を解説する為の工程要所に於ける半導体受光装置の要
部切断側面図であり、以下、これ等の図を参照しつつ説
明する。2 to 5 are cross-sectional side views of the main parts of the semiconductor light receiving device at key points in the process to explain the manufacturing of the embodiment shown in FIG. 1. I will explain while referring to it.
第２図参照
ｆａｌ 液相エピタキシャル（Ｉ １ｑｕｉｄ ｐｈａ
ｓｅ ｅｐｉｔａｘｙ：ＬＰＥ）法を適用することに依
り、ＩｎＰ基板１上にｎ型１ｎＧａＡｓ（或いはＩｎＧ
ａＡ−ｓＰ）光吸収層２、ｎ型ＩｎＰなだれ増倍層３を
成長させる。See Figure 2 fal Liquid phase epitaxial (I 1quid pha
By applying the se epitaxy (LPE) method, n-type 1nGaAs (or InG
aA-sP) Grow the light absorption layer 2 and the n-type InP avalanche multiplication layer 3.
このときの各部のデータは次の通りである。The data of each part at this time is as follows.
ｆｉｌ Ｉ ｎ Ｐ基板１について
キャリヤ濃度： ２ Ｘ １０Ｉ８（ｃｍ−３）面指数
：（１１１）Ａ
（２）ｎ型１ｎＧａＡｓ （Ｐ）光吸収層２についてキ
ャリヤ濃度：１×１０１６〔ｃｍ−３〕厚さ：１．５Ｃ
μｍ〕
（３）ｎ型ＩｎＰなだれ増倍層３についてキャリヤ濃度
： １ 、 ５ Ｘ １０１６ ［Ｃｍ−’）厚さ：３
〔μｍ〕
尚、ＩｎＧａＡｓ （Ｐ）及びＩｎＰは（１１１）Ａ面
を有するＩｎＰ基板１と格子定数が整合するような条件
で成長させる。Carrier concentration for fil I n P substrate 1: 2 x 10I8 (cm-3) Plane index: (111)A (2) n-type 1nGaAs (P) Carrier concentration for light absorption layer 2: 1 x 1016 [cm-3] Thickness: 1.5C
μm] (3) Regarding n-type InP avalanche multiplication layer 3, carrier concentration: 1, 5 x 1016 [Cm-') Thickness: 3
[μm] Note that InGaAs (P) and InP are grown under conditions such that their lattice constants match those of the InP substrate 1 having the (111)A plane.
第３図参照
Ｔｂｌ スパンクリング法、化学気相堆積（ｃ ｈ ｅ
ｍｉｃａｌ ｖａｐｏｕｒ ｄｅｐｏｓｉｔｉ。See Figure 3 Tbl Spankling method, chemical vapor deposition (c h e
mical vapor deposit.
ｎ ： ＣＶＤ）法、プラズマ励起ＣＶＤ法などを適宜
選択して適用することに依り、二酸化シリ’：１７ （
Ｓ ｉ ０２） 或いは窒化シリコン（Ｓ ｉ ３Ｎ４
）などからなる保護膜８を６００ Ｃ人）以上２０００
（人）以下の範囲で適宜選択された厚さに形成する。By appropriately selecting and applying the CVD method, plasma-enhanced CVD method, etc., silicon dioxide':17 (
S i 02) or silicon nitride (S i 3N4
) etc. 600 C people) or more 2000
(Person) Form to a thickness appropriately selected within the following range.
（Ｃ） 通常のフォト・リソグラフィ技術を適用するこ
とに依り、保護膜８を直径が例えば約１００〔μｍ〕で
ある円形にパターニングする。(C) By applying a normal photolithography technique, the protective film 8 is patterned into a circular shape having a diameter of, for example, about 100 [μm].
第４図参照
（ｄ） メルト・バック法を適用することに依り、ｎ型
ＩｎＰなだれ増倍層３を選択的に除去する。See FIG. 4(d) The n-type InP avalanche multiplier layer 3 is selectively removed by applying the melt-back method.
この場合、メルトとして未飽和度が２〔℃〕であるＩｎ
−Ｐを用い、メルト・バンクする深、さは２〔μｍ〕程
度とする。In this case, In with a degree of unsaturation of 2 [°C] as a melt,
-P is used, and the depth and height of the melt bank is approximately 2 [μm].
（ｅｌ メルト・ハックで形成された欠如部分にｎ−型
ＩｎＰガード・リング用半導体層４を成長させる。(el) An n-type InP guard ring semiconductor layer 4 is grown in the missing portion formed by melt hacking.
このようにして得られたなだれ増倍層３とガード・リン
グ用半導体層４との界面ＪＳはなだらかな緩斜面をなし
ている。The thus obtained interface JS between the avalanche multiplication layer 3 and the guard ring semiconductor layer 4 forms a gentle slope.
第５図参照
（ｒｌ ＨＮＯ３＋ＨＦ （重量比で１：１）溶液を用
いて保護膜８を除去する。Refer to FIG. 5 (rl) The protective film 8 is removed using a solution of HNO3+HF (1:1 by weight).
（ｇ＋ 適当なマスクを形成した後、表面からカドミウ
ム（Ｃｄ）を熱拡散してｐ型光光領域５を形成してｐｎ
接合を生成させる。(g+ After forming a suitable mask, cadmium (Cd) is thermally diffused from the surface to form a p-type optical region 5 and a pn
Generate a bond.
このＣｄ拡散では、ソースとしてｃｄＰ２を用い、閉管
法を適用することに依り実施し、拡散温度は５００［”
Ｃ）乃至５５０（’Ｃ）程度であり、拡散深さはｎ型Ｉ
ｎＰなだれ増倍層３中で１．５〔μｍ〕、また、ｎ−型
１ｎＰガード・リング用半導体層４中で１．８ｃμｍ〕
となるようにした。This Cd diffusion was carried out by using cdP2 as a source and applying a closed tube method, and the diffusion temperature was 500 [”
C) to 550 ('C), and the diffusion depth is n-type I.
1.5 [μm] in the nP avalanche multiplication layer 3, and 1.8 cμm in the n-type 1nP guard ring semiconductor layer 4]
I made it so that
拡散が完全に終了した後に於けるｐｎ接合の深さは、な
だれ増倍層３に存在するｐｎ接合とガード・リング用半
導体層４に存在するｐｎ接合とがｎ型ＩｎＰ／ｎ−型Ｉ
ｎＰ界面の緩斜面で連接されるように選択する。The depth of the pn junction after the complete diffusion is such that the pn junction existing in the avalanche multiplication layer 3 and the pn junction existing in the guard ring semiconductor layer 4 are n-type InP/n-type I
They are selected so that they are connected by the gentle slope of the nP interface.
第１図参照
（ｈｌ 通常の技法を適用することに依り、ｐ側に例え
ばＡｕ−Ｚｎからなるオーミックの電極６を、ｎ側に例
えばＡｕ−Ｇｅからなるオーミックの電極７をそれぞれ
形成する。See FIG. 1 (hl) By applying a conventional technique, an ohmic electrode 6 made of, for example, Au--Zn is formed on the p-side, and an ohmic electrode 7 made of, for example, Au--Ge, is formed on the n-side.
前記のようにして製造した半導体受光装置は、均一な面
内感度を有し、ブレイク・ダウン電圧が８０〔■〕、最
大増倍率が３０（増倍がない場合の光電流を１．０〔μ
Ａ））であった。The semiconductor photodetector manufactured as described above has uniform in-plane sensitivity, a breakdown voltage of 80 [■], and a maximum multiplication factor of 30 (with no multiplication, the photocurrent is 1.0 [■]). μ
A)).
本発明の半導体受光装置では、なだれ増倍部を構成する
高濃度或いは狭禁制帯幅である半導体層とガード・リン
グ部を構成する低濃度或いは広禁制帯幅である半導体層
との界面がｐｎ接合面に対−シて前記ガード・リング部
方向に向かって低下する緩斜面をなし、且つ、前記なだ
れ増倍部に於けるｐｎ接合と前記ガード・リング部に於
けるｐｎ接合とが前記緩斜面に沿って連接された構造を
採っている。In the semiconductor light receiving device of the present invention, the interface between the semiconductor layer with a high concentration or a narrow bandgap forming the avalanche multiplier section and the semiconductor layer with a low concentration or a wide bandgap forming the guard ring section is a pn layer. The bonding surface has a gentle slope that decreases toward the guard ring part, and the pn junction in the avalanche multiplier part and the pn junction in the guard ring part The structure is connected along the slope.
このような構造を採っていることから、なだれ増倍部に
於けるｐ ｎ’接合とガード・リング部に於けるｐｎ接
合とが連接される部分に電界集中を生ずることはなくな
り、従って、その部分が局所降伏することもなくなるか
ら、本来のなだれ増倍部で充分ななだれ増倍を発生させ
ることができ、その増倍率を向上することが可能である
。Since this structure is adopted, electric field concentration will not occur in the part where the pn' junction in the avalanche multiplier and the pn junction in the guard ring part are connected, and therefore the Since there is no local yielding of the portion, sufficient avalanche multiplication can be generated in the original avalanche multiplier, and the multiplication factor can be improved.
第１図は本発明一実施例の要部切断側面図、第２図乃至
第５図は第１図に示した実施例を製造する場合を説明す
る為の工程要所に於ける半導体受光装置の要部切断側面
図、第６図は本発明の詳細な説明する為の半導体受光装
置の要部切断側面図、第７図は従来例の要部切断側面図
をそれぞれ表している。
図に於いて、１はＩｎＰ基板、２はｎ型１ ｎＧａＡｓ
光吸収層、３はｎ型１ｎＰなだれ増倍層、４はｎ−型Ｉ
ｎＰガード・リング用半導体層、５はｐ型費光領域、６
はｐ側電極、７はｎ側電極、ＡＢはなだれ増倍部、ＧＲ
はガード・リング部、ＪＳは界面をそれぞれ示している
。
特許出願人 富士通株式会社
代理人弁理士 相 谷 昭 司
代理人弁理士 渡 邊 弘 −
第１図
！２＠
第３図
第４図
第５図
第６図FIG. 1 is a cutaway side view of essential parts of an embodiment of the present invention, and FIGS. 2 to 5 show a semiconductor light receiving device at key points in the process for explaining the manufacturing of the embodiment shown in FIG. 1. 6 is a cross-sectional side view of a main part of a semiconductor light receiving device for explaining the present invention in detail, and FIG. 7 is a cross-sectional side view of a main part of a conventional example. In the figure, 1 is an InP substrate, 2 is an n-type 1 nGaAs
Light absorption layer, 3 is n-type 1nP avalanche multiplication layer, 4 is n-type I
nP guard ring semiconductor layer, 5 is p-type light-emitting region, 6
is the p-side electrode, 7 is the n-side electrode, AB is the avalanche multiplier, GR
indicates the guard ring portion, and JS indicates the interface. Patent Applicant Fujitsu Ltd. Representative Patent Attorney Shoji Aitani Representative Patent Attorney Hiroshi Watanabe - Figure 1! 2 @ Figure 3 Figure 4 Figure 5 Figure 6
Claims (1)
半導体層とガード・リング部を構成する低濃度或いは広
禁制帯幅である半導体層との界面がｐｎ接合面に対して
前記ガード・リング部方向に向かって低下する緩斜面を
なし、且つ、前記なだれ増倍部に於けるｐｎ接合と前記
ガード・リング部に於けるｐｎ接合とが前記緩斜面に沿
って連接された構造を有してなることを特徴とする半導
体受光装置。The interface between the high concentration or narrow bandgap semiconductor layer constituting the avalanche multiplier section and the low concentration or wide bandgap semiconductor layer constituting the guard ring section is in contact with the pn junction surface. The structure has a gentle slope that decreases toward the ring part, and a pn junction in the avalanche multiplier part and a pn junction in the guard ring part are connected along the gentle slope. A semiconductor light receiving device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59109432A JP2657480B2 (en) | 1984-05-31 | 1984-05-31 | Semiconductor light receiving device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59109432A JP2657480B2 (en) | 1984-05-31 | 1984-05-31 | Semiconductor light receiving device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60254674A true JPS60254674A (en) | 1985-12-16 |
| JP2657480B2 JP2657480B2 (en) | 1997-09-24 |
Family
ID=14510095
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59109432A Expired - Lifetime JP2657480B2 (en) | 1984-05-31 | 1984-05-31 | Semiconductor light receiving device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2657480B2 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5683082A (en) * | 1979-12-10 | 1981-07-07 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor light receiver |
| JPS575376A (en) * | 1980-06-13 | 1982-01-12 | Fujitsu Ltd | Semiconductor photoreceiving element |
| JPS5718373A (en) * | 1980-07-08 | 1982-01-30 | Fujitsu Ltd | Semiconductor photoreceiving element |
| JPS5783069A (en) * | 1980-11-11 | 1982-05-24 | Fujitsu Ltd | Manufacture of photoreceiving device |
-
1984
- 1984-05-31 JP JP59109432A patent/JP2657480B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5683082A (en) * | 1979-12-10 | 1981-07-07 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor light receiver |
| JPS575376A (en) * | 1980-06-13 | 1982-01-12 | Fujitsu Ltd | Semiconductor photoreceiving element |
| JPS5718373A (en) * | 1980-07-08 | 1982-01-30 | Fujitsu Ltd | Semiconductor photoreceiving element |
| JPS5783069A (en) * | 1980-11-11 | 1982-05-24 | Fujitsu Ltd | Manufacture of photoreceiving device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2657480B2 (en) | 1997-09-24 |
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