JPS627176A - Semiconductor photodetector - Google Patents
Semiconductor photodetectorInfo
- Publication number
- JPS627176A JPS627176A JP60146375A JP14637585A JPS627176A JP S627176 A JPS627176 A JP S627176A JP 60146375 A JP60146375 A JP 60146375A JP 14637585 A JP14637585 A JP 14637585A JP S627176 A JPS627176 A JP S627176A
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- JP
- Japan
- Prior art keywords
- layer
- type
- semiconductor
- region
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 17
- 230000015556 catabolic process Effects 0.000 abstract description 13
- 230000031700 light absorption Effects 0.000 abstract description 7
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 abstract description 3
- 239000007791 liquid phase Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 2
- 230000002708 enhancing effect Effects 0.000 abstract 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 18
- 239000012535 impurity Substances 0.000 description 9
- 238000000098 azimuthal photoelectron diffraction Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 229910052790 beryllium Inorganic materials 0.000 description 2
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 description 2
- 229910052793 cadmium Inorganic materials 0.000 description 2
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes
- H01L31/1075—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes in which the active layers, e.g. absorption or multiplication layers, form an heterostructure, e.g. SAM structure
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
この発明は、埋め込み成長したガードリング層を有する
アバランシホトダイオードにおいて、その半導体基体の
上面を平坦にする透明な半導体層を設けることにより、
受光領域外のブレークダウンの防止等の性能改善を行う
ものである。[Detailed Description of the Invention] [Summary] The present invention provides an avalanche photodiode having a guard ring layer grown in a buried manner, by providing a transparent semiconductor layer that flattens the upper surface of the semiconductor substrate, thereby achieving a break outside the light-receiving area. This is to improve performance such as preventing downtime.
本発明は半導体受光装置、特になだれ増倍層より低不純
物濃度の半導体層にガードリングが形成される化合物半
導体アバランシホトダイオードの改善に関する。The present invention relates to an improvement in a semiconductor light receiving device, particularly a compound semiconductor avalanche photodiode in which a guard ring is formed in a semiconductor layer having a lower impurity concentration than an avalanche multiplication layer.
光を情報信号の媒体とする光通信等において、光電流が
なだれ降伏によって増倍されるアバランシホトダイオー
ド(以下APDと略称する)は、光検知器の信号対雑音
比を改善する効果が大きい。In optical communications where light is used as an information signal medium, avalanche photodiodes (hereinafter abbreviated as APDs), whose photocurrent is multiplied by avalanche breakdown, are highly effective in improving the signal-to-noise ratio of photodetectors.
特に石英系ファイバによる光通信システムには、インジ
ウム燐/インジウムガリウム砒素(燐)(InP/ I
nGaAs (P) )系等の化合物半導体APDが重
要であリ、このAPDでは受光部外の降伏を防止するた
めのガードリングを、なだれ降伏層より低不純物濃度の
埋め込み成長した半導体層に形成することが多い。しか
しながら従来のこの構造のAPDでは、往々にして目的
とするガードリング効果が得られないことがあり、その
改善が必要とされている。In particular, for optical communication systems using silica-based fibers, indium phosphorus/indium gallium arsenide (phosphorus) (InP/I
Compound semiconductor APDs such as nGaAs(P)) systems are important, and in this APD, a guard ring to prevent breakdown outside the light-receiving area is formed in a buried semiconductor layer with a lower impurity concentration than the avalanche breakdown layer. There are many things. However, with conventional APDs having this structure, the desired guard ring effect is often not achieved, and improvements are needed.
埋め込み構造のInP / I nGaAs (P)系
APDの半導体基体は例えば第2図の模式側断面図に示
す如き構造を有する。A semiconductor substrate of an InP/InGaAs (P) type APD having a buried structure has a structure as shown in a schematic side sectional view of FIG. 2, for example.
同図において、1は1型InP基板、2はn型InPバ
フファ層、3はn型TnGaAs光吸収層、5はn型I
nPなだれ増倍層、6は1型InP層、8はp型受光領
域、9はp型ガードリ′ング領域、10はp側電極、1
1はn側電極である。In the figure, 1 is a type 1 InP substrate, 2 is an n-type InP buffer layer, 3 is an n-type TnGaAs light absorption layer, and 5 is an n-type I
nP avalanche multiplication layer, 6 a 1-type InP layer, 8 a p-type light receiving region, 9 a p-type guard ring region, 10 a p-side electrode, 1
1 is an n-side electrode.
このAPDにイ型1nP基板1を正、p型費光領域8を
負の極性とする高い逆バイアス電圧を印加して、InG
aAs光吸収N3内で入力信号光によって励起された正
孔を一次キャリアとするなだれ降伏を、禁制帯幅がIn
GaAs光吸収層3より大きいInPなだれ増倍層5で
発生させる。A high reverse bias voltage is applied to this APD, with the A-type 1nP substrate 1 having positive polarity and the P-type light dissipating region 8 having negative polarity.
The avalanche breakdown in which the holes excited by the input signal light are used as primary carriers in the aAs optical absorption N3 is expressed by the forbidden band width In
This is caused by the InP avalanche multiplier layer 5 which is larger than the GaAs light absorption layer 3.
このなだれ降伏より低い電圧で、p型費光領域8の周辺
に降伏が発生することを防止するために、なだれ増倍層
5より低不純物濃度のn−型1nP層6を設けて、p型
ガードリング領域9が通常円形であるp型費光領域8の
外周に接して形成されている。In order to prevent breakdown from occurring around the p-type light-emitting region 8 at a voltage lower than this avalanche breakdown, an n-type 1nP layer 6 with a lower impurity concentration than the avalanche multiplication layer 5 is provided, and the p-type A guard ring region 9 is formed in contact with the outer periphery of the p-type dissipating region 8, which is generally circular.
この従来例は例えぼ下記の様に製造される。This conventional example is manufactured, for example, as follows.
すなわち通常液相エピタキシャル成長方法により、1型
1nP基板l上にn型InPバッファ層2、n型1nG
aAs光吸収層3及びn型1nPなだれ増倍層5を成長
し、このN5上に例えば厚さ0.1乃至0゜2μ程度の
マスクを設けて、メルトバック等によりn型InPなだ
れ増倍層5を例えば深さ2乃至3−程度に選択的に除去
し、ここにf型InP層6を埋め込み成長して半導体基
体を形成している。That is, by a normal liquid phase epitaxial growth method, an n-type InP buffer layer 2, an n-type 1nG
An aAs light absorption layer 3 and an n-type 1nP avalanche multiplier layer 5 are grown, a mask with a thickness of, for example, about 0.1 to 0.2μ is provided on the N5, and the n-type InP avalanche multiplier layer is formed by meltback or the like. 5 is selectively removed to a depth of about 2 to 3 mm, for example, and an f-type InP layer 6 is buried and grown there to form a semiconductor substrate.
この半導体基体に、例えばカドミウム(Cd、)を深さ
1乃至2p程度に拡散して、p型費光領域8をn型In
Pなだれ増倍層5からn−型InP層6にわたって形成
し、例えばベリリウム(Be)をn−型InP層6にイ
オン注入し活性化熱処理を施して、pn接合がなだらか
なp型ガードリング領域9を形成する。For example, cadmium (Cd) is diffused into this semiconductor substrate to a depth of about 1 to 2p, and the p-type light-emitting region 8 is replaced with n-type In.
A p-type guard ring region is formed extending from the P avalanche multiplication layer 5 to the n-type InP layer 6, and by implanting, for example, ions of beryllium (Be) into the n-type InP layer 6 and performing activation heat treatment, a p-type guard ring region with a gentle p-n junction is formed. form 9.
上述の製造方法において、n型InPなだれ増倍層5の
選択的除去とn−型1nP層6の埋め込み成長とはマス
クを共用して実施されるが、埋め込み成長の際に半導体
基体の段差部分の成長速度が平坦部分よりも大きいこと
などの理由により、図に示す如く、埋め込み成・長した
n−型InP層6にマスクの端で制限された段差6^を
生ずる。In the above manufacturing method, the selective removal of the n-type InP avalanche multiplication layer 5 and the buried growth of the n-type 1nP layer 6 are carried out using a common mask. For reasons such as the fact that the growth rate of the mask is higher than that of the flat portion, a step 6^ is formed in the buried n-type InP layer 6, which is limited at the edge of the mask, as shown in the figure.
n−型InP層6に生じたこの段差は前記のCd拡散に
よるp型費光領域8に反映してそのpn接合面に湾曲部
8Aが形成され、pn接合に高い逆バイアス電圧を印加
した際にここに電界集中を生ずる。この結果、湾曲部8
Aはなだれ増倍N5より低不純物濃度のn−型1nP層
6内に形成されてはいるが、なだれ降伏より低電圧で降
伏する場合がある。This step generated in the n-type InP layer 6 is reflected in the p-type light-emitting region 8 due to the above-mentioned Cd diffusion, and a curved portion 8A is formed on the p-n junction surface, and when a high reverse bias voltage is applied to the p-n junction, This causes electric field concentration here. As a result, the curved portion 8
Although A is formed in the n-type 1nP layer 6 with a lower impurity concentration than the avalanche multiplication N5, it may break down at a lower voltage than the avalanche breakdown.
また半導体基体上面のこの段差6Aにより、蒸着等によ
る電極材料の密着性が低下することがある。Further, the level difference 6A on the upper surface of the semiconductor substrate may reduce the adhesion of the electrode material by vapor deposition or the like.
以上説明した如く埋め込み構造のAPDでは、埋め込み
成゛長層によって生ずる段差が降伏などの弱点となって
おり、これに対処することが要望されている。As explained above, in an APD having a buried structure, the step caused by the buried growth layer becomes a weak point such as breakdown, and it is desired to deal with this.
前記問題点は、例えば第1図に示す実施例の如く、
光電変換を行う第1の半導体層3上に、該第1の半導体
N3より禁制帯幅が大きい第1導電型の第2の半導体層
5と、
該第1の半導体層3より禁制帯幅が大きく、該第2の半
導体層を選択的に除去して埋め込み成長された第1導電
型の第3の半導体N6と、該第1の半導体層3より禁制
帯幅が大きく、該第2及び第3の半導体層5.6上を覆
って上面が平坦に形成された第4の半導体層7とを備え
て、該第2及び第3の半導体M5.6においてpn接合
を形成する第2導電型の領域8が形成されてなる本発明
による半導体受光装置により解決される。The problem is that, as in the embodiment shown in FIG. 1, for example, a second semiconductor of the first conductivity type, which has a larger forbidden band width than the first semiconductor N3, is placed on the first semiconductor layer 3 that performs photoelectric conversion. layer 5; a third semiconductor N6 of the first conductivity type, which has a larger forbidden band width than the first semiconductor layer 3 and is grown in a buried manner by selectively removing the second semiconductor layer; a fourth semiconductor layer 7 having a larger forbidden band width than the semiconductor layer 3 and having a flat top surface covering the second and third semiconductor layers 5.6; This problem is solved by the semiconductor light receiving device according to the present invention, in which a region 8 of the second conductivity type forming a pn junction is formed in the semiconductor M5.6 of No. 3.
本発明による半導体゛受光装置は、受光領域及びガード
リング領域上に光吸収層より禁制帯幅が大きい、すなわ
ち目的とする光に対して透明な半導体層が設けられて、
半導体基体の上面が平坦とされている。In the semiconductor light receiving device according to the present invention, a semiconductor layer having a larger forbidden band width than the light absorption layer, that is, transparent to the target light, is provided on the light receiving region and the guard ring region,
The top surface of the semiconductor substrate is flat.
従ってpn接合は埋め込み成長による段差部分の下部で
も平坦で、前記従来例の如き電界集中、降伏電圧の低下
を生ぜず、ガードリング効果が確保される。Therefore, the pn junction is flat even under the stepped portion caused by buried growth, and the guard ring effect is ensured without causing electric field concentration or reduction in breakdown voltage as in the conventional example.
また電極の密着性も損なわれず、高い信頼性が得られる
。Moreover, the adhesion of the electrodes is not impaired, and high reliability can be obtained.
以下本発明を、第1図に模式側断面図を示す実施例によ
り、具体的に説明する。The present invention will be specifically explained below with reference to an embodiment whose schematic side sectional view is shown in FIG.
本実施例の半導体基体は例えば下記の様に製造される。The semiconductor substrate of this example is manufactured, for example, as follows.
ヤ型InP基板1の(111)A面上に液相エピタキシ
ャル成長方法により、例えばn型1nPバッフプ層2、
厚さ約2.5−で不純物温度約5X10′Scm −’
のn型InGaAs光吸収N3、厚さ約0.5I!rn
で不純物温度約1×10I6CI11−3のn型InG
aAsP(例えばルミネセンスピーク波長λg =1.
3−)層4、厚さ約3 pmで不純物温度約3×101
6cI11−3のn型InPなだれ増倍層5を成長する
。このN5上に例えば窒化シリコン(Si、N4)によ
り厚さ約0.15−のマスクを設けて、n型1nPなだ
れ増倍層5を例えば深さ約2.5−程度メルトバンクに
よって選択的に除去し、ここに不純物温度約5X10”
cm弓のn−型InPJii6を埋め込み成′長する。For example, an n-type 1nP buffer layer 2,
Thickness is approximately 2.5- and impurity temperature is approximately 5X10'Scm-'
N-type InGaAs optical absorption N3, thickness approximately 0.5I! rn
n-type InG with an impurity temperature of about 1×10I6CI11-3
aAsP (for example, luminescence peak wavelength λg = 1.
3-) Layer 4, thickness of about 3 pm and impurity temperature of about 3×101
An n-type InP avalanche multiplier layer 5 of 6cI11-3 is grown. A mask with a thickness of approximately 0.15 mm is provided on this N5 using, for example, silicon nitride (Si, N4), and the n-type 1nP avalanche multiplication layer 5 is selectively formed, for example, by a melt bank to a depth of approximately 2.5 mm. Remove impurities here at a temperature of about 5X10”
Embed and grow cm-arch n-type InPJii6.
次いでマスクを除去してこの基体上に、例えばλg =
1.15−1不純物濃度約5X10”cm−’のn型I
nGaAsP層7をその上面が平坦となる様に成長して
いる。The mask is then removed and onto this substrate, for example λg =
1.15-1 n-type I with impurity concentration of approximately 5X10"cm-'
The nGaAsP layer 7 is grown so that its upper surface is flat.
なお本実施例で層7にInGaAsPを用いているのは
、段差のあるlnP iJ上に例えば液相エピタキシャ
ル成長方法で成長するとき、その段差を緩和し平坦化す
るのに特に適していることによる。The reason why InGaAsP is used for the layer 7 in this embodiment is that it is particularly suitable for alleviating and flattening the step when grown by liquid phase epitaxial growth, for example, on InP iJ having a step.
またInGaAsP iJ 4は既に知られている如く
、価電子帯及び伝導帯の光吸収層3となだれ増倍層5と
の間の段差を緩和してキャリアのドリフトを容易にし、
応答を高速化する効果を有する。In addition, as is already known, InGaAsP iJ 4 eases the difference in level between the light absorption layer 3 and the avalanche multiplication layer 5 in the valence band and conduction band to facilitate carrier drift,
It has the effect of speeding up the response.
この半導体基体に、例えばカドミウム(Cd)を温度約
2×1010l1lC、深さ約1.5−程度に拡散して
、p+型光受光領域8n型1nPなだれ増倍層5からn
−型TnP層6にわたって形成し、更に例えばベリリウ
ム(Be)をエネルギー140keV、 ドーズ15X
10”■4程度に「型lnP層6にイオン注入し、例え
ば温度700℃、時間20分間程度の活性化熱処理を施
して、p型ガードリング領域9を形成する。For example, cadmium (Cd) is diffused into this semiconductor substrate at a temperature of about 2 x 1010l1lC and to a depth of about 1.5- to a p+ type light receiving region 8n type 1nP avalanche multiplication layer 5 to n
- type TnP layer 6, and furthermore, for example, beryllium (Be) is formed at an energy of 140 keV and a dose of 15X.
Ions are implanted into the lnP layer 6 to a depth of approximately 10" 4, and an activation heat treatment is performed at a temperature of 700.degree. C. for approximately 20 minutes to form a p-type guard ring region 9.
この半導体基体にp側電極10及びn側電極11を形成
した本実施例について、ブレークダウン電圧vB=68
v、波長1.3μmの光に対して、バイアス電圧0.9
v、において増倍率M#30が得られており、前記従来
例のAPDO増倍率Mが高々20程度であるのに比較し
て顕著な効果が得られている。Regarding this example in which the p-side electrode 10 and the n-side electrode 11 are formed on this semiconductor substrate, the breakdown voltage vB=68
v, bias voltage 0.9 for light with a wavelength of 1.3 μm
A multiplication factor M#30 is obtained in V, which is a remarkable effect compared to the APDO multiplication factor M of the conventional example, which is about 20 at most.
以上説明した如く本発明によれば、受光領域外における
降伏の弱点の発生が十分に抑制され、なだれ増倍が設計
意図通りに実現される。また電極の信頼性も向上し、良
好な特性のAPDを優れた歩留りで製造することが可能
となる。As described above, according to the present invention, the occurrence of breakdown weak points outside the light-receiving region is sufficiently suppressed, and avalanche multiplication is realized as designed. Furthermore, the reliability of the electrode is improved, and it becomes possible to manufacture APDs with good characteristics at an excellent yield.
第1図は本発明の実施例の模式側断面図、第2図は従来
例の模式側断面図である。
図において、
1は1型InP基板、
2はn型1nPバッファ層蔦
3はn型InGaAs光吸収層、
4はn型1nGaAsP N。
5はn型1nPなだれ増倍層、
6はn−型lnP埋め込み層、
7は本発明によるn型1nGaAsP層、8はp十型受
光領域、
9はp型ガードリング領域、
10及び11は電極を示す。FIG. 1 is a schematic side sectional view of an embodiment of the present invention, and FIG. 2 is a schematic side sectional view of a conventional example. In the figure, 1 is a 1-type InP substrate, 2 is an n-type 1nP buffer layer, 3 is an n-type InGaAs light absorption layer, and 4 is an n-type 1nGaAsPN. 5 is an n-type 1nP avalanche multiplication layer, 6 is an n-type lnP buried layer, 7 is an n-type 1nGaAsP layer according to the present invention, 8 is a p-type light receiving region, 9 is a p-type guard ring region, 10 and 11 are electrodes shows.
Claims (1)
導体層(3)より禁制帯幅が大きい第1導電型の第2の
半導体層(5)と、 該第1の半導体層(3)より禁制帯幅が大きく、該第2
の半導体層(5)を選択的に除去して埋め込み成長され
た第1導電型の第3の半導体層(6)と、該第1の半導
体層(3)より禁制帯幅が大きく、該第2及び第3の半
導体層(5)(6)上を覆って上面が平坦に形成された
第4の半導体層(7)とを備えて、該第2及び第3の半
導体層(5)(6)においてpn接合を形成する第2導
電型の領域(8)が形成されてなることを特徴とする半
導体受光装置。[Claims] A second semiconductor layer (5) of the first conductivity type having a larger forbidden band width than the first semiconductor layer (3), on the first semiconductor layer (3) that performs photoelectric conversion. , whose forbidden band width is larger than that of the first semiconductor layer (3), and whose forbidden band width is larger than that of the first semiconductor layer (3).
A third semiconductor layer (6) of the first conductivity type, which is grown by selectively removing the semiconductor layer (5) of a fourth semiconductor layer (7) having a flat top surface covering the second and third semiconductor layers (5) and (6); 6) A semiconductor light receiving device characterized in that a second conductivity type region (8) forming a pn junction is formed in step 6).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60146375A JPS627176A (en) | 1985-07-03 | 1985-07-03 | Semiconductor photodetector |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60146375A JPS627176A (en) | 1985-07-03 | 1985-07-03 | Semiconductor photodetector |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS627176A true JPS627176A (en) | 1987-01-14 |
Family
ID=15406292
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60146375A Pending JPS627176A (en) | 1985-07-03 | 1985-07-03 | Semiconductor photodetector |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS627176A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6074586A (en) * | 1983-09-30 | 1985-04-26 | Fujitsu Ltd | Manufacture of semiconductor photo-detector |
-
1985
- 1985-07-03 JP JP60146375A patent/JPS627176A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6074586A (en) * | 1983-09-30 | 1985-04-26 | Fujitsu Ltd | Manufacture of semiconductor photo-detector |
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