JPS60250395A - Display control integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to display control circuits, and particularly to CR7 displays and LC displays.
The present invention relates to a display control integrated circuit that integrates a D display control circuit into a single IC chip.

Prior Art Conventionally, CR7 displays and LCD displays have been put into practical use as display devices. And usually the display is CR7 display or L
Either CD display is used. Therefore, two control circuits, a CR7 display control circuit and an LCI) display control circuit, are provided, and one of them can be selected and used. However, this requires the provision of two chips: an integrated circuit for controlling the CRT display and an integrated circuit for controlling the LCD display, resulting in disadvantages such as increased cost and increased power consumption.

OBJECTS OF THE INVENTION In order to solve the above-mentioned problems, an object of the present invention is to provide a display control integrated circuit that incorporates a CR7 display and an LCD display control in a single chip.

Means for Solving Problems In the present invention, the output of the CR7 display control circuit is utilized to obtain an LCD display control signal. LCl) requires unique timing that is different from that of CRT, but there are many operations in common with CRT display regarding the display operation. Therefore, in the present invention, the output of the CRT display control is used as the input for the LCD display control, and a part of the output is shared, and this is integrated into one chip, thereby reducing the cost and power consumption of the device.

An example of the system configuration of the present invention is shown in FIG. The contents of the display data memory 1 are read out under the control of the display control IC 2, and the desired display timing and display data are read out from the CR.
It is supplied to T3 and becomes a display screen, and at the same time it is supplied to LC.
It is also possible to display D4.

As a display device, it is not necessary to use both at the same time; only one is normally used. As shown in FIG. 2, the display control rc2 includes a CRT display control circuit 5 and an LCD display control circuit 6 in one chip. Then, as shown in FIG. 6, the CR7 display timing signal 7 and the LC
I) It has two types of display timing signals 8. CR7 display timing signal 7 is H5YNC, which becomes a horizontal synchronization signal.
rSYNC, which is a vertical synchronization signal, and DOT, which is a display data signal, are required, and the LCD display timing signal 8 is
DOT, which becomes display data, is shared, and other signals include frame signal FRM, common start signal I)Y, and latch pulse L.
A total of six signals are required: P, dot data timing SCK of the dot signal, and display start timing ELNK.

FIG. 4 shows the display panel section of the LCD, and the LCD panel 9
A shift register 16. An analog driver 14 is provided, LP is input as a shift register 16 clock, and the common start is DY. Furthermore, the segment 1111j includes a shift register 10, a latch 11 .
An analog driver 12 is provided, DOT is written into the shift register 10 by the dot data timing signal SCK, and the shift register 1 is written by the next latch pulse signal LP.
The contents of 0 are transferred to latch 11 and it is displayed in the next display period. Frame signal FH is input to analog driver 10.14 on the common side and segment side, and frame 1
The voltage applied to the LCD is changed to alternating current at regular intervals.

These LCD display timing signals are generated by the LCD display control circuit of the display control IC. However, in view of speed, some of these signals may be configured by external circuits. The minimum required signals are common start signal DY, latch pulse LP, and cheater block SCK.

and a display start signal BLNK. Furthermore, in the present invention, in the display control IC, the data displayed on the LCD is
It is created under the control of the display control rc during the immediately preceding rask scan period (that is, the immediately preceding display data output period).

EMBODIMENT OF THE INVENTION FIG. 5 shows an embodiment of the invention, which consists of six basic blocks 15-21, each having a required timing output. In the figure, DOT is a display data output, and data is output in 1-bit serial or 4 to 8 parallel.

Since this part is extremely high speed, the dot control circuit may be externally connected in some cases. ELNK is a signal output indicating the display start position (display period).

H5YNC is a horizontal synchronization signal and becomes a rask scan (D synchronization signal). VSYNC is a vertical synchronization signal and becomes a display synchronization signal for one screen. On the other hand, on the LCD display control side in the figure, FRM is an AC signal on the LCD display. It is a drive signal, and in LCD display, the voltage applied to the liquid crystal must be changed to AC in one or two frames, so it is an AC conversion timing signal.DY is a common start signal and a hail signal that changes the voltage applied to the LCD screen. It marks the very beginning.

LP is a segment data latch signal, which is a timing signal table for displaying segment data every rask scan. SCK is a data clock and indicates the output timing of display data. Composition of each part.

In operation, the clock input (CLK) is connected to each block 1
5 to 21 basic clocks and is a synchronization signal for display data, but any number of clocks may be used for display data. The horizontal synchronization control block 16 divides CLK,
The horizontal synchronization signal H5YNC and display memory address are generated, and the vertical synchronization control block 17 generates VSYNC and display memory address according to CLK and the output signal of the horizontal synchronization control block 16.

Horizontal synchronization control block 16 and vertical synchronization control block 17
A display start signal ELNK is generated in the display position control block 15 by the output signal. Then, a dot take control block 21 generates display data DOT from the output signal of the display position control block 15 and the display memory data. Here, the dot data control block 21 may be an external circuit for reasons such as speeding up. Furthermore, the LCD display control circuit side B has a display position control block 1 on the CRT display circuit side A.
5. Horizontal synchronization control block 16. Each output signal of the vertical synchronization control block 17 is input, and the frame control block 1
8 generates a frame control signal FRM, and a common control block 19 generates a common control signal LP. Furthermore, the output of the display position control block is input, and the segment control block 20 generates the segment control signal 5CK2G.

FIG. 6 shows a waveform diagram of each display control signal.

The period when BLNK rises from II Z n to H# and it is the display period, and H5YNC goes high is the horizontal synchronizing signal period,
The BLNK signal is used to prevent the period including the period before and after that from being displayed. The waveforms shown in the 4th column and below are compressed as shown by the broken line, and there is H5YNC in each section corresponding to BLNK, and H5YNC in each interval corresponding to BLNK.
are gathered and VSYNC becomes H'', resulting in one screen.DO
T is display data, and during the display period, dot take is generated as display data during a period when the ELNK signal is not input. Furthermore, in the case of LCD, FRM, DY, LP
A double signal is generated, LP is a signal corresponding to H5YNC as mentioned above, and DY is a signal indicating the common start position and V
It corresponds to SYNC, and FRM has one period with the period of Cf)Y in the figure.

Although one embodiment has been shown above, the present invention is not limited to this and can be modified in many ways. For example, H5YNC, V
Although SYNC has been described as an output signal, the same applies even if it is input from the outside. CLK may be any clock (an integral multiple) of the display data. For the sake of explanation, the data to the display memory address is shown with terminals divided into input and output, but the same applies to input and output in order to save terminals.

Effects of the Invention As detailed above, the LCD display requires a unique timing signal, but since the display has many operations in common with the CR7 display, the present invention is different from the present invention (by providing different signals to the CR7 display control circuit). By incorporating the generation circuit into a single-chip display control circuit, it is possible to expect lower costs, smaller size, and lower power consumption.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the system configuration in the display control integrated circuit of the present invention, FIG. 2 is a schematic diagram of the display control integrated circuit of the present invention, and FIG. 6 is each output signal of the display control integrated circuit of the present invention. 4 is a diagram showing an LCD display panel section, FIG. 5 is a configuration diagram of a display control integrated circuit of the present invention, and FIG. 6 is a waveform diagram of each signal in the display control integrated circuit of the present invention. (Main symbols) 1...Display data memory, 2...Display control IC, 5
...CRT, 4...LCD, 5...CR7 display control circuit, 6...LCD display control circuit, 7...CR7
Display timing signal, 8...LCD display timing signal Patent applicant Fujitsu Limited Patent attorney Gobe Tamamushi (1 other person) Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] An external terminal to which one of two sets of display timing outputs used simultaneously or exclusively is connected to the liquid crystal display, an external terminal to input or output a horizontal synchronization signal and a vertical synchronization signal, and an external terminal to which the horizontal synchronization signal and vertical synchronization signal are input or output. a circuit block that receives a synchronization signal and generates a signal indicating the start or end of the display screen; A display control integrated circuit comprising a circuit block that generates.