KR20000050878A - Liquid crystal display using dual scan driving method - Google Patents

Abstract

PURPOSE: A liquid crystal display device using dual scan driving method is provided to reduce the cost of manufacturing. CONSTITUTION: A liquid crystal display device using dual scan driving method includes a timing controller(100), a first and second gate drivers, a first and second data drivers, and a panel(40). The timing controller(100) receives outward data, clock signal, and a synchronous signal, and outputs a control signal and data for displaying the data. The first and second gate drivers generate first and second gate driving signals according to the control signal, respectively. The first and second data drivers output the output data of the timing controller in a predetermined status according to the control signal. The panel(40) displays the output data of the first and second data drivers according to the first and second gate driving signals. The timing controller includes a first and second memory(11,12) as well as a data controller(10,20). The first and second memories(11,12) store outward data. The data controller(10,20) control the panel to write on/read from the memories alternatively.

Description

Liquid crystal display using dual scan driving method {LIQUID CRYSTAL DISPLAY USING DUAL SCAN DRIVING METHOD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display (LCD), and more particularly, to a liquid crystal display using a dual scan driving method.

Currently, panels of thin film transistor liquid crystal displays have a higher resolution and a larger area. The higher the resolution, the higher the frequency and the shorter the time to display one line, which makes it difficult to implement circuits in SXGA (1280 * 1024) and UXGA (1600 * 1200) resolutions.

For this reason, there is a disadvantage in that a phenomenon in which the liquid crystal pixel cannot be charged up to a charging voltage required by the liquid crystal pixel is conventionally generated.

Accordingly, a dual scan method has recently emerged. In this method, the gate driver is divided into two parts to drive the thin film transistor of the panel to simultaneously apply data of the upper and lower parts to the panel.

The technical problem to be solved by the present invention is to solve the above disadvantages, and to apply an accurate data voltage to a high resolution and / or large area panel using a synchronous graphic RAM (SGRAM) and a dual scan driving scheme. To provide a liquid crystal display device using a dual scan drive method.

1 is a block diagram of a liquid crystal display device using a dual scan driving method according to an embodiment of the present invention.

FIG. 2 is a detailed view of the controller of FIG. 1.

3 is a timing diagram of write / read operation of data according to a vertical synchronization signal.

4 is a data input / output timing diagram in pixel units of data.

In order to solve this problem, in a liquid crystal display device displaying data on a panel by a dual scan driving method, the first and second memories store external data. The data controller controls to write / read the external data to the first and second memories in response to an external control signal and output data to the panel. In this way, a large-area, high-resolution liquid crystal display device can be realized.

Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of a liquid crystal display using a dual scan driving method according to an embodiment of the present invention.

FIG. 2 is a detailed view of the controller of FIG. 1.

As shown in FIG. 1, a liquid crystal display using a dual scan driving method according to an exemplary embodiment of the present invention includes a control unit 100, source driver integrated circuits CU1 to CU16, CD1 to CD16, an upper gate driver 200, The lower gate driver 300 and the panel 40 are included.

As shown in FIG. 2, the control unit 100 includes data controllers 10, 20, 30 and memories 11, 12, 13, 14, 15, and 16, and the data controller and the memory include R and G. FIG. , B is present for each data respectively.

Next, the operation of the embodiment of the present invention will be described in detail with reference to FIGS. 1 to 4.

3 is a timing diagram of a write / read operation of data according to a vertical synchronization signal;

4 is a timing diagram of a write / read operation of data according to a horizontal synchronization signal.

First, when power is applied by the user, the control unit 100 receives R, G, B data, clock signal CLOCK, data enable signal DE, horizontal synchronization signal HSYNC, and vertical synchronization signal VSYNC from the outside. Is input to the data processing controllers 10, 20, 30. In general, in the UXGA thin film transistor liquid crystal display, the frequency of the standard clock signal is very high as 160 MHz. In the present invention, a four-divided signal, that is, a clock signal and data of 40 MHz is received. The timing diagram of the input signal is shown in FIG.

The data processing controllers 10, 20, and 30 receiving data of each of R, G, and B store or read the data in the SGRAMs 11, 12, 13, 14, 15, and 16 having bidirectional ports. Data read from (11, 12, 13, 14, 15, 16) is stored in the line memory inside the data processing controllers 10, 20, 30, and rearranged to fit the data driving integrated circuit arrangement. 31: 0) and down_data (31: 0), and are applied to the panel 11 according to the gate driving signals G1 to Gm and Gm + 1 to G2m of the upper and lower gate drivers 200 and 300.

Since the operations of the data processing controllers 10, 20, and 30 are the same, the following description will focus on one data processing controller 10.

As shown in FIG. 3, when the data W1 of the first line is written to the SGRAM 11, the data R601 of the line 601 is read into the data processing controller 10. As shown in FIG.

Next, the data W2 of the second line is written to the SGRAM 12 and the data R1 of the first line of the line 602 is read by the data processing controller 10.

In this manner, data read / write operations are performed in the order as shown in FIG. 3, and the read data is output to the source driver integrated circuits CU1 to CU16 and CD1 to CD16.

As shown in FIG. 3, the order of data stored in the SGRAMs 11 and 12 is that the data of the odd-numbered line is stored in the SGRAM 11 from line 1 to line 601, and the data of the even line. Is stored in the SGRAM 12, and the data of the even line is stored in the SGRAM 11 and the data of the odd line is stored in the SGRAM 12 from the line 601 which is the middle of the frame. By doing so, it is possible to prevent the case of reading twice from the SGRAMs 11 and 12 which are memories.

4 shows a data input / output timing chart in pixel units of data.

As shown in Fig. 4, the input data is divided into four data, and the output data is doubled in clock cycles compared with the input. A dividing method of dividing the integrated circuit into two by eight is used.

That is, data is simultaneously loaded into the 1st, 2nd, 9th, and 10th source driver integrated circuits CU1, CU2, CU9, CU10, CD1, CD2, CD9, and CD10.

Next, data is loaded into the 3rd, 4th, 11th, and 12th source driver integrated circuits CU3, CU4, CU11, CU12, CD3, CD4, CD11, and CD12.

Next, data is loaded into the 5th, 6th, 13th, and 14th source driver integrated circuits CU5, CU6, CU13, CU14, CD5, CD6, CD13, and CD14.

Next, data is loaded into the 7, 8, 15, and 16th source driver integrated circuits CU7, CU8, CU15, CU16, CD7, CD8, CD15, and CD16.

Thus, 1600 pixels of data are displayed and the output frequency is 20 MHz, which is one eighth of the original reference clock. Therefore, the source driver integrated circuits CU1 to CU16 and CD1 to CD16 are driven by the 20 MHz clock.

Next, when data is output to the panel 40 through the source driver integrated circuits CU1 to CU16 and CD1 to CD16 at this timing, the panel displays one screen.

Although the above description focuses on the portion corresponding to the R data, the same applies to the G and B data.

As described above, in the embodiment of the present invention, it is possible to reduce the cost by implementing the dual scan drive method using the S-GRAM.

The present invention can be applied to 21.3 inch or 30 inch UXGA products, which can be changed to a larger screen or a smaller screen.

In addition, the 16 source driver driving integrated circuits transfer data of the 1 st to 8 th and 9 th to 16 th separate circuits into separate data lines to halve the number of data lines and halve the length of the data lines.

Claims (4)

A timing controller which receives external data, a clock signal, and a synchronization signal, and outputs a control signal and data for displaying data; First and second gate drivers configured to output first and second gate driving signals according to the control signal; First and second data drivers for outputting the output data of the timing controller in a predetermined form according to the control signal; A panel for displaying output data of the first and second data drivers according to the first and second gate driving signals, The timing controller, First and second memories for storing the external data; And a data controller configured to alternately write / read the external data to first and second memories according to the external clock signal to output data to the panel. In claim 1, And a controller and a memory for the data controller and the first and second memories, respectively, for each of R, G, and B data. In claim 1, The first and second memories are first and second SRAMs, The order of data stored in the first and second SGRAMs 11 and 12 is that the data of the odd-numbered line is stored in the first SGRAM 11 from the first line to the 600th line, Data is stored in the second esram 12, From line 601 to line 1200 in the middle of the frame, the data of the even-numbered line is stored in the first SGRAM 11, and the data of the odd-numbered line is stored in the second SGRAM 12. Liquid crystal display device. In claim 3, The order of reading the data stored in the first and second SGRAMs 11 and 12 is Between the intervals in which the data from the first line to the 600th line are stored, the odd numbered data of the first line to the 299 line and the even-numbered data of the line 602 to the 900 line are alternated in the first SGRAM. Reading, The odd numbered data of lines 601 to 899 and the even numbered data of line 2 to 300 are alternately read from the second SGRAM. Between each interval in which data from line 601 to line 1200 is stored, the odd numbered data of line 301 to line 599 and the even numbered data of line 902 to line 1200 are alternated in the first SGRAM. Reading, An odd-numbered data from line 901 to line 1199 and even-numbered data from line 302 to line 600 are alternately read from the second S-RAM.