KR20070083361A - Display device and driving method of the same - Google Patents

Abstract

A display apparatus and a driving method thereof are provided to drive a display panel partially without changing configuration of a gate driver by inactivating gate lines during a low level period in which the first and second clock signals are maintained at a low level. A display apparatus includes a display panel(100), a timing controller(130), a clock signal controller(140), and a gate driver(110). The display panel includes plural pixels, which are defined by gate and data lines. The timing controller generates gate clock and clock control signals. The clock signal controller outputs first and second clock signals based on the gate clock signal, and maintains the first and second clock signals at a low level in response to the clock control signal. The gate driver is composed of registers having plural cascaded stages, and outputs gate signals to the gate lines based on the first and second clock signals. The corresponding gate lines are inactivated during the period in which the first and second clock signals are maintained at low level.

Description

DISPLAY DEVICE AND DRIVING METHOD OF THE SAME}

1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.

FIG. 2 is a detailed block diagram of the gate driver shown in FIG. 1.

FIG. 3 is a diagram illustrating an internal configuration of each stage of the gate driver shown in FIG. 2.

4 is a signal waveform diagram of the gate driver shown in FIG. 1.

5A is a diagram schematically illustrating a clock signal controller according to a first embodiment of the present invention.

FIG. 5B is a signal waveform diagram of the clock signal controller shown in FIG. 5A.

6A is a diagram schematically illustrating a clock signal controller according to a second embodiment of the present invention.

FIG. 6B is a signal waveform diagram of the clock signal controller shown in FIG. 6A.

<Description of the symbols for the main parts of the drawings>

100: display panel 110: gate driver

120: data driver 130: timing controller

140: clock signal controller 150: driving voltage generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device and a driving method thereof, and more particularly, to a display device for partially driving a display panel and a driving method thereof.

In general, a display device includes a display panel, a gate driver for outputting a gate signal to a gate wiring of the display panel, and a data driver for outputting a data signal to a data wiring of the display panel in synchronization with the gate signal. In general, the gate driver and the data driver are integrated to form a chip.

Recently, a method of directly forming a gate driver (eg, a gate driver circuit) on a display panel has been used in order to reduce defects occurring in the process of mounting a chip-type gate driver on a display panel.

The gate driving circuit is composed of one shift register including a plurality of stages connected in cascade, and each stage is connected in one-to-one correspondence with the gate wiring to output a gate signal.

Such a gate driving circuit has a problem in that partial driving of the display panel is difficult as a plurality of stages are connected and driven dependently, and a circuit must be changed to partially drive the display panel.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a gate driving circuit and a driving method thereof for partially driving the display panel.

A display device according to an exemplary embodiment for realizing the object of the present invention includes a display panel, a timing controller, a clock signal controller, and a gate driver. The display panel includes a plurality of pixel parts formed by intersecting gate lines and data lines. The timing controller generates a gate clock signal and a clock control signal, and the clock signal controller outputs a first clock signal and a second clock signal based on the gate clock, and responds to the clock control signal. The second clock signal is kept at a low level. The gate driver includes a shift register including a plurality of stages connected in a cascade manner, and outputs a gate signal to the gate lines based on the first clock signal and the second clock signal.

At this time, the gate lines corresponding to the section for maintaining the first clock signal or the second clock signal at a low level are inactivated.

According to an aspect of the present invention, there is provided a method of driving a display device, the method including: generating a data control signal, a gate clock signal, and a clock control signal; Outputting a data signal to the data lines in response to the data control signal; A first clock signal and a second clock signal are output based on the gate clock signal, and the first clock signal or the second clock signal is kept at a low level in response to the clock control signal, and the normal and sustain periods are maintained. Distinguishing; And outputting a gate signal to gate lines formed on the display panel based on the first clock signal and the second clock signal, and deactivating the gate lines in the sustain period.

According to the display device and the driving method thereof, the display panel can be partially driven by controlling the first clock signal and the second clock signal provided to the gate driver to output a low level gate signal.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the display device includes a display panel 100, a gate driver 110, a data driver 120, a driving voltage generator 150, a clock signal controller 140, and a timing controller 130. .

The display panel 100 includes an array substrate and an opposing substrate (eg, a color filter substrate) bonded to each other at a predetermined interval, and a liquid crystal layer interposed between the array substrate and the opposing substrate, and intersects the gate lines GL1 to GLn. And the plurality of pixel portions are formed by the data lines DL1 to DLm. Each pixel unit includes a thin film transistor TFT, a liquid crystal capacitor CLC, and a storage capacitor CST electrically connected to the thin film transistor TFT. The gate electrode and the source electrode of the thin film transistor TFT are connected to the gate line GL and the data line DL, respectively, and the liquid crystal capacitor CLC and the storage capacitor CST are electrically connected to the drain electrode.

The driving voltage generation unit 150 generates and provides driving voltages for driving each unit based on an externally provided power supply voltage. In detail, the data driver 120 supplies the reference gray voltage VREF, the gate driver 110 supplies the gate voltages including the gate on voltage Von and the gate off voltage Voff, and the display panel 100. ) Provides a common voltage (Vcom).

The timing controller 130 may generate synchronization signals and data signals DATA including a main clock signal MCLK, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE from an external device. Receive input. The gate control signal including the gate clock signal GATE CLK, the vertical start signal STV, and the clock control signal CK_CS, the horizontal start signal STH, and the load signal LOAD based on the received synchronization signals. It generates and outputs a data control signal. In addition, the input data signal is provided to the data driver 120.

The data driver 120 converts the data signal DATA into a corresponding analog data voltage in response to the data control signal provided by the timing controller 130, and then forms the data lines DL1 to DLm formed on the display panel 100. ) In this case, the analog data voltage is converted based on the reference gray voltage VREF provided from the driving voltage generator 150.

The clock signal controller 140 receives a gate clock signal and a clock control signal from the timing controller. The first clock signal and the second clock signal are output based on the input gate clock signal. Specifically, the first clock signal or the second clock signal is kept at a low level in response to the clock control signal. That is, one of the first clock signal and the second clock signal output based on the gate clock signal is maintained at a low level.

Meanwhile, although the clock signal controller 140 is separately illustrated in the drawing, this is to clarify the functional division. In general, the clock signal controller 140 is integrated with the timing controller 130 in a chip form.

The gate driver 110 is provided from the first clock signal and the second clock signal provided by the clock signal controller 140, the vertical start signal STV and the driving voltage generator 150 provided from the timing controller 130. The gate signal is output to the gate lines GL1 to GLn based on the received gate off voltage Voff. Here, the first clock signal and the second clock signal are out of phase with each other.

FIG. 2 is a detailed block diagram of the gate driver shown in FIG. 1.

Referring to FIGS. 1 and 2, the gate driver 110 includes one shift register including n + 1 stages SRC1 to SRCn + 1 connected to each other, and n + 1 stages SRC1 to SRCn. +1) includes n driving stages SRC1 to SRCn and one dummy stage SRCn + 1. The gate driver 110 is formed on the same substrate as the substrate of the display panel 100 in which the gate lines GL1 to GLn and the data lines DL1 to DLm and the thin film transistor TFT, which is a switching element, are formed. .

Each stage of the gate driver 110 includes a first input terminal IN1, a second input terminal IN2, a first clock terminal CK, a second clock terminal CKB, a power supply terminal VSS, and an output terminal OUT. The power supply terminal VSS has a gate-off voltage Voff input thereto.

The first clock terminal CK1 and the second clock terminal CK2 of each stage have the first clock signal CK and the second clock terminal CK1 and the second clock terminal CK2 of the odd stage, respectively. The clock signal CKB is supplied, and the second clock signal CK and the second clock signal CKB are supplied to the first clock terminal CK1 and the second clock terminal CK2 of the even-numbered stage, respectively.

The output terminal OUT of each stage outputs the gate signals GS1 to GSn + 1 synchronized with the first clock signal CK or the second clock signal CKB received through the first clock terminal CK1. . That is, the odd-numbered stage outputs the gate signal synchronized with the first clock signal CK, and the even-numbered stage outputs the gate signal synchronized with the second clock signal CKB. In this case, the output terminals OUT of the n driving stages SRC1 to SRCn except for the dummy stage SRCn + 1 are connected in one-to-one correspondence with the gate lines GL1 to GLn formed in the display panel 100.

Therefore, the gate signals GS1 to GSn output from the output terminals OUT of the n driving stages SRC1 to SRCn are sequentially applied to the gate lines GL1 to GLn, and the dummy stages SRCn + 1 of the dummy stages SRCn + 1. The gate signal GSn + 1 output from the output terminal OUT is not output to the gate line GL.

The gate signal GS output through the output terminal OUT is supplied to the second input terminal IN2 of the previous stage and the first input terminal IN1 of the next stage. Here, the vertical start signal STV is applied to the first input terminal IN1 of the first stage SRC1 without the front stage and the second input terminal IN2 of the n + 1th stage SRCn + 1 without the next stage. ) Is supplied.

The first clock signal CK, the second clock signal CKB, the vertical start signal STV, and the gate-off voltage Voff are disposed at one side of the shift register including the n + 1 stages SRC1 to SRCn + 1. An applied wiring portion is formed, and is electrically connected to each stage through a connection wiring.

FIG. 3 is a diagram illustrating an internal configuration of each stage of the gate driver shown in FIG. 2.

2 and 3, each stage SRC of the gate driver 110 may include a pull-up driver 310, a first pull-up drive controller 320, a second pull-up drive controller 330, and a pull-down driver 340. And a holding part 350. For convenience of description, only the arbitrary stage SRCi will be described.

The pull-up driver 310 includes a gate electrode connected to a T1 node, controlled by the control signal CNTR1, a drain electrode receiving a first clock signal CK, and a source electrode connected to an output terminal OUT. One transistor TR1 is included. In addition, a first capacitor C1 is formed between the gate electrode and the source electrode of the first transistor TR1. Here, the first capacitor C1 is formed of a parasitic capacitor or an additionally added capacitor. Preferably, since the first capacitor C1 stores the control signal CNTR1 of the T1 node to serve as boot strapping, an overlap area between the gate electrode and the source electrode is defined as the gate electrode and the drain electrode. It is formed to have a larger capacity by increasing the area of overlap with.

The first pull-up driving controller 320 includes a second transistor TR2 in which a drain electrode and a gate electrode are commonly connected, and the gate signal GSi-1 of the front stage is input, and the input gate signal GSi-1 is input. Outputs a control signal CNTR1 to the T1 node.

The second pull-up driving controller 330 receives the gate signal GSi + 1 output from the output terminal 360 of the next stage, and the drain electrode of the second pull-up driving controller 330 is connected to the T1 node to supply the first transistor TR1. The third electrode TR3 is connected to the gate electrode and the source electrode is connected to the gate off voltage Voff. When the gate electrode is turned on by the gate signal GSi + 1 output from the output terminal 360 of the next stage, the gate off voltage Voff is provided to the T1 node.

The gate signal output terminal 360 is connected to the first pull-up driving controller of the next stage SRCi + 1 and the second pull-up driving controller of the front stage SRCi-1, and the gate signal GSi of the i-th stage SRCi. ) Will be printed.

The pull-down driver 340 includes the fourth transistor TR4. The gate electrode of the fourth transistor TR4 receives the second clock signal CKB, the source electrode receives the gate off voltage Voff, and the drain electrode of the first transistor TR1 of the pull-up driver 310. It is connected to the source electrode and the output terminal 360. The pull-down driver 340 is controlled by the second clock signal CKB to inactivate the gate line GL.

The holding part 350 includes a fifth transistor TR5, a seventh transistor TR7, and a second capacitor C2. Gate electrodes of each of the fifth transistor TR5 and the seventh transistor TR7 are connected to a node T2, and the source electrode is connected to a gate off voltage Voff. One end of the second capacitor C2 is connected to the first clock signal CK. The gate electrodes of the fifth transistor TR5 and the seventh transistor TR7 are connected to the drain electrode of the sixth transistor TR6 connected to the T1 node, and when the sixth transistor TR6 is turned on The fifth transistor TR5 and the seventh transistor TR7 are turned off by the gate off voltage Voff. When the sixth transistor TR6 is turned off, the gate electrodes of the fifth transistor TR5 and the seventh transistor TR7 are charged by the second capacitor C2 charging the first clock signal CK. The clock signal CK is output to the T1 node and the output terminal 360. Therefore, the holding unit 350 outputs the first clock signal CK to the i-th gate line GLi as the gate signal GSi, and then, before the i + 1th gate line GLi + 1 is activated, the first unit 350. The clock signal CK is maintained to be output to the i-th gate line GLi. That is, the holding unit 350 serves to prevent a malfunction signal from being applied to the gate line GLi while one frame is being driven. Therefore, the output terminal 360 is maintained by the operations of the fifth transistor TR5 and the fourth transistor TR4 which are turned on in response to the first clock signal CK and the second clock signal CKB.

4 is a signal waveform diagram of the gate driver shown in FIG. 1.

1 to 4, the gate driver 110 of the present invention maintains the first clock signal CK and the second clock signal CKB at a low level and a high level, respectively, by a clock control signal CK_CS. At the same time, the corresponding i + 1 th stage SRCi + 1 outputs a low level signal. Therefore, the stages SRCi + 1 to SRCn + 1 after the i + 1th stage SRCi + 1 all output a low level signal.

Specifically, the i + 1th stage SRCi +! Corresponding to the time point at which the first clock signal CK and the second clock signal CKB are held receives the high level gate signal from the previous stage. IN1). Accordingly, the first pull-up driver 320 drives the first transistor TR1 to turn on, but the low level signal is output to the output terminal 360 because the first clock signal CK maintains the low level.

As a result, the first pull-up driving controller cannot be turned on by the low-level signal output from the i-th second stage SRCi + 2, and finally outputs the low-level signal.

Accordingly, the i + 1th stage SRCi + 1 corresponding to the point where the first clock signal CK and the second clock signal CKB maintain the low level and the high level, respectively, outputs a low level signal. Therefore, the subsequent stages SRCi + 1 to SRCn +! All output a low level signal.

On the other hand, when the next frame is started and the vertical start signal STV is applied, the first stage SRC1 is driven to output a high level gate signal, and the above-described operation is repeated.

That is, the first to i-th stages SRC1 to SRCi before the time when the first clock signal CK and the second clock signal CKB are maintained at the same level by the clock control signal CK_CS are normally driven. The gate signal is output at a high level, and the i + 1 to n + 1th stages SRCi + 1 to SRCn + 1 after the holding time are abnormally operated to output a low level signal to the gate line.

Accordingly, the display panel displays the image by operating the upper region corresponding to the first to i-th gate lines GL1 to GLi normally, and corresponds to the i + 1 to n-th gate lines GLi + 1 to GLn. The lower region does not work.

5A is a diagram schematically illustrating a clock signal controller according to a first embodiment of the present invention, and FIG. 5B is a signal waveform diagram of the clock signal controller illustrated in FIG. 5A.

5A and 5B, the clock signal controller 140 according to the first embodiment of the present invention includes an AND operation element.

The AND operation element receives the gate clock signal GATE CLK and the clock control signal CK_CS through two input terminals, and performs an AND operation. The output terminal of the logical AND unit is branched into the non-inverting output terminal and the inverting output terminal. The non-inverting output terminal outputs the result value of the logical AND unit as it is, and the inverting output terminal inverts the result value of the logical AND unit through the inverting logic element. And print it out. Here, the clock signal output to the non-inverting output terminal is the first clock signal CK, and the clock signal output to the inverting output terminal is the second clock signal CKB. Therefore, the first clock signal CK and the second clock signal CKB are reversed in phase.

The clock control signal CK_CS is sequentially applied with the first level and the second level in one frame period, and specifically, the high level and the low level are sequentially applied. Here, the second level section having the low level corresponds to the section keeping the first clock signal CK at the low level.

That is, the logical AND element has a characteristic of outputting a high level signal only when both input signals are high level. Therefore, the first clock signal CK corresponding to the gate clock signal GATE CLK is output in the first level section in which the clock control signal CK_CS has a high level, and the clock control signal CK_CS has a low level. In the two-level period, the first clock signal CK is maintained at a low level regardless of the gate clock signal GATE CLK.

At this time, since the second clock signal CKB is a signal obtained by inverting the first clock signal CK, which is a result of the logical product operation element, the second clock signal CKB is maintained at a high level in the second level section having a low value.

The clock signal controller is a method of maintaining the first clock signal at a low level, and a method of maintaining the second clock signal at a low level will be described below.

6A is a diagram schematically illustrating a clock signal controller according to a second exemplary embodiment of the present invention, and FIG. 6B is a signal waveform diagram of the clock signal controller illustrated in FIG. 6A.

6A and 6B, the clock signal controller 140 according to the second embodiment of the present invention includes a logical sum operation element.

The OR operation element receives the gate clock signal GATE CLK and the clock control signal CK_CS through two input terminals, and performs logical sum association. The output terminal of the logical sum operation element is branched into the non-inverted output terminal and the inverted output end. The non-inverted output terminal outputs the result value of the logical sum operation element as it is, and the inverted output terminal inverts the result value of the logical sum operation element through the inversion logic element. . Here, the clock signal output to the non-inverting output terminal is the first clock signal CK, and the clock signal output to the inverting output terminal is the second clock signal CKB. Therefore, the first clock signal CK and the second clock signal CKB are opposite in phase.

The clock control signal CK_CS is sequentially applied with the first level and the second level in one frame period, and specifically, the low level and the high level are sequentially applied. The second level section having the high level corresponds to the section keeping the second clock signal CKB at the low level.

That is, the OR operation element has a characteristic of outputting a low level signal only when both input signals are at a low level. Accordingly, the first clock signal CK corresponding to the gate clock signal GATE CLK is output in the first level section in which the clock control signal CK_CS has a low level, and the clock control signal CK_CS has a high level. In the two-level period, the first clock signal CK is maintained at a high level regardless of the gate clock signal GATE CLK. That is, the second clock signal CKB inverting the first clock signal CK is maintained at a low level corresponding to the second level section of the clock control signal.

In some cases, the timing controller may generate and supply the first clock signal and the second clock signal to the clock signal controller. In this case, the clock signal controller may be formed of an AND logic element, and thus, the first clock signal or the second clock signal may be used. And a first holding part for holding the signal at a low level in response to the first clock control signal.

The clock signal controller may further include a second holding part configured as a logic sum operation element to hold the second clock signal or the first clock signal at a high level in response to the second clock control signal.

Here, the first clock control signal and the second clock control signal are signals having opposite phases to each other. Since the first holding part and the second holding part, the first clock control signal, and the second clock control signal can be easily inferred through FIGS. 5A and 5B, and FIGS. 6A and 6B, detailed descriptions thereof will be omitted.

As described above, according to the present invention, the structure of the gate driver is maintained by maintaining the first clock signal and the second clock signal provided to the gate driver at the same level, and outputting a gate signal having a low level after the retention time. The display panel can be partially driven without changing.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (10)

A display panel including a plurality of pixel portions formed by crossing gate lines and data lines; A timing controller configured to generate a gate clock signal and a clock control signal; A clock signal controller configured to output a first clock signal and a second clock signal based on the gate clock signal, and to maintain the first clock signal or the second clock signal at a low level in response to the clock control signal; And A shift register including a plurality of stages connected in cascade, and including a gate driver configured to output a gate signal to the gate lines based on the first clock signal and the second clock signal, And the gate lines corresponding to a section for maintaining the first clock signal or the second clock signal at a low level are inactivated. The method of claim 1, wherein each stage of the gate driver A first pull-up driving controller configured to receive a gate signal of an adjacent stage and output a control signal; A pull-up driver configured to receive the first clock signal and output a gate signal to an output terminal in response to the control signal; A holding unit configured to hold the gate wiring in a pull-down state at a gate-off voltage in response to the first clock signal; And And a pull-down driver configured to pull down the gate line in response to a second clock signal. The clock signal controller of claim 2, wherein the clock signal controller comprises a logical AND operator receiving the gate clock signal and the clock control signal. And maintaining the first clock signal at a low level in response to the clock control signal, wherein the clock control signal has a high level and a low level sequentially in one frame period. The clock signal control unit of claim 2, wherein the clock signal controller includes a logical sum operator configured to receive the gate clock signal and the clock control signal. The second clock signal is maintained at a low level in response to the clock control signal, wherein the clock control signal has a low level and a high level sequentially in one frame period. 3. The display device of claim 2, wherein the gate clock signal comprises a first gate clock signal and a second gate clock signal that are out of phase with each other. 4. The clock signal controller of claim 5, wherein the clock signal controller includes a logical product operator configured to receive the first gate clock signal and the clock control signal. And the clock control signal has a high level and a low level sequentially in one frame period. The clock signal control unit of claim 5, wherein the clock signal controller includes a logical sum calculator configured to receive the second gate clock signal and the clock control signal. And the clock control signal has a low level and a high level sequentially in one frame period. A driving method of a display device including a plurality of pixel parts by crossing gate lines and data lines, Generating a data control signal, a gate clock signal, and a clock control signal; Outputting a data signal to the data lines in response to the data control signal; A first clock signal and a second clock signal are output based on the gate clock signal, and the first clock signal or the second clock signal is kept at a low level in response to the clock control signal, and the normal and sustain periods are maintained. Distinguishing; And And outputting a gate signal to gate lines formed in the display panel based on the first clock signal and the second clock signal, and deactivating the gate lines in the sustain period. Driving method. The method of claim 8, wherein the clock control signal has a first level and a second level sequentially in one frame period, and the first clock signal or the second clock signal is set to a low level in correspondence to the second level period. And holding the display device. The method of claim 9, wherein the first level and the second level are opposite in phase to each other.

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