JPS6292995A - Liquid crystal display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a liquid crystal display device that can be connected to, for example, a personal computer or the like so as to be replaceable with a CRT display device.

[Prior art]

For example, in order to drive a CRT display device from a personal computer, a horizontal synchronization signal, a vertical synchronization signal, and a video signal are output.

Conventional liquid crystal display devices are driven by a completely different driving principle from that of CRT display devices, such as by applying an alternating current voltage between the transparent electrode and the back electrode of each pixel. It was necessary to supply a synchronization signal dedicated to the liquid crystal display device, a shift clock alternating signal for controlling the timing of changing the signal to alternating current, and a liquid crystal video signal from the personal computer.

In order to display an image corresponding to the image on a liquid crystal display by directly inputting the signal for driving the CRT display device, two frame memories each having a storage capacity corresponding to the data signal of one screen of the CRT display device are used. Once a data signal for a CRT display device is attached with a frame memory write address and written to one frame memory, the stored contents are shifted to the other frame memory, and the stored contents are read from the other frame memory and displayed on the LCD. It is conceivable to form a liquid crystal display drive signal that matches the display format, drive a liquid crystal display unit with this liquid crystal display drive signal, and display an image corresponding to the image on the CRT display. However, using two frame memories in this way is extremely disadvantageous in terms of cost.

[Purpose of the invention]

The present invention has been made in consideration of the above-mentioned problems. For example, it is possible to input various signals for driving a CRT display device output from a computer, etc., and display an image corresponding to the video signal. The purpose of this invention is to provide an inexpensive liquid crystal display device that requires only one frame memory.

[Structure of the invention]

In order to achieve the above object, the liquid crystal display device according to the present invention includes one frame memory having a storage capacity corresponding to the data signal of one screen of the CRT display device, and the above-described data signal for the CRT display device. data writing means for writing into the frame memory with a frame memory write address; data reading means for reading data from the frame memory; and liquid crystal display driving means for creating a signal for driving a liquid crystal display device from the read data. a liquid crystal display unit that inputs the liquid crystal display drive signal and displays an image corresponding to the image on the CRT display device; and a write/read switching means that alternately switches between writing and reading data in the frame memory. ,
Timing signal generating means for inputting horizontal and vertical synchronizing signals for driving a CRT display device and generating timing signals for controlling the operation timings of the data writing means, data reading means, liquid crystal display driving means, and writing/reading switching means. It is characterized by having the following.

A data signal for one screen of a CRT display device is temporarily stored in a frame memory by a data writing means. When writing of data to the frame memory is completed, the read switching means switches to a data read mode in which data from the frame memory can be read, and the data reading means reads the data from the frame memory. From the read data, the liquid crystal display driving means creates a liquid crystal display driving signal that matches the liquid crystal display format, and by inputting this liquid crystal display driving signal, an image corresponding to the image on the CRT display is generated. is displayed on the LCD display unit. Timing signals that control the operation timings of the data writing means, data reading means, liquid crystal display driving means, and writing/reading switching means are created by a timing signal creating means that inputs horizontal and vertical synchronizing signals for driving the CRT display device. .

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 5.

As shown in FIG. 1, this liquid crystal display device includes a horizontal/vertical timing signal and clock signal generation circuit 1, a frame memory writing circuit 2, a frame memory reading and liquid crystal display circuit 3, a frame memory circuit 4, It consists of a liquid crystal display unit 5.

As shown in FIG. 2, the horizontal/vertical timing signal and clock signal generating circuit 1 inputs a horizontal synchronizing signal Hsy+tc for driving a CRT display device (not shown) to control the operation of the frame memory writing circuit 2. The clock signal generating circuit 6 generates a clock signal C1ock, which is one of the signals to be used to write the frame memory. a horizontal timing signal generation circuit 7 that generates the horizontal timing signal HbLank; and the horizontal timing signal Hbllln.
k (!: Vertical timing signal generation circuit that inputs the vertical synchronization signal V 1ync for driving the CRT display device and generates the vertical timing signal Vb1mllk, which is one of the signals for controlling the operation of the frame memory writing circuit 2. 8, and a data creation circuit 9 which inputs the color video signals R, G, and B, combines them into one serial signal, and outputs the data as data Data whose relationship (delay time) with the frequency r of the clock signal C1ock is adjusted. Consists of.

The clock signal generation circuit 6 has an input voltage ■.

A voltage controlled oscillation circuit 12 whose oscillation frequency f0 changes in response to the level of Frequency divider circuit 13 and □, this 1/N frequency divider circuit 1
3 and the above-mentioned horizontal synchronization signal H9plIC are input and their phases are compared to detect the output frequency of the 1/N frequency divider 13, and therefore the delay/advance of the oscillation frequency f0 of the clock signal C1ock with respect to the horizontal synchronization signal H1VIIe. The phase comparison detection circuit 10 has a capacitor (not shown) that is charged and discharged by the delay/lead detection operation of the phase comparison detection circuit 10, and as a result of the charging and discharging, the oscillation frequency of the voltage controlled oscillation circuit 12 changes. The filter circuit 11 outputs a voltage vc whose level increases and decreases so that f0 is adjusted to a constant value. In this way, the oscillation frequency f0 of the voltage controlled oscillation circuit 12, which receives the voltage VC whose level goes up and down so as to adjust the oscillation frequency f0 of the voltage controlled oscillation circuit 12 to a constant value, is maintained at a desired frequency by feedback control. controlled by.

The frame memory write circuit 2 includes a frame memory write address counter circuit 1 as shown in FIG.
4, a frame memory write write signal and chip select signal generation circuit 15, and a basic clock generation circuit 16.
, a read/write switching signal generation circuit 17 , and a frame memory write data generation circuit 18 .

The frame memory write address counter circuit 14
inputs the horizontal timing signal HbLank, vertical timing signal VbLa11k and clock signal C1ock, outputs a frame memory write address signal,
In addition, necessary signals are provided to other frame memory write signal and chip select signal generation circuits 15, basic clock generation circuit 16, read/write switching signal generation circuit 17, and frame memory write data generation circuit 18 of frame memory write circuit 2. is configured to output. Also, these frame memory write signal and chip select signal generation circuit 15, basic clock generation circuit 16, read/write switching signal generation circuit 17, and frame memory write data generation circuit 18
is the frame memory write address counter circuit 14
Input the signal from C1ock and the clock signal C1ock,
Frame memory write write signal WR, chip select signal C3, basic clock signal Ck I, respectively.
It is configured to output a read/write switching signal and frame memory write data for writing screen data. The basic clock signal Ck is output to the frame memory readout and liquid crystal display circuit 3, and is used for writing other frame memory write address signals, frame memory write write signal WR, chip select signal C3, read/write switching signal, and screen data. The frame memory write data is output to the frame memory read and liquid crystal display circuit 3.

The frame memory readout and liquid crystal display circuit 3 includes a frame memory readout address generation circuit 19, a frame memory readout and chip select signal generation circuit 20, and a liquid crystal display unit display circuit 21, as shown in FIG.

The frame memory read address generation circuit 19 includes:
It is configured to input the basic clock signal Ck, generate a frame memory read address signal, and output necessary signals to the frame memory read and chip select signal generation circuit 20 and the liquid crystal display unit display circuit 21. . Further, the frame memory readout and chip select signal generation circuit 20 generates a frame memory readout read signal 10I for instructing data readout of the frame memory based on a signal from the frame memory readout address generation circuit 19, and a frame memory readout signal 10I for instructing data readout from the frame memory. It is configured to generate a chip select signal C8 that selects a chip within the frame memory. LCD display Uniso! - The display circuit 21 inputs the signal from the frame memory read address generation circuit 19, the basic clock signal Ck, and the data read from the frame memory circuit 4, and drives the liquid crystal display in accordance with the format for the liquid crystal display. signal for, i.e., synchronization signal for liquid crystal display,
It is configured to output serial data for liquid crystal display, data soft clock signal, and alternating current signal. The liquid crystal display unit 5 is driven by each signal for driving the liquid crystal display, and is configured to display an image corresponding to the image of the CRT display device.

The frame memory circuit 4 includes, as shown in FIG.
A frame memory read/write switching circuit 22 for control signals, a frame memory read/write switching circuit 23 for data, and a frame memory 24 are provided. The frame memory read/write switching circuit 22 inputs the read/write switching signal from the read/write switching memory generation circuit 17 of the frame memory writing circuit 2, and writes the control signal supplied to the frame memory 24 into the frame memory. Frame memory write address signal, frame memory write write signal WR, and thousand knob select signal C3 on the circuit 2 side, frame memory read address signal, frame memory read read signal 0. E and chip select signal C8. Further, the frame memory read/write switching circuit 23 for data inputs the read/write switching signal, and synchronizes with switching of the control command.
The data input/output terminal of the frame memory 24 is connected to and switched between the frame memory write data creation circuit 18 of the frame memory write circuit 2 and the liquid crystal display unit display circuit 21 of the frame memory read/write switching circuit 23. ing.

In the liquid crystal display device configured in this way, the frame memory writing circuit 2 outputs the horizontal and vertical synchronizing signals Hsync V 5sync and video signal R
, G, and B, and the data is sequentially written to the address of the frame memory 24 corresponding to the screen in synchronization with the frame memory write signal WR at a predetermined timing. on the other hand,
The data stored in the frame memory 24 is sequentially read out by the frame memory readout and liquid crystal display circuit 3 in synchronization with the frame memory readout read signal OE.
As one of the signals for driving the liquid crystal display that conforms to the format of the liquid crystal display, the liquid crystal display unit 5 is used as serial data for the liquid crystal display along with the liquid crystal display synchronization signal, data shift clock signal, and alternating current signal. is output to. The liquid crystal display unit 5 receives these signals and displays an image corresponding to the screen.

Read/write access to the frame memory 24 is as follows:
Switching is performed in a time-division manner, read access is performed between write accesses, the read data is launched, and the data is processed to match the format of the liquid crystal display and displayed on the liquid crystal display.

The present invention is not limited to the above-mentioned embodiments. For example, in this embodiment, by providing a synchronizing signal separating means at the front stage of the horizontal/vertical timing signal and clock signal generation circuit 1, a composite for a CRT display device can be produced. It is also possible to manually generate signals and display them on a liquid crystal display.

〔Effect of the invention〕

As described above, in the liquid crystal display device of the present invention, the data signal of one screen of the CRT display device is temporarily stored in the frame memory by the data writing means, and between the data writing to the frame memory, the data signal of one screen of the CRT display is stored by the data Elh outputting means. The data in the frame memory is read out, processed by the liquid crystal display driving means to suit the formano 1 for displaying the liquid level, and displayed on the liquid crystal display unit. Furthermore, the signals that control the timing of writing the data and creating signals that conform to the liquid crystal display format are all configured to be generated directly or indirectly from the synchronization signal for the CRT display device. . Therefore, according to the liquid crystal display device of the present invention, since the liquid crystal display can be performed by manually applying only the signal for driving the CRT display device, it is possible to use it in place of a CRT display device. Furthermore, since the liquid crystal display device of the present invention uses only one frame memory, it has the advantage of reducing manufacturing costs.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an outline of an embodiment of the present invention, FIG. 2 is a block diagram of its horizontal/vertical timing signal and clock signal generation circuit, and FIG. 3 is a block diagram of its frame memory writing circuit. FIG. 4 is a block diagram of the frame memory readout and liquid crystal display circuit, and FIG. 5 is a block diagram of the frame memory circuit. 2 is a horizontal/vertical timing signal and clock signal generation circuit, 2 is a frame memory write circuit, 3 is a frame memory readout and liquid crystal display unit drive circuit, 4 is a frame memory circuit, 5 is a liquid crystal display unit, and 6 is a clock signal generation circuit. , 7 is a horizontal timing signal generation circuit, 8 is a vertical timing signal generation circuit, 9 is a data generation circuit, 1
0 is a phase comparison detection circuit, 11 is a filter circuit, 12 is a voltage controlled oscillation circuit, 13 is a 1/N frequency divider circuit, 14 is a frame memory write address counter box, 15 is a frame memory write write signal and chip select signal generation circuit, 16 is the basic clock generation circuit, 17 is the read/write circuit.
Write switching signal generation circuit, 18 frame memory write data generation circuit, 19 frame memory read address generation circuit, 20 frame memory read and chip select signal generation circuit, 21 liquid crystal display unit display circuit, 22 frame memory read/write A switching circuit 23 is a frame memory read/write switching circuit, and 24 is a frame memory. Patent Applicant Sharp Corporation Figure 3 Figure 4rIA 5th! ! ! !

Claims (1)

[Claims] 1. One frame memory having a storage capacity corresponding to the data signal of one screen of the CRT display device, and data writing in which the data signal for the CRT display device is appended with the frame memory write address and written to the frame memory. a data reading means for reading data from the frame memory; a liquid crystal display driving means for creating a signal for driving a liquid crystal display from the read data; a liquid crystal display unit that displays an image corresponding to the image of the device;
write/read switching means for alternately switching between writing and reading data in the frame memory;
Timing signal creation means for inputting horizontal and vertical synchronization signals for driving the RT display device and creating timing signals for controlling the operation timings of the data writing means, data reading means, liquid crystal display driving means, and writing/reading switching means. A liquid crystal display device comprising: