JPS6162097A - Integrated circuit for dot display driving - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to an integrated circuit for driving a dot marker (IJ) display device, and in particular to an integrated circuit for driving a dot display that can be used by connecting a plurality of circuits in cascade. Regarding circuits.

(b) Conventional technology In general, when displaying characters or figures on a dot matrix display device using liquid crystal, for example, a large number of X-thin electrodes are sequentially selectively driven based on a well-known liquid crystal dynamic driving method. , In the selected state, drive signals for selection or non-selection are applied to a large number of Y thin electrodes. Here, the signals for driving the large number of Y-thin electrodes are created based on display information indicating lighting and non-lighting of a large number of dots connected to the currently selected X-thin electrode. A storage circuit is provided for supplying display information to a circuit that drives the display.

Conventionally, a memory circuit for storing display information was developed by Japanese Patent Publication No. 59-1
As shown in Japanese Patent No. 1916, a latch circuit or a parallel output shift register having a pit output equal to the number of Y thin electrodes is used, and the contents of the memory circuit are rewritten every time the selection state of the X thin electrodes changes. Therefore, a shift register is provided for receiving new display information from the outside and storing it until the next X-thin electrode is selected.

Then, the drive circuit for the Y-thin electrode, the memory circuit for storing display information, the shift register for storing display information for rewriting, etc., were integrated into an integrated circuit to create a circuit dedicated to driving the Y-thin electrode of the dot matrix (IJ) display device. IC has been realized.

(c) Problems to be solved by the invention (Dot matrix) using the IC dedicated to driving the Y thin electrode mentioned above.
When driving an IJ display device, if the number of Y fine electrodes of the display device is greater than the number of Y fine electrode drive outputs of the IC, the IC
In this case, if the ICs are connected in cascade and the shift registers of each IC are connected serially, display information is applied from one side, and the last IC
In order to shift up to 1, all the shift registers of each IC must be operated by a synchronizing signal. That is, if the number of Y thin electrodes of the display device is N, the number of operations of the shift register required to display the - row is N3, which has the drawback of increasing the power consumed by the shift register. Therefore, if the number of ICs used increases due to the larger screen of dot matrix display devices, the increase in power consumption will become noticeable, and the number of control terminal connections will also increase, leading to crosstalk with other signals and malfunctions. Cause.

B) Means for Solving the Problems The present invention has been made in view of the above-mentioned points, and includes a drive circuit that creates and outputs a dot drive signal, and a drive circuit that stores N pieces of display information. It is equipped with a storage circuit for supplying the data, a serial-to-parallel conversion circuit for converting display information serially applied from the outside into parallel data of a predetermined number of bits, and an accumulation circuit for sequentially accumulating display information for each converted parallel data. In the integrated circuit for driving dot display,
A control circuit that controls the storage operation of the storage circuit, detects that the storage circuit has stored N pieces of display information, and stops the operation of the serial-to-parallel conversion circuit and the storage circuit based on the detection output; and a control circuit that controls the storage circuit based on the detection output. The dot display driving integrated This reduces the power consumption of the circuit.

(E) Operation According to the above-described means, the display information applied serially is converted into parallel data by the serial-parallel conversion circuit based on the synchronizing signal, and is sequentially stored in the storage circuit.

Then, when N pieces of display information are stored in the storage circuit, the operation of the serial-to-parallel conversion circuit and the storage circuit is stopped by the detection output of the control signal. On the other hand, due to the sensing force, the applied display information is output to the outside from the output terminal via the gate circuit, and the synchronization signal is output again to the outside via the gate and output terminal, so the display information is output. using the terminal to which the synchronization signal is output and the terminal to which the synchronization signal is output.
This makes it possible to connect a large number of dot display driving integrated circuits in cascade. However, power consumption can be reduced.

(f) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention.
This is the case of a product circuit. In Figure 1, the liquid crystal drive circuit (
1) Outputs Y1 to Y capable of driving 80 Y thin electrodes of a display device. 4 applied externally.
The various voltages V t , V t , V s , V 4 are applied to 80 pieces of display information from the memory circuit (2), and a signal M is applied from the outside to indicate that the liquid crystal is an AC section. is selected based on and sent to outputs Y, to Y-0. The memory circuit (2) has respective outputs Y1 to Y. For example, 80
It consists of latch circuits. Also, memory circuit (2)
The storage operation is performed by the control signal C applied to the external terminal (3).
Controlled by LI, 80 pieces of display information stored in the storage circuit (4) are input and stored at once at the falling edge of the control signal CL1. Serial-parallel conversion circuit (5)
consists of a 4-bit shift register that can shift in both directions, and the 4-bit output of the shift register is sent to an accumulation circuit (4 bits).
), and is also applied to the serial-parallel conversion circuit (5
) is connected to the data input terminal (6) and (power).The shift direction of the serial-to-parallel conversion circuit (5) is controlled by the signal SHL applied to the external terminal (8). When applying display information to the Y-axis electrodes Y, Y, . ,
Y. When applying display information in the order of...Y, set the signal SHL to 1'' and input the display information from the data input terminal (6).The storage circuit (4) is connected to the serial-parallel conversion circuit (5). It sequentially stores the 4-bit output of ), the latch circuit is controlled by the latch clock output from the latch clock, ~L4 is the latch clock, and the latch circuit is controlled by the latch clock, ~L8 is the latch clock 2, ... latch circuit L?? ~L , . are sequentially controlled every 4 bits, such as 2-bit clock data, . Lip flop α1ll (hereinafter referred to as E-FF) and E-FF
(AND gate α which is controlled by the output Q of
When the control signal CLI falls, the operation starts and the AN
A 7-bit counter a3 counts the synchronizing signal CL2 output from the D gate α, and a latch clock inputs the upper five bits of the color/receiving signal a3 and latches based on the synchronizing signal CL2 and the signal SHL. It consists of a decoder α (a) that creates That is, the decoder θ(1
) to the latch clock synchronized with the synchronization signal CL2, ~
0. o is sequentially generated to control the storage circuit (4). At this time, when the signal SHL is 0'', the decoder α furnace 1, da, .

The latch clock is output in this order, but the signal SHL is “
1”, decoder a (a) is da, 01°...
Since the display information is output in the order of . . . , the order of storage in the storage circuit (4) is reversed, and in conjunction with the shift direction control of the serial-parallel conversion circuit (5), the order in which the display information is sent can be arbitrarily selected. In addition, the counter (13 inputs the synchronization signal CL2 by 8
When 0 pieces are counted, the display information in the storage circuit (4) is 80.
At this time, the counter 03) outputs ] as a detection output. In the detection output, I is usually "
It is a signal that becomes "0" after 80 counts at 1", and is applied to the reset terminal R of the E-FF system, the gate circuit system, and the AND gate αη via the inverter Q51. Therefore,
When the counter (13) counts 80 synchronizing signals CL2, the detection output CA resets E-FFa[and E
-FFQOI) AND by output Q″IO” Q2
) cuts off the synchronizing signal CL2, the operation of the counter 9 stops, and the serial counter operating with the synchronizing signal CL2
The operations of the parallel conversion circuit (5) and decoder C14) are stopped.

On the other hand, the gate circuit θe receives the signal SHL and the detection output CA1.
AND gate α1 which receives the data input terminal (6) as input (L mark, signal SHL, detection output CA, and data input terminal (7)), AND
The output of the gate circuit ae, that is, the output of the OR gate, is connected to the data output terminal 0D. Therefore, for example, when the signal SHL is set to '0', the data input terminal (7)
When the K display information is applied serially, if T is output as a detection output, the display information is AND gate staff and OR
Game) C! The data output terminal Qυ is also output to the outside via I. Furthermore, a synchronizing signal CL2 is applied to the AND gate surface to which the detection output CA is applied.
The output is connected to an external terminal Qz. Therefore, when the detection output CA is output, the synchronization signal CL2 is output from the external terminal (2) via the AND gate αη.

As described above, according to the embodiment shown in FIG. 1, the control circuit (9) is enabled to operate by the pulse of the control signal CLI, and display information and a synchronization signal can be applied. However, in this state, the gate circuit (161 and AN
D game) (17) is cut off, so display information and synchronization signal CL2 are not output from data output terminal 01) and external terminal (221).And when 80 display information and synchronization signal CL2 are applied, As a result of the detection output AK, the operation of the serial-parallel conversion circuit (5) and decoder I is stopped, and the storage circuit (4) stops its operation with 80 new pieces of display information stored.In this state, The display information applied to the data input terminal (7)K is outputted from the data output terminal f21) via the gate circuit clQ, and the synchronization signal CL2 applied to the input terminal α])K
It is also output from the external terminal via the AND game (17). Then, when all display information has been output, the display information stored in the storage circuit (4) is stored in the storage circuit (2) by the pulse of the control signal CLI.

FIG. 2 is a wiring diagram for driving a liquid crystal dot matrix display device with 240 Y-axis electrodes. In FIG. 2, 6M24 (C) is the dot of the embodiment shown in FIG. This is an integrated circuit for display driving. Each integrated circuit (231 (Foundation)
The terminal SHL in (c) is grounded, and the order in which display information is applied is on the left, that is, the output Y of the integrated circuit (c).

The display information is applied in order starting from the one corresponding to the first one. Therefore, DL is used as the data input terminal, and the terminal D of the integrated circuit (c)
L is connected to the display information output terminal DATA of the controller (E) that controls the display, and the data output terminal DOUT of the integrated circuit (C) is connected to the data input terminal DL of the integrated circuit.
Further, the data output terminal DOUT of the integrated circuit (C) is connected to the data input terminal DLK of the integrated circuit (C). Similarly, the synchronization signal input terminal CL2 of the integrated circuit (to) is connected to the output terminal CL2 of the controller (g) that outputs the synchronization signal CL2 synchronized with the output of display information, and the synchronization signal output terminal of the integrated circuit (c) The terminal CL20UT is connected to the synchronizing signal input terminal CL2 of the integrated circuit (2), and the synchronizing signal output terminal CL201]T of the integrated circuit (C) is connected to the synchronizing signal input terminal CL2 of the integrated circuit (C). In other words, regarding display information and synchronization signals, the integrated circuits (23) (c) are connected in cascade.In addition, the integrated circuits (c) (24
Each terminal M of @ is connected to an output terminal M of a controller (to) that outputs a signal M for AC driving the liquid crystal, and each control terminal CLI is connected to an output terminal M of a controller (4) that outputs a control signal CLI. Connected to terminal CLIK. That is,
Regarding the signal M and the control signal CLI, the integrated circuits (C) and (C) are connected in parallel.

The operation in the case shown in FIG. 2 will be explained with reference to the timing diagram in FIG. 3. In FIG. 3, signal M, control signal CLI, synchronization signal CL2 and display information serial output D
L is the output signal from the controller (A), signals A (NOI), I (NO2), and τ (NO3) are the detection outputs of each counter (13) of the integrated circuit (C) and O4 (C). , signal DOUT(No1), DOUT(No2), D
OUT (NO3) and CL20UT (NOI), CL2
0UT (NO2) and CL20UT (NO3) are signals output from the output terminals DOUT and CL2 of the integrated circuit cMl)QB, respectively.

From the rising edge K of the pulse of the control signal CLI, each Σ-FFQI of the integrated circuit (C) (C) (Fund) (C) is set, and 6
force, fy ylti3f) detection output A (Not), A (N02), A (NO3) becomes 11", and each control circuit (9) becomes operational, but the voltage applied to the integrated circuit @ Serial output D of synchronization signal CL2 and display information
Since L is a detection output and is not output to the next stage than A (NOI) K, the integrated circuit (to) stores the display information in the storage circuit (4) by the synchronization signal CL2, but the integrated circuit (to) stores the display information in the storage circuit (4). ) remains operational. Then, when the integrated circuit (to) accumulates 80 pieces of display information,
Since the detection output (ACNOI) becomes Io'' in synchronization with the fall of the synchronization signal CL2, the integrated circuit (to) stops operating while holding the 80 pieces of display information in the storage circuit (4).・Display information and synchronization signal CL2 from the 81st unit are output terminals DOUT and CI of the integrated circuit (c),
20UT, the integrated circuit starts storing display information. Then, when the integrated circuit accumulates 80 pieces of display information, the detection output is τ(NO
2) becomes 0'', and the integrated circuit stops operating while holding the 80 pieces of display information. Therefore, the display information from the 161st piece and the synchronization signal CL2 are output from the integrated circuit (2). Therefore, the integrated circuit (c) starts an operation of accumulating display information.

In this way, when a total of 240 pieces of display information and synchronization signal CL2 are output, the controller (20 is the control signal C
Outputs LI pulse. With the rising edge of the control signal CLI, each E-FFQOJ is set as described above, and the control circuit (9) becomes operational, and with the falling edge of the control signal CLI, the integrated circuit (23+(
24) CI! The 80 pieces of display information stored in the storage circuit (4) of (2) are stored in the storage circuit (2) and are stored in the drive circuit (1).
) is applied to By performing the above operation 64 times, for example, the number of X moving electrodes in an IJ display device, the X moving electrode is driven for one selection cycle, that is, for one screen (one frame). . Furthermore, in the next frame, the signal M is set to ``0'' and the same operation is performed, resulting in AC driving of the liquid crystal.

(G) Effects of the Invention As described above, according to the present invention, a plurality of dot display driving integrated circuits can be connected in cascade regarding display information and synchronization signals, so that the wiring between the integrated circuits can be shortened.
Since the number of wires connected to each integrated circuit is also reduced, it is possible to eliminate the effects of noise and crosstalk.Furthermore, only the integrated circuit that stores display information performs operations such as shifting, and other Since the operation of the integrated circuit is stopped, it has the advantage of significantly reducing power consumption, and the effect is particularly remarkable when a large number of integrated circuits are used to operate at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a wiring diagram when a plurality of dot display driving integrated circuits shown in FIG. 1 are used, and FIG. FIG. 3 is a timing diagram showing the operation of the connection diagram. Explanation of main drawing numbers (1)...Liquid crystal drive circuit, (2)...Memory circuit,
(4)...Storage circuit, (5)...Serial-parallel conversion circuit, (3>(6)+71(8)(11>(
21) (221...external terminal, (9)-4171
1 control circuit, fi7)-A N D gate, (16)・
& −) circuit, (23)(24)(,!5)...
Dot display driving integrated circuit, (26)...controller.

Claims (1)

[Claims] 1. A drive circuit that generates and outputs N drive signals for driving the dots of a dot matrix display device, and a display information storage circuit that stores N pieces of display information indicating lighting and non-lighting of dots and supplies them to the drive circuit. In an integrated circuit for driving a dot display, the integrated circuit is equipped with an accumulation circuit that sequentially stores display information serially applied from the outside in predetermined bits based on a synchronization signal applied in synchronization with the display information. , controls the display information storage operation of the storage circuit by counting the synchronization signal, detects that the storage circuit has stored N pieces of display information, and stops the operation of the storage circuit based on the detection output. a control circuit; a gate circuit that is controlled by a detection output output from the control circuit and outputs display information serially applied from the outside from an output terminal; and a gate circuit that outputs the synchronization signal applied from the outside to the outside again. 1. An integrated circuit for driving a dot display, characterized in that it is provided with a gate and an output terminal for the purpose of driving the dot display.