JPS60247745A - Interruption control circuit - Google Patents

Abstract

PURPOSE:To make a response time constant and improve timing accuracy, and expand an application range by performing counting operation in every instruction cycle at a request for interruption and accepting the interruption when the counted value attains to a specific value. CONSTITUTION:A request flag 2 is set in synchronism with the rising of an interruption request signal IRQ and its output signal IF goes up to ''1'', and a counter 3 in the reset state is actuated to count up by one for every machine cycle. When the specific number of machine cycles from the start of counting to the acceptance of interruption is set to ''8'', instructions being executed at present are executed continuously and automatically up to a final state even if an input for an instruction decoder 9 varies. Then when the counter counts up to the specific value ''8'', the output CMP of a comparator 5 goes up to ''1'' and a gate 7 is opened to output an interruption acceptance request signal IN=1, so that a decoder 9 starts accepting the interruption. At this time, any instruction code is disregarded even if inputted to the decoder 9, and an interruption ACK signal is generated to reset the flag 2, thus completing a series of interruption processes.

Description

[Detailed Description of the Invention] Industrial Field of Application The present invention relates to an interrupt control circuit for a single-chip microcomputer. ○Conventional configuration and its problems Field of application of a single-chip microcomputer (hereinafter referred to as microcomputer) Among these, when used as a microcontroller, real-time responsiveness is important.

An interrupt processing function is provided to improve real-time responsiveness. Considering the original purpose of the interrupt function, it is necessary to immediately interrupt the work currently being executed and transfer control to the execution of the interrupt processing program. Even if it is called prompt, it is difficult to interrupt a command currently being executed. Therefore, microcomputers that accept interrupts after executing the currently executing instruction are common.

When real-time control is performed using a microcomputer, control tolerances may be required in microsecond units. For example, when generating an interrupt using a zero-crossing signal from a commercial power source and controlling the pulse width of a load current, variations in interrupt response time directly affect control accuracy. In the case of a microcomputer that accepts interrupts on an instruction-by-instruction basis, variations in instruction execution time are reflected in variations in interrupt acceptance response times.

FIG. 1 shows the conventional microcomputer interrupt acceptance timing.

IRQ is an interrupt request signal, a and b indicate instruction execution, and MOV (data transfer).

It shows the timing at which MUL (multiplication), AND (logical product) instructions, etc. are executed.

In the example a, the MUL instruction is being executed when the interrupt occurs, and in the example b, the AND instruction is being executed. As is clear from the examples a and b, the time from interrupt generation to interrupt acceptance changes depending on the type of instruction or the difference in execution state position of the same instruction.

Microcontroller instructions range from those that can be executed in one instruction cycle to those that require about 10 instruction cycles, such as operations between registers, and the disadvantage is that the difference in execution time for each instruction affects the variation in interrupt acceptance time. was there.

Purpose of the Invention Therefore, the present invention provides a circuit that makes the time from interrupt generation to acceptance constant in a microcomputer, which has a different execution speed for each instruction, and improves the control accuracy of microcomputer applications that perform timing control using interrupt-driven programs. The purpose is to raise the

Structure of the Invention In order to make the time from interrupt generation to acceptance a constant time, when one interrupt request occurs, a counter that counts every instruction cycle is started, and the output value of the counter is set to a specified value. This is an interrupt control circuit configured to check whether the specified value has been reached every cycle, and to accept the interrupt when the specified value is reached.After the execution of the instruction that was being executed when the interrupt occurred, the CPU The acceptance wait cycle is repeated until the counter reaches the specified value. The specified value of this counter is set to the number of instruction cycles that require the longest execution time.

Description of examples Hereinafter, details will be explained based on one embodiment of the present invention.

FIG. 2 is an interrupt acceptance timing diagram in this embodiment. Note that in the figure, IRQ is an interrupt request signal, and a and b indicate instruction execution. MOv (transfer),
MUL (multiplication).

A state in which AND (logical product), W (wait cycle) 1 interrupt acceptance, etc. are executed is shown.

The microcontroller in this embodiment takes 8 machine cycles for the MUL instruction and 3 machine cycles for the AND instruction.

The MOV instruction requires an execution time of 1c2 machine cycles.

First, in the execution example a, a case is shown in which the interrupt request signal IRQ is generated in the second machine cycle after the start of execution of the MUL instruction. A counter is activated upon occurrence of an interrupt, and when the counter value indicates 7, the MUL instruction that has been in the middle of execution is completed. After this, the CPU wait cycle is repeated until the count value reaches 8 without starting to accept the interrupt immediately.

Next, in the execution example b, a case is shown in which an interrupt occurs in the second machine cycle of an AND instruction. Unlike case a, the wait for 6 machine cycles is repeated while the count value is between 2 and 8.

That is, in the case of an instruction that finishes execution early, the delay time until interrupt acceptance is controlled to be constant during execution of any type of instruction by repeating many wait cycles.

FIG. 3 is a block diagram of the embodiment.

1 is a terminal for applying an interrupt request signal from outside the microcomputer. 2 is a flag for detecting an interrupt, which is set in synchronization with the rising edge of the interrupt request signal IRQ from the terminal 1, and is set in the output signal IF-1. 3 is a counter, which counts one in one instruction cycle. The counter 3 is reset when the output signal of the flag 2 is IF-0. 4 is a register that stores a specified value;
Can be set by command. In this explanation, the operation when 8 is set is shown. A comparator 5 compares the output Q of the counter 3 and the output P of the register 4, and outputs a match signal CMP when P and Q match. 6
is a gate, which opens when the output IF of the flag 2 is 1 and the comparator output CMP is 0, and is set to the interrupt acceptance wait request signal WAIT=1. A gate 7 is opened when the output IF of the flag 2 is 1 and the output CMP of the comparator is 1, and the interrupt acceptance request signal INT is set to 1. 8 is a 2→1 multiplexer. When executing a normal instruction, the mouth side is opened and the value of the instruction register is input to the instruction decoder. When waiting for interrupt acceptance, the output WAIT of the gate 6 is 1, so the A side is opened and the wait code is input to the instruction decoder.

Reference numeral 9 denotes an instruction decoder, which decodes instructions and interrupt acceptance codes. One ACK of the instruction decoder output signal
The flag 2 is cleared by the signal.

The operation of the interrupt control circuit of this embodiment configured as described above will be explained below.

FIG. 4 is a timing diagram for explaining the details of the operation of this embodiment.

Interrupt request flag 2 is set in synchronization with the rising edge of interrupt request signal IRQ, and F=1. Then,
Counter 3, which has been in a reset state until now, is activated and performs one count per machine cycle.

If the specified machine cycle from the start of counting to the acceptance of an interrupt is set to 8, the output WA of comparator 6
The IT signal is initially 0. During this time, the multiplexer 8 selects the i side, thereby instructing the instruction decoder 9 to execute a wait cycle. Therefore, when the currently executed instruction ends, a wait cycle is executed. An instruction that is currently being executed is automatically continued to the final state of the instruction even if the input to the instruction decoder 9 changes.

When the counter reaches the specified value of 8, the output of the comparator 5 becomes CMP=1, the gate 7 opens, an interrupt acceptance request signal NT=1 is output, and the instruction decoder 9 starts accepting the interrupt. At this time, any instruction code input to the instruction decoder is ignored. In the interrupt acceptance cycle, an interrupt ACK signal is generated, flag 2 is cleared, and a series of interrupt processing is completed.

In the above explanation, since the instruction that takes the most time is the MUL instruction, the specified value is determined to be 8 and written to the register 4.

However, if the maximum number of instructions used in an application program is 5 machine cycles, register 4 is set to 6.

Furthermore, if the time from generation to acceptance of an interrupt does not need to be constant, writing 0 to the register 4 can cause the microcomputer to operate in the same way as a conventional microcomputer.

Effects of the Invention By having the configuration as described above, the present invention can make the response time from interrupt occurrence to acceptance constant, and is suitable for applications where the timing of a microcomputer application system is controlled by an interrupt-driven program. It has great practical value, as it can improve timing accuracy and expand the scope of application to areas that could not be achieved with modern microcontrollers.

[Brief explanation of drawings]

Figure 1 is a conventional interrupt reception timing diagram, Figure 2 is an interrupt reception timing diagram of an embodiment of the present invention, Figure 3 is a block diagram showing the configuration of the embodiment, and Figure 4 is the operation of the embodiment. FIG. 1... Interrupt terminal, 2... Interrupt request flag, 3... Counter, 4, 5...
Gate, 6...Multiplexer, 7...
・Instruction decoder. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3

Claims (1)

[Claims] a terminal for providing an interrupt request signal; a flag for interrupt detection that is set by a pulse signal applied to the terminal;
A counter that starts counting after the flag is set, a comparison detection means that detects a state in which the output value of the counter has not reached a specified value and outputs a standby request signal for accepting an interrupt, and an instruction code and an interrupt. An interrupt control circuit comprising: an instruction decoder for decoding an acceptance code; and means for inserting a wait cycle for causing the instruction decoder to wait for interrupt acceptance based on the output of the comparison detection means.