JPS61154491A - Motor controller - Google Patents

Abstract

PURPOSE:To eliminate the sampling delay between speed and current controls by providing two counters, controlling the speed at every pulse of the first counter, and controlling the current at every pulse of the second counter. CONSTITUTION:The first counter 2 for generating an interrupt pulse at every prescribed time T1 and the second counter 3 started by the first counter 3 for generating an interrupt pulse after a time T2 equal to the all executing time of a speed control program are provided in a digital controller for controlling the current and the speed. The speed is controlled at every interrupt pulse generation from the counter 2 or integer times thereof, and the current is controlled at every interrupt pulse from the counter 3 to eliminate the delay of sampling between the speed control and the current control, and the sampling interval of the speed and current controls is set to be constant to improve the controlling performance.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a motor control device that controls the speed and current of a motor using a digital control device such as a microphone computer. 4 through 4 are timing waveform diagrams for explaining conventional examples of such control systems.

In Fig. 2, (A) and (0) respectively indicate interrupt pulses A and B for the digital control device, and these separate pulses A and B control the current as shown in (C) and (=). , speed control is performed. In this case, since the pulses A and B are issued asynchronously with each other, the current control program and the speed control program are executed asynchronously with each other. Also, this is an example where the execution level of the current control program is higher. Therefore, when pulse A is issued while speed control is being performed using pulse BK, the speed control program will be changed to t in the same figure, for example. The time indicated by is interrupted, and the execution of the current control program is made to wait until the end of the current control program.

FIG. 3 shows an example in which speed control and current control are executed synchronously. In response to an interrupt pulse CK as shown in (a) in the figure, current control is first performed as shown in (b), and then (
Speed control is performed as shown in c).

#! Figure 4 is also an example of a case where speed control and current control are performed synchronously. In this case, when a normal current control program is executed and a speed control program is also executed, speed control is performed first, and then current control is performed. It is for controlling.

[Problem that the invention seeks to solve]

According to the method shown in Figure 2, a) there is a delay between speed control and current control due to sampling, and the value changes (time t in the figure).
□, 1. , 1. reference).

口) The sampling interval for speed control is undefined (
(See time t4 in the figure).

These problems cause the performance of the control device to deteriorate.

On the other hand, in the method shown in Figure 3, between speed control and current control,
There is a problem that a certain sampling delay occurs as shown by t in the figure, and the method shown in Figure 4 also has a problem that the sampling interval for current control is not constant◇ [To solve the problem ] A first means for generating an interrupt pulse at fixed time intervals T1 in a digital control device that performs at least current control and speed control.
and a 20th counter that is activated by this first counter and generates an interrupt pulse after a time equal to the total execution time of the speed control program (known in advance) T2.
A counter is provided.

[Effect]

The digital control device performs speed control every time an interrupt pulse is generated from the first counter or every integer multiple thereof, and current control is performed every time an interrupt pulse is generated from the second counter, thereby controlling sampling between speed control and current control. To improve control performance by eliminating delays and keeping sampling intervals of speed control and current control constant.

[Embodiments of the invention]

FIG. 1 is a configuration diagram showing an embodiment of the present invention, and FIG. 1A is a timing waveform diagram for explaining its operation.

As is clear from FIG. 1, this embodiment.

For example, a digital control device 1 consisting of a microcomputer etc. has two interrupt pulse generation counters 2.
, 3 are added.

Now, when the clock CL is given from the digital control device 1 to the counter 23, the first counter 2 generates an interrupt pulse signal as shown in FIG. 1A (a) to the digital control device 1, and the 20th counter An interrupt pulse and a clear signal IN1, which serve as a clear signal, are output to the 20th counter 3, and the 20th counter 3
For this, an interrupt pulse signal IN2 as shown in the diagram (b) is applied. That is, the counter value CT1 corresponding to the sampling time T1 for current control and the counter value CT2 corresponding to the execution time T2 of the speed control program are sent to the microprocessor 1 via an external setting device or data bus t. counter 2. Since the time T is given to the 20th counter 3, the first counter 2
Outputs an interrupt pulse and clear signal INI for each INI,
The second counter 3 starts a counting operation upon receiving the signal INI, and generates an interrupt pulse IN2 after time T2 has elapsed. From this K, the digital control device 1 outputs the signal IN.
Every time I is taken or an integer multiple thereof, the fAIN(c)
While executing the speed control program as in
Each time the receiver receives the light, it executes the light control program as shown in Figure (d).

〔Effect of the invention〕

In a digital control device that is composed of a microcomputer and controls the rotational speed of an electric motor, two force and counters are added, and speed control is executed for each fixed interval pulse generated by the 10th counter or for each integral multiple thereof. , 10th
Since current control is performed for each pulse generated from the 20th counter after the pulse of the counter starts and the execution time of the speed control program has elapsed, the sampling interval of speed control and current control remains unchanged. This brings about the advantage of being able to eliminate sampling delays between controls.

[Brief explanation of drawings]

@ Figure 1 is a configuration diagram showing an embodiment of the present invention, Figure 1A is a timing waveform diagram for explaining its operation, and Figures 2 to 4 are diagrams for explaining conventional examples of motor control systems. It is a timing waveform diagram. Description of symbols 1...Digital control device, 2...First counter, 3...Second counter, CL...
... Clock signal, INI ... Interrupt and clear signal, IN2 ... Interrupt signal. Agent Patent Attorney Akio Namiki Agent Patent Attorney Seiki Matsuzaki 1 Zurikan IAII

Claims (1)

[Scope of Claims] 1) A digital control device, a first counter that generates a first interrupt pulse to the control device at predetermined time intervals, and a counter that is activated every time the first interrupt pulse is generated and a predetermined time has elapsed since then; a second counter that later generates a second interrupt pulse to the control device, and the control device performs speed control every time the first interrupt pulse is generated or every integral multiple thereof;
A motor control device characterized in that current control is performed every time the second interrupt pulse is generated. 2) In the motor control device according to claim 1, the time from when the second counter is activated to when the second interrupt pulse is generated corresponds to the total calculation execution time for speed control. An electric motor control device characterized by: