JP4156148B2 - Task scheduling device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a task scheduling device having a multitasking function and a task switching method.
[0002]
[Prior art]
In a microcontroller having a multitasking function, when a single processor is used, one task is selected from a plurality of tasks, and the selected task is executed by the processor.
[0003]
When trying to control multiple hardware engines with different number of processing cycles by multitasking, associate multiple tasks with each of the multiple hardware engines, and switch the task when the hardware engine execution process is completed. It is.
[0004]
[Problems to be solved by the invention]
However, in the above-described conventional microcontroller, task switching is performed upon completion of execution of the hardware engine, so it is very difficult to control the timing at which task switching occurs from the microcontroller program.
[0005]
For this reason, a controller using multitasking has a problem that it takes time to develop a hardware function test and program depending on task switching timing.
[0006]
An object of the present invention is to solve the above-described conventional problems, and to provide a task scheduling apparatus and a task switching method that can easily perform task switching timing control.
[0007]
[Means for Solving the Problems]
In order to achieve this object, the task scheduling apparatus of the present invention has a configuration in which a mechanism for switching tasks occurs after the number of cycles set by an instruction.
[0008]
That is, the task scheduling apparatus of the present invention has a microcontroller that selects one task from a plurality of tasks and executes it sequentially, and performs task switching after a predetermined cycle when an instruction is issued in the task being executed. Features.
[0009]
The task switching method of the present invention includes a first step of designating a set value by an instruction in a task being executed, a second step of counting a value, the counted value, and the set value. And a fourth step of selecting a task to be executed next. In the third step, the task switching is performed when the counted value is equal to the set value. It is generated.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0011]
(Embodiment 1)
FIG. 1 shows the configuration of a task scheduling apparatus according to Embodiment 1 of the present invention.
[0012]
In FIG. 1, reference numeral 101 denotes a processor, which decodes a task program and executes an instruction.
[0013]
Reference numerals 120 to 122 denote hardware engines 0, 1, and 2, which are activated by activation signals 130, 131, and 132 from the processor 101, start the respective processing executions, and when the processing is completed, end signals 140, 141, and 142. Is generated.
[0014]
A scheduler 102 selects a task when switching tasks.
Reference numerals 110, 111, and 112 denote tasks 0, 1, and 2, and information such as how far the program has been executed for each task is saved.
[0015]
Reference numeral 103 denotes a counter. Counting is started by an instruction 134 from the processor 101, and the count value is output as a counter output 135.
[0016]
A comparator 104 compares the counter output 135 with a predetermined value, and outputs the result as a comparison output 136.
[0017]
Reference numeral 105 denotes a logical sum, which generates a logical sum of the end signals 140 to 142 and the comparison output 136 and outputs it as a task switching signal 137.
[0018]
With respect to the present embodiment configured as described above, the operation at the time of task switching will be described below.
[0019]
It is assumed that task 0 is executed in processor 101 and instruction 134 is issued by the task 0 program.
[0020]
In the counter 103, when the instruction 134 is issued, 0 is incremented to 0, 1, 2, 3,... Every cycle with 0 as an initial value, and this is output as the counter output 135.
[0021]
In the comparator 104, when the counter output 135 is input, it is compared with a predetermined value, for example, “10”.
[0022]
When the counter output 135 is not “10”, “0” is output as the comparison output 136. When the counter output 135 is “10”, “1” is output as the comparison output 136. The comparison output 136 is a logical sum 105 and is logically combined with the end signals 140 to 142, and a task switching signal 137 is generated.
[0023]
In the scheduler 102, when the task switching signal 137 is input, the execution position on the program of the task 0 that has been executed so far is saved in the task 0 (110), and the task to be executed next is selected.
[0024]
For example, if task 1 is selected, the execution position of task 1 saved in task 1 (111) is sent to the processor, and program execution of task 1 is started.
[0025]
As described above, according to the present embodiment, task switching can occur after a predetermined value “10” cycles from the issue of the instruction described in task 0.
[0026]
(Embodiment 2)
FIG. 2 shows a configuration of a task scheduling apparatus according to the second embodiment of the present invention.
[0027]
In FIG. 2, reference numeral 203 denotes a counter. When an initial count is set by an initial value setting command 234 from the processor 101, the count is started, and the count value is output as a counter output 235.
[0028]
A comparator 104 compares the counter output 235 with a predetermined value and outputs the result as a comparison output 236.
[0029]
With respect to the present embodiment configured as described above, the operation at the time of task switching will be described below.
[0030]
It is assumed that task 0 is executed in processor 101 and initial value setting instruction 234 is issued by the task 0 program.
[0031]
When the initial value setting command 234 is issued, the counter 203 decrements every cycle using the value specified by the initial value setting command 234 as the initial value.
[0032]
For example, when the initial value is “10”, decrementing is performed every cycle as 10, 9, 8, 7,..., And it is output as the counter output 235.
[0033]
When the counter output 235 is input to the comparator 204, it is compared with a predetermined value, for example, “0”.
[0034]
When the counter output 235 is not “0”, “0” is output as the comparison output 236. When the counter output 235 is “0”, “1” is output as the comparison output 236. Thereafter, similarly, a task switching signal 137 is generated and task switching is performed.
[0035]
As described above, task switching can be generated after a set cycle by an instruction described in task 0.
[0036]
(Embodiment 3)
FIG. 3 shows a configuration of a task scheduling apparatus according to the third embodiment of the present invention.
[0037]
In FIG. 3, reference numeral 322 denotes a hardware engine 3, which is activated by an activation signal 334 from the processor 101, starts executing each process, and generates an end signal 343 when the process ends.
[0038]
In the logical sum 105, a logical sum of the end signal 343 and the end signals 140 to 142 is generated and output as the task switching signal 107.
[0039]
With respect to the present embodiment configured as described above, the operation at the time of task switching will be described below.
[0040]
It is assumed that task 0 is executed in the processor 101 and a start command for the hardware engine 3 is issued by the task 0 program.
[0041]
When an activation command for the hardware engine 3 is issued, an activation signal 3 (334) is generated, and at the same time, a counter initial value is sent to the hardware engine 3 (322).
[0042]
The hardware engine 3 (322) decrements every cycle from the sent counter initial value, and when the count value is “0”, an end signal 3 (343) is generated. Thereafter, similarly, a task switching signal 107 is generated and task switching is performed.
[0043]
As described above, task switching can occur after the cycle set by the instruction described in task 0.
[0044]
(Embodiment 4)
FIG. 4 is a flowchart of the task switching method according to the fourth embodiment of the present invention.
[0045]
In FIG. 4, in the first step S1, a set value is designated by an instruction in the program of the task being executed. This set value specifies the number of cycles from when an instruction is issued until task switching is performed.
[0046]
In the second step S2, counting is started. The initial value of the count is “0”, and the count value is incremented every cycle.
[0047]
In the third step S3, the set value designated in the first step S1 is compared with the count value counted in the second step.
[0048]
If the set value is not equal to the count value, the process returns to the second step S2. If the set value is equal to the count value, the process proceeds to the fourth step S4.
[0049]
In the fourth step S4, a task to be executed next is selected.
[0050]
As described above, according to this embodiment, task switching can occur after a cycle set by an instruction described in a task being executed.
[0051]
【The invention's effect】
According to the present invention, task switching timing control can be easily performed by providing a mechanism for generating task switching after the number of cycles set by an instruction.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a task scheduling apparatus according to a first embodiment of the present invention. FIG. 2 is a block diagram illustrating a task scheduling apparatus according to a second embodiment of the present invention. FIG. 4 is a block diagram showing a task scheduling apparatus. FIG. 4 is a flowchart of a task switching method according to the fourth embodiment of the present invention.
100 Microcontroller 101 Processor 102 Scheduler 103 Counter 104 Comparator 105 Logical sum 110 Task 0
111 Task 1
112 Task 2
120 Hardware engine 0
121 Hardware engine 1
122 Hardware Engine 2
130 Start signal 0
131 Start signal 1
132 Start signal 2
134 Command 135 Counter output 136 Comparison output 137 Task switching signal 140 End signal 0
141 End signal 1
142 End signal 2
203 Counter 204 Comparator 234 Initial value setting instruction 235 Counter output 236 Comparison output 322 Hardware engine 3
334 Start signal 3
343 End signal 3

Claims (2)

Select one task from a plurality of tasks, comprising a microcontroller for executing sequentially, a execution process of the task is completed the task scheduling apparatus for performing e replacement task cutting,
When a specific instruction is issued in a task being executed , task switching is performed after a predetermined cycle from the issuance of the specific instruction, even if task execution processing has not ended , and the predetermined number of cycles is set by the specific instruction A task scheduling apparatus. Select one task from a plurality of tasks, the execution of the task is completed, a switching method of the task to be performed by switching a task, the particular instruction by the task, the particular instruction issued The first step of designating the number of cycles from the start to task switching as a set value, the second step of counting the value as a count value every cycle, and the second step A third step of comparing the count value with the set value specified in the first step, and a fourth step of selecting a task to be executed next,
In the third step, when the count value is equal to the set value, task switching is generated even if the task execution processing is not completed .

Images