JPS60242647A - Mounting method of hybrid integrated circuit - Google Patents

Mounting method of hybrid integrated circuit

Info

Publication number
JPS60242647A
JPS60242647A JP9983684A JP9983684A JPS60242647A JP S60242647 A JPS60242647 A JP S60242647A JP 9983684 A JP9983684 A JP 9983684A JP 9983684 A JP9983684 A JP 9983684A JP S60242647 A JPS60242647 A JP S60242647A
Authority
JP
Japan
Prior art keywords
integrated circuit
synthetic resin
substrate
hybrid integrated
welding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9983684A
Other languages
Japanese (ja)
Inventor
Hajime Kato
肇 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9983684A priority Critical patent/JPS60242647A/en
Publication of JPS60242647A publication Critical patent/JPS60242647A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To prevent leakage or short-circuit on a substrate, by injecting gel insulating synthetic resin so as to cover a hybrid integrated circuit substrate housed in a hollow package and connecting the upper portions of lead lines raised from said substrate with connecting pieces by means of welding. CONSTITUTION:A substrate 1, on which electronic parts such as a semiconductor chip 3 and a chip capacitor 4 are mounted and from which a plurality of lead lines 5 are raised, is bonded to a heat sink 2. Gel insulating synthetic resin is injected from a lead hole 6a to cover the substrate 1 and is cured to form a synthetic resin layer 11. Then, each lead line is connected by welding with each connecting piece 8. Electricaly conductive metallic powder 9 is produced by this welding, and the powder 9 falling within the frame 6 is adhered onto the synthetic resin layer 11. Accordingly, the electronic parts on the substrate 1 can be effectively prevented from accidents such as short circuit or the like.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、中空パッケージ内に混成集積回路基板を収
容し、この基板から上方に引出されたリード線に外端端
子の接続片を溶接接続する、混成集積回路の実装方法に
関する。[Detailed Description of the Invention] [Technical Field of the Invention] This invention accommodates a hybrid integrated circuit board in a hollow package, and connects a connecting piece of an outer terminal by welding to a lead wire drawn upward from the board. , relates to a method for implementing hybrid integrated circuits.

〔従来技術〕[Prior art]

従来のこの種の混成集積回路の実装は、第１図及び第２
図に混成集積回路装置の平面図及び断面図で示すように
していた。（１）は厚膜基板などからなる混成集積回路
基板（以下「基板」と称する）。Conventional implementations of this type of hybrid integrated circuit are shown in Figures 1 and 2.
The figure shows a plan view and a sectional view of a hybrid integrated circuit device. (1) is a hybrid integrated circuit board (hereinafter referred to as "substrate") consisting of a thick film substrate or the like.

（２）はアルミ材など機械的強度が高く良熱伝導性の金
属材からなるヒートシンクで、基板（１）を接着支持し
ている。基板（１）上には半導体チップ（３）、チップ
コンデンサ（４）など電子部品が装着され、リード線（
５）が上方に引出されている。（６）はエポキシ系樹脂
など合成樹脂成形品からなるフレームで、ヒートシンク
【２）上の周囲に接着剤により接着されている。（６ａ
）は吹付は用穴、（６ｂ）はリード用穴である。(2) is a heat sink made of a metal material with high mechanical strength and good thermal conductivity, such as aluminum, which adhesively supports the substrate (1). Electronic components such as a semiconductor chip (3) and a chip capacitor (4) are mounted on the board (1), and lead wires (
5) is pulled upward. (6) is a frame made of a synthetic resin molded product such as epoxy resin, and is bonded around the heat sink (2) with adhesive. (6a
) is a hole for spraying, and (6b) is a hole for lead.

（６ｃ）は突起部で、この内側にコンデンサなどが装着
される。（７）はフレーム（３）に固着され引出された
外部端子、（８）は外部端子（７）に一端が接続された
接続片で、立上り辺が上記リード線（５）に溶接接続さ
れている。この突出した各リード線（５）及び各接続片
（８）及びリード用穴部は、ゴムキャップαＯがかぶせ
られ、封鎖される。(6c) is a protrusion, inside of which a capacitor or the like is mounted. (7) is an external terminal fixed to the frame (3) and pulled out; (8) is a connection piece with one end connected to the external terminal (7), and the rising side is welded to the lead wire (5). There is. Each of the protruding lead wires (5), each connection piece (8), and the lead hole are covered with a rubber cap αO and sealed.

リード線（５）と接続片（８）との接合は、はんだ付け
やラッピング法などがあるが、耐環境上高信頼度を要す
る場合、はんだ付は及び溶接によることが多い。車輛用
彦ど周囲温度が高く、振動のある環境で使用される場合
、確実な溶接接続が採用される。The lead wire (5) and the connecting piece (8) can be joined by soldering, wrapping, etc., but if high reliability is required in terms of environmental resistance, soldering or welding is often used. When vehicles are used in environments with high ambient temperatures and vibrations, reliable welded connections are used.

この溶接接続では、はんだ付けの場合のように使用フラ
ックスの洗浄などを要せず、作業性がよく簡単であり、
自動化が容易にできる利点がある。Unlike soldering, this welded connection does not require cleaning of the flux used, and is easy to work with.
It has the advantage of being easily automated.

しかし、拵２図のように中空パッケージの場合。However, in the case of a hollow package like Koshirae 2 diagram.

リード線（５）と接続片（８）とを溶接すると、導電性
の金属粉（９）が生じ、この一部が基板（１）上に落ち
て付着し、漏電や短絡となるおそれがあり、信頼性がよ
くなかった。When welding the lead wire (5) and the connection piece (8), conductive metal powder (9) will be generated, and some of this may fall and adhere to the board (1), resulting in electrical leakage or short circuit. , reliability was not good.

〔発明の概要〕[Summary of the invention]

この発明は、上記従来の実装方法の欠点をなくするため
になされたもので、電子部品が装着されリード線が立上
げられ、中空パッケージ内に収容された混成集積回路基
板上に、ゲル状の絶縁合成樹脂をかけて覆い、この合成
樹脂を硬化させて後、リード線と接続片とを溶接するよ
うにし、溶接による金属粉が落下しても合成樹脂層上に
付着し。This invention was made to eliminate the drawbacks of the conventional mounting method described above. Electronic components are mounted, lead wires are raised, and a gel-like material is mounted on a hybrid integrated circuit board housed in a hollow package. The lead wire and the connecting piece are welded together after covering with insulating synthetic resin and curing the synthetic resin, so that even if metal powder from welding falls, it will not adhere to the synthetic resin layer.

漏電や短絡などをなくシ、信頼性を向上する。混成集積
回路の実装方法を提供することを目的としている。Eliminates electrical leakage and short circuits, improving reliability. The purpose is to provide a method for implementing hybrid integrated circuits.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例による混成集積回路の実装方
法を、第３図及び第４図に示す混成集積回路装置の平面
図及び断面図により説明する。図にお騒て、　［１）　
〜ＱＯ、（６ａ）　〜（ａｃ）は上記従来のものと同一
のものである。上面に半導体チップ（３）。Hereinafter, a method for mounting a hybrid integrated circuit according to an embodiment of the present invention will be explained with reference to a plan view and a sectional view of a hybrid integrated circuit device shown in FIGS. 3 and 4. Make a fuss about the figure, [1]
~QO, (6a) ~(ac) are the same as the above conventional ones. Semiconductor chip (3) on the top surface.

チップコンデンサ（４）など電子部品が装着され、複数
本のリード線（５）が立上げられた基板（１）をヒート
シンク（２）上に固着し、このヒートシンク（２）上に
固着したフレーム（６）により囲まれている。これらヒ
ートシン／）　（’））Ｊ−フレーム（６）２により中
空パッケージを形成し、混成集積回路を収容した構成に
なっている。次に、リード用穴（６ａ）からゲル状の絶
縁合成樹脂を注入し、基板（１）上を覆い硬化させ合成
樹脂層αＤとする。この後、各リード線（５）と各接続
片（８）とをそれぞれ溶接接続する。この溶接により導
電性の金属粉（９）が生じるが、フレーム（６）内に落
下した金属粉（９）は合成樹脂層α目」付着する。これ
により、従来のような、基板（１）上での電子部品の短
絡などの事故が防止される。A board (1) on which electronic components such as a chip capacitor (4) are attached and a plurality of lead wires (5) are mounted is fixed on a heat sink (2), and a frame ( 6). These heat sinks/) (')) J-frames (6) 2 form a hollow package in which a hybrid integrated circuit is housed. Next, a gel-like insulating synthetic resin is injected through the lead holes (6a) to cover the substrate (1) and harden to form a synthetic resin layer αD. After this, each lead wire (5) and each connection piece (8) are connected by welding, respectively. Conductive metal powder (9) is produced by this welding, and the metal powder (9) that has fallen into the frame (6) adheres to the synthetic resin layer α. This prevents accidents such as short-circuiting of electronic components on the board (1) as in the conventional case.

なお、中空パッケージの形状は、上記一実施例のものに
限らず、混成集積回路を収容し、立上ったリード線と接
続片をフレーム外で溶接接続する実装によるものであれ
ば、他の形状であっても適用でき、上記実施例と同様の
効果があげれる。Note that the shape of the hollow package is not limited to that of the above-mentioned example, but may be any other shape as long as it accommodates the hybrid integrated circuit and is mounted by welding the rising lead wires and connection pieces outside the frame. It can be applied to any shape, and the same effects as in the above embodiment can be achieved.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明の方法によれば、中空パッケー
ジに収容した混成集積回路基板上を、ゲル状の絶縁合成
樹脂の注入により覆い、硬化させ合成樹脂層上し、この
後、上記基板から立上っであるリード線の上端部と接続
片とを溶接接続したので、溶接により生じる金属粉が合
成樹脂層上に付着することになり、基板とでの漏電や短
絡が防止され、製品の歩留りが向上し、信頼性が高めら
れろうまた。装着された電子部品が環境から保護される
。As described above, according to the method of the present invention, a hybrid integrated circuit board housed in a hollow package is covered by injecting a gel-like insulating synthetic resin, and is cured to form a synthetic resin layer. Since the upper end of the rising lead wire and the connection piece are connected by welding, metal powder produced by welding will adhere to the synthetic resin layer, preventing electrical leakage and short circuits with the board, and improving the quality of the product. It will also improve yield and reliability. The installed electronic components are protected from the environment.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の実装方法を示す混成集積回路装置の平面
図、第２図は＠１図のｎ−ｎ線における断面図、第３図
はこの発明の一実施例による実装方法を示す混成集積回
路装置の平面図、第４図は第３図のＩＶ−ＩＶ線におけ
る断面図である。 １・・・混成集積回路基板、２・・・ヒートシンク、３
・・・半導体チップ、４・・・チップコンデンサ、５・
・・リード線、６・・・フレーム、７・・・外部端子、
８・・接続片、９・・・金属粉、１１・・・合成樹脂層
なお１図中同一符号は同−又は相当部分を示す。 代理人　大岩増雄 第１図 第２図 第３図 第４図FIG. 1 is a plan view of a hybrid integrated circuit device showing a conventional mounting method, FIG. 2 is a sectional view taken along line nn of FIG. A plan view of the integrated circuit device, FIG. 4 is a sectional view taken along the line IV--IV in FIG. 3. 1... Hybrid integrated circuit board, 2... Heat sink, 3
...Semiconductor chip, 4...Chip capacitor, 5.
...Lead wire, 6...Frame, 7...External terminal,
8...Connection piece, 9...Metal powder, 11...Synthetic resin layer Note that the same reference numerals in the drawings indicate the same or equivalent parts. Agent Masuo Oiwa Figure 1 Figure 2 Figure 3 Figure 4

Claims (2)

【特許請求の範囲】[Claims] （１）　上面に電子部品が装着されリード線が立上げら
れた混成集積回路基板を中空パッケージに収容し２この
中空パッケージ上に引出された上記リード線の上端部を
、外部端子への接続片に溶接接続するようにした実装方
法において、ゲル状の絶縁合成樹脂を上記パッケージ内
の上記混成集、積回路基板上に注入して−覆って硬化さ
せ、この後上記リード線と上記接続片とを溶接すること
を特徴とする混成集積回路の実装方法。(1) A hybrid integrated circuit board with electronic components mounted on the top surface and lead wires raised is housed in a hollow package.2 The upper ends of the lead wires drawn out onto the hollow package are connected to connection pieces to external terminals. In the mounting method, a gel-like insulating synthetic resin is injected onto the composite circuit board and integrated circuit board in the package, covered and cured, and then the lead wires and the connection pieces are welded together. A hybrid integrated circuit mounting method characterized by welding. （２）中空パッケージは、上面に混成集積回路基板を固
着したヒートシンクと、合成樹脂材からなり上記ヒート
シンク上の周囲に固着されたフレームとから構成された
特許請求の範囲＃Ｊ１項記載の混成集積回路の実装方法
。(2) The hybrid integrated circuit according to claim #J1, wherein the hollow package is composed of a heat sink having a hybrid integrated circuit board fixed to its upper surface, and a frame made of synthetic resin and fixed around the heat sink. How to implement the circuit.
JP9983684A 1984-05-16 1984-05-16 Mounting method of hybrid integrated circuit Pending JPS60242647A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9983684A JPS60242647A (en) 1984-05-16 1984-05-16 Mounting method of hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9983684A JPS60242647A (en) 1984-05-16 1984-05-16 Mounting method of hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS60242647A true JPS60242647A (en) 1985-12-02

Family

ID=14257894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9983684A Pending JPS60242647A (en) 1984-05-16 1984-05-16 Mounting method of hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS60242647A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5285559A (en) * 1992-09-10 1994-02-15 Sundstrand Corporation Method and apparatus for isolating electronic boards from shock and thermal environments
WO2007096975A1 (en) 2006-02-24 2007-08-30 Fujitsu Limited Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5192064A (en) * 1975-02-11 1976-08-12

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5192064A (en) * 1975-02-11 1976-08-12

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5285559A (en) * 1992-09-10 1994-02-15 Sundstrand Corporation Method and apparatus for isolating electronic boards from shock and thermal environments
WO2007096975A1 (en) 2006-02-24 2007-08-30 Fujitsu Limited Semiconductor device
US7834443B2 (en) 2006-02-24 2010-11-16 Fujitsu Limited Semiconductor device with molten metal preventing member

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