JPH0685126A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0685126A
JPH0685126A JP26522092A JP26522092A JPH0685126A JP H0685126 A JPH0685126 A JP H0685126A JP 26522092 A JP26522092 A JP 26522092A JP 26522092 A JP26522092 A JP 26522092A JP H0685126 A JPH0685126 A JP H0685126A
Authority
JP
Japan
Prior art keywords
semiconductor device
terminal
resin
case
outer case
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP26522092A
Other languages
Japanese (ja)
Other versions
JP2924498B2 (en
Inventor
Masahide Miyagi
正英 宮城
Toshifusa Yamada
敏総 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP26522092A priority Critical patent/JP2924498B2/en
Publication of JPH0685126A publication Critical patent/JPH0685126A/en
Application granted granted Critical
Publication of JP2924498B2 publication Critical patent/JP2924498B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To provide a terminal assembly structure to obtain a reliable semiconductor device which is easy to assemble with respect to outgoing terminals and hardly influenced by external stress or thermal stress due to being subjected to heat cycles. CONSTITUTION:An outgoing terminal 6 is soldered to a ceramic substrate 2 mounted with semiconductor elements 4, and one end of the terminal is projected from the resin case 7. The case 7 is then filled with gelatinous resin 9, being sealed. The outgoing terminal 6 is integrated into the case 7 by insert molding. This facilitates the assembly of the semiconductor device including the outgoing terminal. In addition, external and thermal stresses exerted on the outgoing terminal are directly received by the case; therefore, unfavorable stress will not be applied to the ceramic substrate or the soldered part between the terminal and the substrate.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、インバータなどに適用
するパワースイッチング素子として用いるパワートラン
ジスタモジュールなどを対象とした半導体装置、特にそ
の組立構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for a power transistor module used as a power switching element applied to an inverter or the like, and more particularly to an assembly structure thereof.

【0002】[0002]

【従来の技術】まず、本発明の実施対象となる半導体装
置の従来における組立構造を図7に示す。図において、
1は放熱用金属ベース、2はセラミック基板、3は基板
2の導体パターン、4は基板上に搭載した半導体素子
(パワートランジスタ)、5は内部配線のボンディング
ワイヤ、6はセラミック基板2上に起立させて導体パタ
ーン3と半田付けした外部導出端子、7は樹脂モールド
品で作られた外囲ケース、8はおなじく樹脂モールド品
のケース蓋、9は半導体素子4を封止して外囲ケース内
に充填したシリコーンゲルなどのゲル状樹脂、10は外
部導出端子6を固定するために外囲ケース7の端子引出
し部に注入,硬化したエポキシなどの成形樹脂である。
2. Description of the Related Art First, a conventional assembly structure of a semiconductor device to which the present invention is applied is shown in FIG. In the figure,
1 is a metal base for heat dissipation, 2 is a ceramic substrate, 3 is a conductor pattern of the substrate 2, 4 is a semiconductor element (power transistor) mounted on the substrate, 5 is a bonding wire for internal wiring, and 6 is standing on the ceramic substrate 2. The external lead-out terminal soldered to the conductor pattern 3, 7 is an outer case made of a resin molded product, 8 is a similar resin molded product case lid, and 9 is a semiconductor device 4 sealed in the outer case. A gel-like resin such as a silicone gel filled in 10 is a molding resin such as epoxy that is injected and cured in the terminal lead-out portion of the outer case 7 to fix the external lead-out terminal 6.

【0003】かかる構成により、半導体素子4は外囲ケ
ース7内でゲル状樹脂9により封止保護され、また外部
導出端子6はモールド樹脂10により外囲ケース7に固
定されてセラミック基板2との間の半田付け部に外部か
ら加わる応力,ヒートサイクルによる熱応力が加わるの
を防止している。
With such a structure, the semiconductor element 4 is sealed and protected by the gel resin 9 in the outer case 7, and the external lead-out terminal 6 is fixed to the outer case 7 by the mold resin 10 so that the semiconductor substrate 4 and the ceramic substrate 2 are connected to each other. This prevents external stress and thermal stress due to heat cycles from being applied to the soldered parts in between.

【0004】[0004]

【発明が解決しようとする課題】ところで、前記した半
導体装置の端子組立構造では、外部導出端子6を外囲ケ
ース7に固定するために、組立治具を用いて外部導出端
子6を所定の組立位置に精度よく保持することが必要と
なるほか、外囲ケース7に対して外部導出端子6の周囲
にモールド樹脂10の注入,硬化の工程が必要となるた
めに組立工数が多く、かつ部品のアッセンブリに多くの
時間と費用が掛かるためにコストアップとなる。また、
外部導出端子6を固定するエポキシなどのモールド樹脂
10とセラミック基板2とは熱膨張率が大きく異なるこ
とから、ヒートサイクルに伴う熱応力でセラミック基板
2に割れが生じたり、外部導出端子6の半田付け部が劣
化するなどのトラブルが発生し易い難点があった。
By the way, in the terminal assembly structure of the semiconductor device described above, in order to fix the external lead-out terminal 6 to the outer case 7, the external lead-out terminal 6 is assembled in a predetermined manner using an assembly jig. In addition to the need to accurately hold the position, the molding case 10 needs to be injected and cured around the external lead-out terminal 6 with respect to the outer case 7, resulting in a large number of assembly steps and a large number of parts. Assembling requires a lot of time and cost, resulting in an increase in cost. Also,
Since the mold resin 10 for fixing the external lead-out terminals 6 and the ceramic substrate 2 have large thermal expansion coefficients, the ceramic substrate 2 is cracked due to thermal stress due to the heat cycle, or the solder of the external lead-out terminals 6 is soldered. There is a problem that troubles such as deterioration of the attachment portion are likely to occur.

【0005】さらに、当該半導体装置をスイッチング素
子として使用する場合には、スイッチング動作に伴う電
流変化(di/dt),電圧変化(dv/dt)が基
で、回路インダクタンス,浮遊容量によって高周波ノイ
ズが発生し、これが誘導ノイズとして電源回路,周囲空
間に伝播して周辺機器にノイズ障害を与えることが知ら
れており、その対策としてノイズカットフィルタを回路
に接続したり、あるいは半導体装置を大地に接地された
金属製容器内に収容して静電遮へいするなどの手段が従
来より講じられている。しかして、静電遮へいのために
特別な金属容器を付設することは重量が増し、寸法が大
形化するために好ましくなく、その改善策が望まれてい
る。
Further, when the semiconductor device is used as a switching element, high frequency noise is generated due to circuit inductance and stray capacitance based on current change (di / dt) and voltage change (dv / dt) accompanying switching operation. It is known that the noise is generated and propagates as inductive noise to the power supply circuit and the surrounding space to cause noise interference to peripheral devices. As a countermeasure, connect a noise cut filter to the circuit or ground the semiconductor device to ground. Conventionally, measures such as electrostatic shielding by accommodating it in a metal container have been taken. However, it is not preferable to attach a special metal container for electrostatic shielding because the weight increases and the size becomes large, and an improvement measure thereof is desired.

【0006】本発明は上記の点にかんがみなされたもの
であり、第1の目的は前記課題を解決して組立性に優
れ、しかも外部導出端子に応力の影響を及ぼすことが殆
どない信頼性の高い半導体装置、特にその端子組立構造
を提供することにある。また、第2の目的はパッケージ
自身に静電遮へい機能を持たせてパワー素子のスイッチ
ング動作に伴って発生する誘導ノイズの周囲伝播を良好
に抑制できるようにした半導体装置を提供することにあ
る。
The present invention has been made in view of the above points, and a first object thereof is to solve the above-mentioned problems and to be excellent in assembling property, and to have a reliability that an external lead-out terminal is hardly affected by stress. An object of the present invention is to provide a high semiconductor device, especially a terminal assembly structure thereof. It is a second object of the present invention to provide a semiconductor device in which the package itself has an electrostatic shielding function so that the ambient propagation of induced noise generated by the switching operation of the power element can be favorably suppressed.

【0007】[0007]

【課題を解決するための手段】上記した第1,第2の目
的は、本発明により、半導体装置を次記のように構成す
ることで達成される。まず、第1の目的に対しては、 (1)外部導出端子を樹脂製の外囲ケースにインサート
成形して一体ブロック化する。
The above first and second objects can be achieved by the present invention by configuring a semiconductor device as follows. First, for the first purpose, (1) the external lead-out terminal is insert-molded into a resin-made enclosure case to form an integral block.

【0008】(2)外部導出端子のケース貫通部位に樹
脂製のピンブロックを一体成形するとともに、外囲ケー
ス側には前記ピンブロックの外形に対応する端子引出し
穴を開口し、該端子引出し穴に前記ピンブロックを嵌め
込んで接着する。 (3)前項(2)において、ピンブロックを異形輪郭体
で構成する。 (4)前項(1)または(2)において、外囲ケースの
底部側に末広り脚部を形成して基板ないし金属ベースと
の間を接合する。
(2) A pin block made of resin is integrally formed in the case penetrating portion of the external lead-out terminal, and a terminal lead-out hole corresponding to the outer shape of the pin block is opened on the side of the outer case, and the terminal lead-out hole is formed. The pin block is fitted into and bonded. (3) In the above item (2), the pin block is formed of an irregular contour body. (4) In the above item (1) or (2), a diverging leg portion is formed on the bottom side of the outer casing to join the substrate or the metal base.

【0009】(5)前項(1)または(2)において、
外囲ケースと基板ないし金属ベースとの間を半田付けな
どにより合金接合する。 また、第2の目的に対する解決手段とし次記の構成があ
る。 (6)外囲ケースをその注型樹脂に導電性粉末を混在さ
せて成形する。 (7)外囲ケースの内周面に外部導出端子の貫通部を除
いて導電膜を被着形成する。
(5) In the above item (1) or (2),
The outer case and the substrate or the metal base are alloy-bonded by soldering or the like. Further, there is the following configuration as a means for solving the second object. (6) The enclosure case is formed by mixing the casting resin with conductive powder. (7) A conductive film is formed on the inner peripheral surface of the outer case except the penetrating portion of the external lead terminal.

【0010】[0010]

【作用】前記(1)〜(3)項の構成により、半導体装
置の取扱時に外部導出端子に加わる外力は、樹脂ケース
で直接受け止められるのでセラミック基板,ないし基板
との間の半田付け部に外部応力が作用することがない。
また、ピンブロックを歯車形,十字形,楕円形,台形な
どの異形輪郭体とすることにより、例えば単純な円形輪
郭体と比べて外囲ケースとの間の接着面積が大となり、
これによりケースとの間で高い接着力が得られる。しか
も外囲ケース内にはゲル状樹脂が充填されているのでセ
ラミック基板,および外部導出端子の半田付け部にヒー
トサイクルに起因する熱応力の加わるおそれも殆どなく
なる。さらに、半導体装置の組立ラインでは外部導出端
子を固定するための位置決め保持,成形樹脂の注入,硬
化工程が不要となるので組立工数も少なくて済む。
With the constructions of the above (1) to (3), the external force applied to the external lead-out terminal during handling of the semiconductor device is directly received by the resin case, so that the external force is applied to the ceramic substrate or the soldering portion between the external substrate and the substrate. No stress acts.
In addition, by making the pin block a deformed contour body such as a gear shape, a cross shape, an ellipse shape, or a trapezoid shape, for example, the bonding area with the outer case becomes larger than that of a simple circular contour body,
As a result, a high adhesive force is obtained between the case and the case. Moreover, since the outer case is filled with the gel-like resin, there is almost no risk of applying thermal stress due to the heat cycle to the ceramic substrate and the soldered portion of the external lead terminal. Further, since the semiconductor device assembly line does not require the positioning and holding for fixing the external lead-out terminal, the injection of the molding resin, and the curing step, the number of assembling steps can be reduced.

【0011】また、前記(4)項の構成により、外囲ケ
ースと相手側のセラミック基板,あるいは金属ベースと
の間に広い接合面積が確保される。さらに、(5)項の
構成では、外囲ケースと基板,金属ベースとの接合を、
基板と外部導出端子との半田付け接合と同じ工程で同時
に行うことができ、接着剤による固着法と比べて接着剤
の塗布,硬化する工数が省ける。
Further, according to the construction of the above item (4), a wide bonding area is secured between the outer case and the other side ceramic substrate or the metal base. Further, in the configuration of the item (5), the outer case, the substrate, and the metal base are joined together as follows.
This can be performed at the same time in the same process as the soldering and joining of the substrate and the external lead-out terminal, and the number of steps for applying and curing the adhesive can be saved as compared with the fixing method using the adhesive.

【0012】一方、(6),(7)項の構成によれば、半
導体装置のパッケージ自身が静電遮へい体のしての機能
を持つことになり、パワー素子のスイッチング動作に伴
う誘導ノイズが周辺空間へ伝播して周辺機器に影響する
ノイズ障害を抑制できる。
On the other hand, according to the configurations of (6) and (7), the package of the semiconductor device itself has a function as an electrostatic shield, and the induced noise accompanying the switching operation of the power element is generated. It is possible to suppress noise interference that propagates to the peripheral space and affects peripheral devices.

【0013】[0013]

【実施例】以下本発明の実施例を図面に基づいて説明す
る。なお、各実施例で図7と対応する同一部材には同じ
符号が付してある。図1は本発明の請求項1に対応する
実施例を示すものであり、外部導出端子6は樹脂モール
ド品として作られた外囲ケース7の成形金型にインサー
トして一体成形され、外部導出端子6と外囲ケース7と
が一体にブロック化して構成される。そして、セラミッ
ク基板2に外部導出端子6を半田付けする際には、外部
導出端子6を外囲ケース7とともにセラミック基板上の
定位置に載置し、この状態で樹脂ケース7の接着,およ
び外部導出端子6と導体パターン3との間の半田付けを
行う。その後にケース蓋8を被着し、樹脂ケース7の内
部にゲル状樹脂9を充填して半導体素子4を封止する。
Embodiments of the present invention will be described below with reference to the drawings. In each embodiment, the same members corresponding to those in FIG. 7 are designated by the same reference numerals. FIG. 1 shows an embodiment corresponding to claim 1 of the present invention, in which an external lead-out terminal 6 is integrally molded by being inserted into a molding die of an outer case 7 made as a resin-molded product. The terminal 6 and the outer case 7 are integrally formed into a block. Then, when soldering the external lead-out terminals 6 to the ceramic substrate 2, the external lead-out terminals 6 are placed together with the outer case 7 at a fixed position on the ceramic substrate, and in this state, the resin case 7 is bonded and the external case Soldering between the lead-out terminal 6 and the conductor pattern 3 is performed. After that, the case lid 8 is adhered, and the inside of the resin case 7 is filled with the gel resin 9 to seal the semiconductor element 4.

【0014】図2,図3は本発明の請求項2,3に対応
する実施例を示すものであり、この実施例においては、
まず外部導出端子6に対し、あらかじめ該端子が樹脂ケ
ース7を貫通する部位に樹脂製のピンブロック11を一
体成形して端子をピンブロックに埋め込み、一方では外
囲ケース7のモールド成形時に前記ピンブロック11の
外形に対応する端子引出し穴を開口しておく。そして、
外部導出端子6をセラミック基板2の導体パターン3の
上に立てて半田付けした後、上方から外囲ケース7を被
せてピンブロック11をケース側の端子引出し穴に嵌め
込むとともに、さらに両者間を接着剤で接着固定する。
FIGS. 2 and 3 show an embodiment corresponding to claims 2 and 3 of the present invention. In this embodiment,
First, with respect to the external lead-out terminal 6, a resin-made pin block 11 is integrally molded in advance at a portion where the terminal penetrates the resin case 7, and the terminal is embedded in the pin block. A terminal lead-out hole corresponding to the outer shape of the block 11 is opened. And
After the external lead-out terminal 6 is erected on the conductor pattern 3 of the ceramic substrate 2 and soldered, the outer case 7 is covered from above to fit the pin block 11 into the terminal lead-out hole on the case side, and between the both. Fix with adhesive.

【0015】この場合に、図3(a)〜(c)で表すよ
うに、前記の樹脂ブロック11を外形歯車形,十字形,
楕円形などの異形輪郭体として成形しておくことによ
り、例えば単純な円形輪郭体と比べて樹脂ケースとの間
の接着面積が大となるので、これによりケースとの間で
高い接着力が得られ、より一層堅牢な構造となる。図4
(a),(b)はそれぞれ本発明の請求項4,5に対応す
る構造を図1の外囲ケースに適用した実施例を示すもの
である。すなわち、(a)図では外囲ケース7の底部側
に末広り脚部7aを形成してセラミック基板2との間を
接着剤により接合したものである。このように外囲ケー
ス7に末広り脚ブロック7aを設けておくことにより、
より広い接合面積が確保できてパッケージの組立接合強
度が高まる。また、(b)図では外囲ケース7の底面に
あらかじめメタライズを施しておき、外囲ケース7とセ
ラミック基板2との間を、接着剤を用いずに半田付けな
どで合金接合したものであり、その半田接合部を符号1
2で示す。この構成によれば、接着剤の塗布,硬化など
のわずらしい工程が不要となり、しかも外囲ケース7と
セラミック基板2との間の接合作業を外部導出端子6の
半田付け工程と同時に行うことができるので、半導体装
置の組立工数が少なくて済む利点が得られる。なお、
(a),(b)図の構成は図2で述べたピンブロック11
を採用の外囲ケース7に対しても同様に実施適用するこ
とができるのは勿論である。
In this case, as shown in FIGS. 3 (a) to 3 (c), the resin block 11 has the external gear shape, the cross shape,
By forming it as an irregular contour such as an ellipse, the adhesion area with the resin case will be larger than that of a simple circular contour, for example, so that a high adhesive force with the case can be obtained. The structure is even more robust. Figure 4
(A) and (b) respectively show an embodiment in which the structure corresponding to claims 4 and 5 of the present invention is applied to the outer case of FIG. That is, in FIG. 3A, the diverging leg portion 7a is formed on the bottom side of the outer casing 7 and is joined to the ceramic substrate 2 with an adhesive. By providing the diverging leg block 7a on the outer case 7 in this way,
A wider joint area can be secured and the package joint strength is increased. Further, in the figure (b), the bottom surface of the outer case 7 is metallized in advance, and the outer case 7 and the ceramic substrate 2 are alloy-bonded by soldering or the like without using an adhesive. , The solder joint is designated as 1
2 shows. According to this configuration, complicated steps such as application and curing of an adhesive are unnecessary, and the joining work between the outer case 7 and the ceramic substrate 2 is performed simultaneously with the soldering step of the external lead-out terminals 6. Therefore, there is an advantage that the number of assembling steps of the semiconductor device can be reduced. In addition,
The configuration shown in FIGS. 2A and 2B is the pin block 11 described in FIG.
It is needless to say that the same can be applied and applied to the enclosure case 7 adopting the above.

【0016】図5(a),(b)は図2における外囲ケー
ス7を対象に、本発明の請求項6,7による誘導ノイズ
防止対策を施した実施例を示すものである。なお、この
実施例においてはピンブロック11が断面台形の錐体と
して形成されている。まず、(a)図は外囲ケース7,
ケース蓋8の材料である注型樹脂に、適量のカーボン,
あるいは金属などの導電性粉末13を分散,混在して外
囲ケース7,ケース蓋8をモールド成形したものであ
る。なお、ピンブロック11は、外部導出端子6に対す
る沿面絶縁強度を確保するために導電性粉末を混在させ
ない。また(b)図は外囲ケース7,ケース蓋8の注型
樹脂に導電性粉末を混在させる代わりに、ピンブロック
11の貫通部を除いて外囲ケース7,ケース蓋8の内周
面に例えば銅または鉛合金の導電性薄膜14(膜厚35
μm程度)を印刷,あるいはメッキにより被着形成した
ものである。なお、この導電性薄膜14は、直接大地に
接地するか、あるいはセラミック基板2の導体パターン
3を介して接地することができる。
FIGS. 5 (a) and 5 (b) show an embodiment in which the outer case 7 in FIG. 2 is subjected to the measures against the induced noise according to claims 6 and 7 of the present invention. In this embodiment, the pin block 11 is formed as a cone with a trapezoidal cross section. First, (a) is an enclosure case 7,
An appropriate amount of carbon is added to the casting resin that is the material of the case lid 8.
Alternatively, the conductive powder 13 such as metal is dispersed and mixed, and the outer case 7 and the case lid 8 are molded. The pin block 11 does not contain conductive powder in order to secure the creeping insulation strength for the external lead-out terminal 6. Further, FIG. 7B shows that the inner case surfaces of the outer case 7 and the case lid 8 are removed except for the penetrating portion of the pin block 11 instead of mixing the conductive powder in the casting resin of the outer case 7 and the case lid 8. For example, a conductive thin film 14 of copper or lead alloy (film thickness 35
It is formed by printing or plating. The conductive thin film 14 can be directly grounded to the ground or can be grounded via the conductor pattern 3 of the ceramic substrate 2.

【0017】かかる構成によれば、外囲ケース7,ケー
ス蓋8のパッケージ自身が静電遮へい体としての機能を
持つようになるので、ケース内に組み込んだ半導体素子
4のスイッチング動作により発生するノイズが周辺空間
に伝播するのを抑制し、周辺機器にノイズ障害を与える
のを防止できる。なお、図5のパッケージ構造は図1の
外囲ケースにも実施適用することができる。
According to this structure, the package itself including the outer case 7 and the case lid 8 has a function as an electrostatic shield, so that the noise generated by the switching operation of the semiconductor element 4 incorporated in the case. Can be prevented from propagating to the surrounding space, and noise interference to peripheral devices can be prevented. The package structure of FIG. 5 can be applied to the outer case of FIG.

【0018】図6は先記した各実施例の応用例を示すも
のである。すなわち、図1〜図5で述べた各実施例では
外囲ケース7をセラミック基板2に接合したのに対し
て、この実施例は外囲ケース7を金属ベース1に接合し
てパッケージが組立て構成されている。なお、この実施
例の外囲ケース7に図5(b)で述べた導電性薄膜14
を被着形成し、かつ外囲ケース7と金属ベース1との接
合に図4(b)で述べた半田付け接合法を採用すること
により、セラミック基板2の導体パッケージ3を経由す
ることなく、静電遮へい体として機能する導電性薄膜1
4を金属ベース1を介して直接大地側に接地することが
できる。
FIG. 6 shows an application example of each of the above-mentioned embodiments. That is, in each of the embodiments described with reference to FIGS. 1 to 5, the outer case 7 is joined to the ceramic substrate 2, whereas in this embodiment, the outer case 7 is joined to the metal base 1 to assemble the package. Has been done. In addition, the conductive thin film 14 described in FIG.
By applying the soldering joining method described with reference to FIG. 4B to the outer case 7 and the metal base 1 without depositing via the conductor package 3 of the ceramic substrate 2. Conductive thin film 1 that functions as an electrostatic shield
4 can be directly grounded to the ground side via the metal base 1.

【0019】[0019]

【発明の効果】以上述べたように、本発明の半導体装置
によれば、次記の効果を奏する。 (1)本発明の請求項1〜3の構成を採用することによ
り、特に外部導出端子を定位置へ固定するのに位置決め
治具が不要であり、かつ外囲ケースとの間の固定も簡単
で組立工数が少なくて済む。しかも外部導出端子に加わ
る外部からの応力,ヒートサイクルによる熱応力などは
外囲ケースが直接吸収するので、外部導出端子と基板と
の間の半田接合部に不当な応力の加わることがない。
As described above, the semiconductor device of the present invention has the following effects. (1) By adopting the configurations of claims 1 to 3 of the present invention, a positioning jig is not particularly required to fix the external lead-out terminal to a fixed position, and the fixing with the outer case is easy. Therefore, the number of assembling steps is small. Moreover, since the outer case directly absorbs the external stress applied to the external lead-out terminal, the thermal stress due to the heat cycle, and the like, the solder joint between the external lead-out terminal and the substrate is not unduly applied with stress.

【0020】(2)本発明の請求項4の構成によれば、
外囲ケースの接着面積が広く確保できてパッケージの接
合強度が高まる。 (3)本発明の請求項5の構成によれば、手間のかかる
接着剤の塗布,硬化工程を省略して外囲ケースと基板,
あるいは金属ベースとの間の接合作業を、外部導出端子
と基板との半田付けと同じ工程で同時に行うことができ
て組立工数の削減化が図れる。
(2) According to the configuration of claim 4 of the present invention,
A wide bonding area can be secured for the outer case, and the bonding strength of the package is enhanced. (3) According to the structure of claim 5 of the present invention, the enclosing case and the substrate can be omitted by omitting the time-consuming steps of applying and curing the adhesive.
Alternatively, the joining work with the metal base can be simultaneously performed in the same step as the soldering of the external lead-out terminal and the substrate, and the number of assembling steps can be reduced.

【0021】(4)本発明の請求項6,7の構成を採用
することにより、半導体装置のパッケージ自身に静電遮
へい機能を与えることができ、これにより特別な静電遮
へい容器を付設することなく、パワー素子のスイッチン
グ動作に伴って発生する高周波ノイズが周囲空間に伝播
して他の周辺機器に及ぼすノイズ障害を良好に抑制でき
るど、機能面で優れた効果を発揮する。
(4) By adopting the constitutions of claims 6 and 7 of the present invention, it is possible to impart an electrostatic shielding function to the package of the semiconductor device itself, thereby providing a special electrostatic shielding container. However, the high-frequency noise generated by the switching operation of the power element can be effectively suppressed from propagating to the surrounding space and affecting other peripheral devices, but the function is excellent.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の請求項1に対応する実施例の組立構成
FIG. 1 is an assembly configuration diagram of an embodiment corresponding to claim 1 of the present invention.

【図2】本発明の請求項2に対応する実施例の組立構成
FIG. 2 is an assembly configuration diagram of an embodiment corresponding to claim 2 of the present invention.

【図3】本発明の請求項3に対応する実施例のピンブロ
ック外形輪郭体を表す平面図であり、(a) は歯車形,
(b) は十字形, (c)は楕円形の外形図
FIG. 3 is a plan view showing a pin block outer shape contour body of an embodiment corresponding to claim 3 of the present invention, FIG.
(B) is a cross shape, (c) is an oval outline drawing

【図4】図1の応用実施例を示すものであり、(a)は
本発明の請求項4に対応する実施例の組立構成図、
(b)は本発明の請求項5に対応する実施例の組立構成
FIG. 4 shows an application example of FIG. 1, and (a) is an assembly configuration diagram of an embodiment corresponding to claim 4 of the present invention,
(B) is an assembly configuration diagram of an embodiment corresponding to claim 5 of the present invention.

【図5】図2の応用実施例を示すものであり、(a)は
本発明の請求項6に対応する実施例の組立構成図、
(b)は本発明の請求項7に対応する実施例の組立構成
FIG. 5 shows an application example of FIG. 2, wherein (a) is an assembly configuration diagram of an embodiment corresponding to claim 6 of the present invention,
(B) is an assembly configuration diagram of an embodiment corresponding to claim 7 of the present invention

【図6】図5と異なる応用実施例の組立構成図6 is an assembly configuration diagram of an application example different from FIG.

【図7】従来における半導体装置の組立構成図FIG. 7 is an assembly configuration diagram of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 金属ベース 2 セラミック基板 3 導体パターン 4 半導体素子 6 外部導出端子 7 外囲ケース 7a 末広り脚部 8 ケース蓋 9 ゲル状樹脂 11 ピンブロック 12 半田接合部 13 導電性粉末 14 導電性薄膜 1 Metal Base 2 Ceramic Substrate 3 Conductor Pattern 4 Semiconductor Element 6 External Lead-out Terminal 7 Enclosure Case 7a Edge Spread Leg 8 Case Lid 9 Gel Resin 11 Pin Block 12 Solder Joint 13 Conductive Powder 14 Conductive Thin Film

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】放熱用金属ベース上に積層した基板に半導
体素子,外部導出端子を搭載してなる組立体に樹脂製の
外囲ケースを組合わせ、かつ外部導出端子の一端を外囲
ケースより外部に引き出すとともに、外囲ケース内にゲ
ル状樹脂を充填して封止した半導体装置において、外部
導出端子を樹脂ケースにインサート成形して一体ブロッ
ク化したことを特徴とする半導体装置。
1. An outer casing made of resin is combined with an assembly in which a semiconductor element and an external lead terminal are mounted on a substrate laminated on a metal base for heat dissipation, and one end of the external lead terminal is separated from the outer casing. What is claimed is: 1. A semiconductor device in which an external lead-out terminal is insert-molded into a resin case to form an integrated block in a semiconductor device which is drawn out to the outside and is filled with a gel resin in an outer case and sealed.
【請求項2】放熱用金属ベース上に積層した基板に半導
体素子,外部導出端子を搭載してなる組立体に樹脂製の
外囲ケースを組合わせ、かつ外部導出端子の一端を外囲
ケースより外部に引き出すとともに、外囲ケース内にゲ
ル状樹脂を充填して封止した半導体装置において、外部
導出端子のケース貫通部位に樹脂製のピンブロックを一
体成形するとともに、外囲ケース側には前記ピンブロッ
クの外形に対応する端子引出し穴を開口し、該端子引出
し穴に前記ピンブロックを嵌め込んで接着したことを特
徴とする半導体装置。
2. An outer casing made of resin is combined with an assembly comprising a semiconductor element and an external lead terminal mounted on a substrate laminated on a metal base for heat dissipation, and one end of the external lead terminal is connected to the outer casing. In a semiconductor device in which the outer case is filled with a gel-like resin and sealed while being pulled out to the outside, a resin pin block is integrally formed at the case penetrating portion of the outer lead terminal, and A semiconductor device, wherein a terminal lead-out hole corresponding to the outer shape of a pin block is opened, and the pin block is fitted and adhered to the terminal lead-out hole.
【請求項3】請求項2記載の半導体装置において、ピン
ブロックを異形輪郭体で構成したことを特徴とする半導
体装置の端子組立構造。
3. A terminal assembly structure for a semiconductor device according to claim 2, wherein the pin block is formed of an irregular contour body.
【請求項4】請求項1,または2記載の半導体装置にお
いて、外囲ケースの底部側に末広り脚部を形成して基板
ないし金属ベースとの間を接合したことを特徴とする半
導体装置。
4. The semiconductor device according to claim 1, wherein a diverging leg portion is formed on the bottom side of the outer case and is joined to a substrate or a metal base.
【請求項5】請求項1,または2記載の半導体装置にお
いて、外囲ケースと基板ないし金属ベースとの間を半田
付けなどにより合金接合したことを特徴とする半導体装
置。
5. The semiconductor device according to claim 1, wherein the outer case and the substrate or the metal base are alloy-bonded by soldering or the like.
【請求項6】請求項1,または2記載の半導体装置にお
いて、外囲ケースをその注型樹脂にカーボン,金属など
の導電性粉末を混在させて成形したことを特徴とする半
導体装置。
6. The semiconductor device according to claim 1, wherein the outer case is formed by mixing conductive powder such as carbon or metal in the casting resin.
【請求項7】請求項1,または2記載の半導体装置にお
いて、外囲ケースの内周面に外部導出端子の貫通部を除
いて導電性膜を被着形成したことを特徴とする半導体装
置。
7. The semiconductor device according to claim 1, wherein a conductive film is formed on the inner peripheral surface of the outer case except the penetrating portion of the external lead terminal.
JP26522092A 1992-07-16 1992-10-05 Semiconductor device Expired - Lifetime JP2924498B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26522092A JP2924498B2 (en) 1992-07-16 1992-10-05 Semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP4-188468 1992-07-16
JP18846892 1992-07-16
JP26522092A JP2924498B2 (en) 1992-07-16 1992-10-05 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0685126A true JPH0685126A (en) 1994-03-25
JP2924498B2 JP2924498B2 (en) 1999-07-26

Family

ID=26504947

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26522092A Expired - Lifetime JP2924498B2 (en) 1992-07-16 1992-10-05 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2924498B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0924845A3 (en) * 1997-12-22 2001-05-23 Omnirel LLC Power semiconductor module
US6885097B2 (en) 2000-04-25 2005-04-26 Kabushiki Kaisha Toyota Jidoshokki Semiconductor device
US8759839B2 (en) 2011-11-04 2014-06-24 Sumitomo Electric Industries, Ltd. Semiconductor module and method for manufacturing semiconductor module
KR20160047959A (en) * 2014-10-23 2016-05-03 주식회사 솔루엠 Power module
KR20160051513A (en) * 2014-11-03 2016-05-11 주식회사 솔루엠 Power module and manufacturing method thereof
US11626333B2 (en) 2020-05-22 2023-04-11 Fuji Electric Co., Ltd. Semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0924845A3 (en) * 1997-12-22 2001-05-23 Omnirel LLC Power semiconductor module
US6885097B2 (en) 2000-04-25 2005-04-26 Kabushiki Kaisha Toyota Jidoshokki Semiconductor device
US8759839B2 (en) 2011-11-04 2014-06-24 Sumitomo Electric Industries, Ltd. Semiconductor module and method for manufacturing semiconductor module
KR20160047959A (en) * 2014-10-23 2016-05-03 주식회사 솔루엠 Power module
KR20160051513A (en) * 2014-11-03 2016-05-11 주식회사 솔루엠 Power module and manufacturing method thereof
US11626333B2 (en) 2020-05-22 2023-04-11 Fuji Electric Co., Ltd. Semiconductor device

Also Published As

Publication number Publication date
JP2924498B2 (en) 1999-07-26

Similar Documents

Publication Publication Date Title
JP3316714B2 (en) Semiconductor device
JP2000294692A (en) Resin-sealing type electronic device and manufacture of the same, ignition coil for internal combustion engine using the same device
JPH02342A (en) Attachment of integrated circuit chip and package assembly
JP2002135080A (en) Surface acoustic wave device and its manufacturing method
JPH0831988A (en) Sealing structure of tape carrier package
US5444602A (en) An electronic package that has a die coupled to a lead frame by a dielectric tape and a heat sink that providees both an electrical and a thermal path between the die and teh lead frame
JPS62202548A (en) Semiconductor device
JPH0685126A (en) Semiconductor device
JPH0661372A (en) Hybrid ic
JPH02278752A (en) Semiconductor device
JP3703969B2 (en) Electronic circuit device and manufacturing method thereof
JP3447385B2 (en) Hybrid IC and manufacturing method thereof
KR100237912B1 (en) Packaged semiconductor, semiconductor device made therewith and method for making same
JPH06334070A (en) Hybrid integrated circuit device
JPH03266456A (en) Semiconductor chip heat dissipating member and semiconductor package
JPH0513963A (en) Electronic component mounting board
JPS6239036A (en) Hybrid ic
JPH06140535A (en) Tape-carrier-package type semiconductor device
KR0129198B1 (en) Semiconductor package
JPS60242647A (en) Mounting method of hybrid integrated circuit
JP3711669B2 (en) Electronic component mounting board
JPH0864761A (en) Hybrid ic and manufacture thereof
JPH05160317A (en) Structure for assembling semiconductor device
JPH02305013A (en) Mounting structure for surface acoustic wave element
JPH1155057A (en) Production of solid-state element device

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080507

Year of fee payment: 9

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080507

Year of fee payment: 9

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090507

Year of fee payment: 10

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090507

Year of fee payment: 10

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100507

Year of fee payment: 11

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100507

Year of fee payment: 11

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100507

Year of fee payment: 11

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110507

Year of fee payment: 12

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110507

Year of fee payment: 12

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120507

Year of fee payment: 13

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120507

Year of fee payment: 13

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120507

Year of fee payment: 13

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130507

Year of fee payment: 14

EXPY Cancellation because of completion of term
FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130507

Year of fee payment: 14