JPS60239050A - 半導体基板の位置合わせ方法 - Google Patents

半導体基板の位置合わせ方法

Info

Publication number
JPS60239050A
JPS60239050A JP59094841A JP9484184A JPS60239050A JP S60239050 A JPS60239050 A JP S60239050A JP 59094841 A JP59094841 A JP 59094841A JP 9484184 A JP9484184 A JP 9484184A JP S60239050 A JPS60239050 A JP S60239050A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
substrate
bonding
bumps
bonding tool
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59094841A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0416017B2 (enExample
Inventor
Yasunori Senkawa
保憲 千川
Takamichi Maeda
前田　崇道
Masao Hayakawa
早川　征男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP59094841A priority Critical patent/JPS60239050A/ja
Publication of JPS60239050A publication Critical patent/JPS60239050A/ja
Publication of JPH0416017B2 publication Critical patent/JPH0416017B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing

Landscapes

  • Wire Bonding (AREA)
JP59094841A 1984-05-11 1984-05-11 半導体基板の位置合わせ方法 Granted JPS60239050A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59094841A JPS60239050A (ja) 1984-05-11 1984-05-11 半導体基板の位置合わせ方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59094841A JPS60239050A (ja) 1984-05-11 1984-05-11 半導体基板の位置合わせ方法

Publications (2)

Publication Number Publication Date
JPS60239050A true JPS60239050A (ja) 1985-11-27
JPH0416017B2 JPH0416017B2 (enExample) 1992-03-19

Family

ID=14121261

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59094841A Granted JPS60239050A (ja) 1984-05-11 1984-05-11 半導体基板の位置合わせ方法

Country Status (1)

Country Link
JP (1) JPS60239050A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5536974A (en) * 1992-05-22 1996-07-16 Sumitomo Electric Industries, Ltd. Semiconductor device with light reflecting substrate area

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4992548A (enExample) * 1973-01-10 1974-09-04

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4992548A (enExample) * 1973-01-10 1974-09-04

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5536974A (en) * 1992-05-22 1996-07-16 Sumitomo Electric Industries, Ltd. Semiconductor device with light reflecting substrate area

Also Published As

Publication number Publication date
JPH0416017B2 (enExample) 1992-03-19

Similar Documents

Publication Publication Date Title
TW201946201A (zh) 黏晶裝置及半導體裝置的製造方法
JPS60239050A (ja) 半導体基板の位置合わせ方法
TW202107575A (zh) 黏晶裝置及半導體裝置的製造方法
JPS5816532A (ja) 位置決め装置
JP2596913B2 (ja) 半導体ペレットの位置決め装置
JP2701174B2 (ja) バンプ付け方法
JPH01173174A (ja) 認識位置補正方法
JP2533375B2 (ja) テ―プボンディングにおけるリ―ドとバンプの位置検出方法
JPH0416436Y2 (enExample)
JPH0224949A (ja) 集束イオンビームによるデバイス加工位置合せ装置
JPH07118492B2 (ja) テープボンディングの位置決め方法
JPH0455529B2 (enExample)
JPH01183127A (ja) ダイボンデイング方法
JPS62291126A (ja) パタ−ン認識マ−ク
JPH0799399A (ja) 位置合わせ装置
JPH02155243A (ja) 認識装置
JP3319283B2 (ja) ボンディング位置のティーチング方法
JPH04291738A (ja) マップを利用した半導体装置の組立方法
JPS63247788A (ja) パネル位置決め装置
CN119703260A (zh) 一种dbc预焊接辅助装置及控制方法
JP2004151654A (ja) 電気光学装置、及び電気光学装置の製造方法並びに電子機器
JPH03104249A (ja) インナーリードのボンディング装置
JP2000329516A (ja) アライメントマーク
JPH04205342A (ja) 一体型表示入力装置
JP2792285B2 (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees