JPS6022825A - High speed semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a master-slave SR flip-flop where number of gates to be inverted at operation is decreased and higher speed operation is attained by constituting a gate circuit as 2-level. CONSTITUTION:The gate circuit system for the master-slave SR flip-flop circuit is the BFL system which is used frequently in the normally-on type GaAs integrated circuit, and a positive potential is given to positive power supply inputs VDD1-VDD8 and a negative potential is given to negative power inputs VSS1- VSS4 at the operation. Further, the number of gates to be inverted at the operation is less than that of the circuit of all NOR constitution and the high speed operation is attained. Moreover, the single phase clock operation is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a high-speed master-slave SR Flyno-Pufronov circuit with single-phase clock operation that takes advantage of the normally-on logic features that have been praised in GaAslC. GaAslC combines high-speed performance and low power consumption that cannot be achieved with SiIC, so it is expected to be applied in a wide range of fields in the future.

In order for GaAs ICs to exhibit their high performance as practical ICs, in addition to improving logic gates, it is necessary to improve the circuitry of various basic module circuits. In particular, since the flip-flop circuit is the most basic component that is used very often in actual logic ICs, the development of high-performance flip-flop circuits is directly related to GaAslC's final 1: Noh mask. These are extremely important and connected issues. , Flip-flop circuits as components of GaAs ICs are not easy to use.
Single-phase clock operation, 6) stable operation and performance, especially ■ high speed (+i!i) is desirable.

FIG. 1 is a circuit diagram of a conventional edge trigger type D flip-flop. In the figure, terminals C, D, Q, and φ are a clock data input and an inverted output, respectively.

Although this circuit operates stably with a single-phase clock, it has the disadvantage that its speed is slow due to the large number of gates that must be inverted during operation, and its function is limited to delay operation.

FIG. 2 is a circuit diagram of a conventional mask-slave SR flip-flop. In the figure, C1, S, R, Q.

Q is a clock input, reverse phase clock, set input, reset input and output J are inverted outputs, respectively.

Since the circuit shown in FIG. 1 is an all-N ORliil'i configuration, the number of data l- to be inverted to ++H is large and the speed is slow compared to the circuit described later. Also, a two-phase clock is required.

FIG. 3 is a circuit diagram of another type of conventional master-slave SR flip-flop. In the diagram, the 1st child C, C, S,
R, Q, and φ are clock inputs, reverse phase clock inputs, cent inputs, reset inputs, and inverted outputs, respectively.

This circuit has a two-level gate configuration, which reduces the number of gates, and has about twice the number of gates as compared to the above-mentioned circuit. However, in order to reliably operate this circuit, a high-precision two-phase clock is required, and if C1C goes low at the same time, take damage will occur, and if it goes high at the same time, it will easily self-oscillate. do. GaA that operates at high speed
It is extremely difficult to supply a highly accurate two-phase clock to s1C without satisfying the above conditions.

rDisclosure of the invention] 21. '-4'
, Nina Master Slave SR Frino Pfronov Ill
This is what I would like to suggest.

The master-slave SR flip-flop circuit of the present invention is of the type shown in FIG. 4 or FIG. The gate circuit system has been widely used in normally-on type GaΔS integrated circuits. It is a BFL method, and V during operation.
D January to positive potential to VDD8 and vSS1 to VSS
Apply a negative potential to 4. In the figure, c, i::, s.

R, Q, and ◇ are respectively black, evening force, reverse phase clock input, cent input, reset input and output, and inverted output.

In the circuit of the present invention, since the gate circuit has a two-level configuration, the number of gates to be inverted during operation is smaller than that of the all-NOR circuit shown in FIGS. The action can be achieved. Additionally, this circuit operates with a single-phase clock. [Industrial Applicability] The present invention relates to a master-slave SR flip-flop that is suitable for a normally-on GaAs integrated circuit that operates stably and at high speed with a single-phase clock. It is. GaAs
Since it can be widely used as a basic component of digital ICs, it has great industrial value.

[Brief explanation of the drawing]

NS1 is a diagram of a conventional engine trigger D flip-flop circuit, and FIGS. 2 and 3 are diagrams of a conventional mask-slave S R flip-flop circuit. 4 and 5 are 1. for explaining the master-slave SR flip-flop circuit fll↑ of the present invention. <1. In the diagram C... Clock input C... Reverse phase clock input D... Data input Q... Output ◇...・・Inverted output S・・・Input R−・・Reset input VDD l, VDD 2, VDD3, VD
D4, VDD5. Vl) D n . VDD7. VDD8−−・−・Positive power supply input VSSi,
VSS2. VSS3. VSS4. - Negative power supply 4・'1i11+

Claims (1)

[Claims] (]) In a normally-on GaAs integrated circuit composed of a Schottky gate (MESFET) and a Schottky diode, first, second, and third drivers whose sources are commonly grounded and whose drains are connected in parallel MESFET and its driver MESF
By cross-connecting two impark circuits consisting of a fourth driver MESF E i'' connected in series to the drain of the ET, a load, and a level shift circuit (1.
The fifth and sixth drivers ME connected in series, with the flip-flop circuit constructed as a mask or slave.
The horizontal J is
be decapitated. A high-speed semiconductor device characterized by combining a flip-flop circuit as a slave or a mask.