JPH0247638Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Technical Field) This invention relates to a semiconductor circuit using a shot gate field effect transistor (hereinafter referred to as MESFET), and particularly to a data flip-flop circuit.

(Technical background) Like a data flip-flop circuit, a MESFET in which a positive phase pulse is applied to the gate terminal, an inverter, a negative phase pulse is applied to the gate terminal
MESFETs and inverters are often connected in series. Figure 1 is
This shows a data flip-flop circuit with MESFET as a component, and T1 to T4 are
MESFET, I1 to I4 are inverters, I5 and I6 are inverters in the drive circuit, and the D input signal is taken in while the C input signal is high level, and the D input signal is taken in when the C input signal becomes low level. It operates by outputting the input signal to Q and Q.

However, the configuration shown in Figure 1 can be used as is.
When used in a circuit using GaAs MESFET, the first
In the figure, the input input to the gates of GaAsMESFETT2 and T3 is the output of inverter I5, and the output of inverter I5 is also input to the gate of inverter I6, so the high level of the input input to the gates of GaAsMESFETT2 and T3 is the output of inverter I6. Voltage determined by shot barrier height, e.g. 0.7V
becomes. Since the low level of the signal entering the source of MESFETT2, T3 is not completely 0V but a voltage of 0.1 to 0.2V, the source of MESFETT2, T3 -
The voltage between the gates will be 0.5 to 0.6V. Therefore, MESFETT2 and T3 are not sufficiently conductive.

In the configuration described above, the gate of the transmission gate -
Since it is not possible to apply a sufficient voltage between the sources to exceed the height of the shot barrier, this has been a major hindrance to the high-speed operation required of data flip-flop circuits.

In addition to data flip-flop circuits,
Semiconductor circuits equipped with transmission gates using GaAs MESFETs also have the aforementioned drawbacks.

(Purpose of the invention) The purpose of the invention is to obtain a semiconductor circuit using a transmission gate with high operating speed.

(Summary of the invention) The main point of this invention is that in a semiconductor circuit using a GaAs MESFET transmission gate, the transmission gate drive circuit consists of two circuits connected in parallel to its input terminal, one of which is connected to one inverter. One of the two inverters is configured to output negative phase pulses, and the other is comprised of two cascaded inverters and outputs positive phase pulses.

(Embodiment) Fig. 2 is a data flip-flop circuit diagram for explaining an embodiment of this invention, and Fig. 3 is a circuit diagram of an inverter used in this embodiment. The power supply voltage 31 is a normally-off type MESFET, and 32 is a normally-on type MESFET. Furthermore, FIG. 4 shows the conventional data flip-flop circuit configuration shown in FIG.
The speeds of the data flip-flop circuit of the present embodiment shown in FIG. 2 are determined by computer simulation and compared with those of the case where the GaAs MESFET is used.

Further, D is a data input terminal, C is a clock input terminal, Q is an output terminal of a data flip-flop,
Q is the negative phase output terminal of Q, T11 to T14 are normally-off type GaASMESFETs, and I10 to I16 are
This is a direct-coupled inverter using GaAs MESFETs.

As shown in Figure 2, the data input terminal D is connected to the source of normally-off GaAs MESFET (hereinafter referred to as FET) T11, and the drain of FETT11 is
Connect to the source of FETT12 and the input terminal of inverter I10. The output terminal of inverter I10 is connected to the input terminal of inverter I11, and the output terminal of inverter I11 is connected to the drain of FETT12 and
Connect to the source of FETT13. The drain of FETT13 is connected to the source of FETT14 and inverter I.
Connect to 12 input terminals. The output terminal of inverter I12 is connected to the input terminal of inverter I13, and the output terminal of inverter I13 is connected to the drain of FETT14. Output and Q are taken from the output terminals of inverter I12 and inverter I13, respectively.

Further, the clock input terminal C is connected to the input terminals of an inverter I14 and an inverter I15, and the output terminal of the inverter I14 is connected to the input terminal of an inverter I16. The output terminal of inverter I15 is
Connected to the gates of FETT12 and FETT13, and the output terminal of inverter I16 is connected to the gates of FETT11 and FETT1.
Connect to gate 4.

In the circuit configuration in Figure 1, FETT2, T3
However, in the circuit configuration according to this embodiment shown in FIG. 2, by obtaining the voltage input to the gates of FETT12 and T13 from the inverter I15, The high level of this input signal is not limited by the voltage clamped by the shot barrier height, but is determined by the constant potential power supply voltage, and a voltage of 0.7V or higher can be output. This signal is FETT12,T
When input to the gate of FETT 13, a voltage higher than the shot barrier height is applied between their source and gate, so that FETT 12 and T13 become completely conductive. Therefore, signals passing through these transmission gates can be transmitted quickly, and the operation of the data flip-flop can be made faster.

Furthermore, in the circuit configuration shown in Figure 1, the load on inverter I5 is divided into inverter I6 and FETT2.
Since FETT3 is large, FETT2 and FETT3
However, in the circuit configuration of FIG. 2 according to this embodiment, the inverter I
Since the load of 15 is only FETT12 and T13
The rise and fall of the signals entering the gates of FETT12 and T13 are sharp and the flip-flop operates stably.

In addition, the speeds of the data flip-flop circuit shown in FIG. 1 and the data flip-flop circuit of this embodiment shown in FIG. 2 were determined by computer simulation, and the comparison results are shown in FIG. .
In FIG. 4, the horizontal axis shows the power supply voltage, and the vertical axis shows the calculated delay time from when the clock input changes until it is output to the data input Q. a,
aa is the delay when the output from the output terminal Q changes from low level to high level, b and bb are the delays when the output from the output terminal changes from low level to high level,
c, cc indicate the delay in which the output from the output terminal Q changes from high level to low level, d, dd indicate the delay in which the output from the output terminal changes from high level to low level, and a, b, c, d is the conventional circuit configuration, aa,
bb, cc, and dd are based on the circuit configuration of this embodiment. When the output from output terminal Q changes from high level to low level at power supply voltage 1V 5
%, conversely when changing from low level to high level 22
%, 26% when the output from the output terminal changes from high level to low level, and 7% when the output changes from low level to high level. The effectiveness of not clamping by other gate circuits has been shown.

Note that even in semiconductor circuits with transmission gates other than data flip-flops, the transmission gate drive circuit is composed of two circuits connected in parallel to the input terminals, one of which is composed of one inverter. The transmission gate can be effectively utilized by configuring one inverter to output negative-phase pulses and the other to output positive-phase pulses through two cascade-connected inverters. can.

(Effects of the invention) As explained above, this invention prevents the high-level signal that enters the gate terminal of the transmission gate circuit from being clamped to other shot junctions of the drive circuit, resulting in stable and high-speed operation. A semiconductor circuit can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a data flip-flop circuit with MOSFET as a component, FIG. 2 is a data flip-flop circuit diagram for explaining an embodiment of this invention, and FIG. FIG. 4, a circuit diagram of the inverter used in the example, is a diagram comparing the speeds of the circuit shown in FIG. 1 and the circuit of the present embodiment shown in FIG. 2, determined by computer simulation. D...Data input terminal, C...Clock input terminal,
Q...The output terminal of the data flip-flop is Q
negative phase output terminal, T1 to T4...MESFET, I1
~I6...Inverter, T11-T14...
MESFET, I10-I16...Inverter, V...
Constant potential power supply voltage, 31...Normally off type
MESFET, 32...Normally-on type MESFET.

Claims (1)

[Claims for Utility Model Registration] A first stage circuit including a normally-off type first short-gate field effect transistor, one or a plurality of cascade-connected inverters each including the short-gate field-effect transistor as a component, and a normally-off second short-gate field effect transistor. A second stage circuit including a field effect transistor and a second stage circuit including one or a plurality of cascaded inverters each having a short gate field effect transistor as a component; A drive circuit including an inverter and outputting a positive phase pulse and a negative phase pulse is provided, the positive phase pulse output is applied to the gate of the first shot gate field effect transistor, and the negative phase pulse output is applied to the gate of the second shot gate field effect transistor. In the semiconductor circuit applied to the gate of the transistor, the drive circuit is composed of two circuits connected in parallel to its input terminal, one of which is composed of an inverter and outputs a reverse phase pulse, and 1. A semiconductor circuit characterized in that the other one is composed of a plurality of cascade-connected inverters and outputs positive-phase pulses.