JPH0411131B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gallium arsenide semiconductor integrated circuit among semiconductor integrated circuits.

[Conventional technology]

Below, as a conventional technology, the E/D type shown in Fig. 1 of Proceedings of the 1986 Institute of Electronics and Communication Engineers General Conference Proceedings P2-306
A sense amplifier circuit in a Direct Coupled FET Logic circuit (hereinafter abbreviated as an E/D type DCFL circuit) will be described. FIG. 2 shows the circuit configuration of the prior art. 21 and 24 in the figure are normally-on metal-semiconductor field effect transistors (hereinafter metal-semiconductor field effect transistors).
(abbreviated as MESFET) 22, 23 and 25 are normally-off MESFETs and normally-on type
MESFET21 has a drain connected to a positive power supply (node 26), and a gate and source connected to a normally-off type
MESFET22 drain and normally-off type
The normally-off type MESFET is connected to the first terminal (node 27) other than the gate of MESFET23.
22 has a normally-on type MESFET2 drain.
1 gate and source and normally off type
The gate is connected to the input node (node 28) at the first terminal other than the gate of MESFET23 (node 27).
In the normally-off type MESET23, the source is connected to the ground potential, and the first terminal of the two terminals other than the gate is connected to the normally-on type MESFET2.
1 gate and source and normally off type
The second terminal is connected to the drain (node 27) of MESFET22, and the second terminal is connected to the normally-off type MESFET2.
5 gate (node 30), and a signal for controlling conduction/non-conduction between the first terminal and the second terminal is input to the gate (node 29). The drain of the normally-on type MESFET 24 is positive. The drain (node 31) of the normally-off type MESFET 25 whose gate and source are connected to the power supply (node 26)
The normally-off type MESFET25 is connected to
The drain is connected to the gate and source (node 31) of the normally-on type MESFET 24, and the gate is connected to a second terminal other than the gate (node 30) of the normally-off type MESFET 23, and the source is connected to the ground potential.
Further, the node 31 becomes an output node.

Next, the operation will be explained. In Figure 2, normally-on type MESFET21 and normally-off type
MESFET22 and normally-on type MESFET2
4 and normally-off type MESFET25 each constitute an E/D inverter circuit, and normally-off type MESFET25 constitutes an E/D inverter circuit.
MESFET 23 is a transfer gate that controls conduction or non-conduction between node 27 and node 30 by a control signal from node 29 . When a logic signal is input from node 28, normally-on type MESFET 21 and normally-off type MESFET 22
is inverted by an inverter circuit consisting of
It is output from node 27. Here, when the control signal from the node 29 is at a low level and the transfer gate 23 is in a non-conducting state, the level at the node 27 is not transmitted to the node 30, and the level at the node 27 is at a high level.
The level rises to the power supply voltage at node 26. Conversely, when the control signal from the node 29 is at High level and the transfer gate 23 is in a conductive state, the potential of the output node 27 of the first stage inverter is transmitted to the node 30, and the normally-on type MESFET 24
It is further inverted by an inverter circuit consisting of a normally-off type MESFET 25 and outputted from the notebook 31. By the way, in MESFET, the potential between the gate and source is the height of the shot barrier between the gate metal and the gallium arsenide semiconductor substrate.
It cannot rise above about 0.6V, and the power supply potential of the node 26 is normally set higher than the above-mentioned shot barrier height. Therefore, the high level of the nodes 27 and 30 has a value of about 0.6V, which is the height of the shot barrier between the gate and source of the normally-off type MESFET 25.

Further, the low level of the node 27 is always a constant value (approximately the ground potential) regardless of whether the transfer gate 23 is normally non-conductive.

[Problem that the invention seeks to solve]

Since the conventional E/D type DCFL circuit has the above configuration, when the transfer gate 23 is non-conductive, the high level of the output of the previous stage rises to the power supply potential, and then the transfer gate becomes conductive. At the same time, when the output node of the previous stage changes from a high level to a low level, the voltage amplitude of this node increases, causing a problem that the change from high level to low level is slow.

This invention was made to solve the above problems, and is composed of a plurality of semi-insulating gallium arsenide semiconductor field type transistors,
In a device in which the output node of the first logic circuit and the input node of the second logic circuit are connected by a transfer gate, the high level of the output node before the transfer gate is always set to the shot barrier height of the metal-semiconductor interface. By setting the transfer gate to a small degree, the transfer gate changes from a non-conducting state to a conducting state, and at the same time, the output node of the previous stage changes from a non-conducting state to a conducting state.
The object of the present invention is to shorten the fall time of this node when changing from a high level to a low level, and to provide a gallium arsenide semiconductor integrated circuit suitable for high-speed operation.

[Means for solving problems]

The gallium arsenide semiconductor integrated circuit according to the present invention has an output node at the front stage of the transfer gate.
Normally-off type with at least the source at ground potential
It is connected to the gate of MESFET.

[Effect]

The normally-off MESFET in this invention is
The potential of the output node at the front stage of the transfer gate is always set to about the height of the shot barrier at the metal-semiconductor interface, regardless of whether the transfer gate is in a conductive state or a non-conductive state.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In Figure 1, 1 and 4 are normally on type
MESFETs 2, 3, 5 and 12 are normally-off MESFETs, and normally-on MESFET 1 is
The drain is connected to the positive power supply (node 6), and the gate and source are connected to the first node other than the drain of normally-off type MESFET 2, the gate of normally-off type MESFET 12, and the gate of normally-off type MESFET 3.
is connected to the terminal (node 7) of the normally-off type.
MESFET2 has a normally-on drain type.
MESFET1 gate and source and normally-off type MESFET12 gate and normally-off type
The first terminal (node 7) other than the gate of MESFET 3 is connected to the gate, the gate is connected to the input node (node 8), and the source is connected to the ground potential. is connected to the gate and source of normally-on type MESFET 1, the drain of normally-off type MESFET 2, and the gate (node 7) of normally-off type MESFET 12, and the second terminal is connected to the gate (node 10) of normally-off type MESFET 5.
A signal for controlling conduction or non-conduction between the first terminal and the second terminal is input to the gate (node 9). The drain of the normally-on MESFET 4 is connected to the positive power supply (node 6), and the gate and source are connected to the drain (node 11) of the normally-off type MESFET 5.
MESFET5 has a normally-on drain type.
MESFET4 gate and source (node 11)
, the gate is connected to the second terminal (node 10) other than the gate of the normally-off type MESFET 3, and the source is connected to the ground potential, and the normally-off type MESFET
12 is the gate and source of normally-on type MESFET 1 and normally-off type MESFET 2
connected to the drain of and the first terminal (node 7) other than the gate of the normally-off type MESFET 3,
At least the source is connected to ground potential. Also,
Node 11 becomes the output node.

Hereinafter, the effects of the above embodiment will be explained based on FIG. 1. Normally-on type MESFET1, normally-off type MESFET2, and normally-on type
MESFET4 and normally-off type MESFET5 are the first and second transistors each consisting of an E/D inverter circuit.
Normally-off type MESFET3 constitutes the logic circuit of
serves as a transfer gate that controls conduction or non-conduction between the node 7 and the node 10 by the control signal of the node 9. Also, normally-off type
The MESFET 12 constitutes clamping means for clamping the high level potential at the output node 7 of the first logic circuit to the potential at the height of the shot barrier at the metal-semiconductor interface.

The input logic signal from node 8 is inverted by an inverter circuit composed of normally-on type MESFET 1 and normally-off type MESFET 2, and is output from node 7. At this time, when the control signal to the node 9 is at a low level and the transfer gate 3 is in a non-conductive state, the high level at the node 7 is not transmitted to the node 10. At this time, node 7's
Due to the action of the normally-off MESFET 12, the High level cannot rise to the power supply voltage of the node 6, and is clamped at about 0.6V, which is the shot barrier height at the metal-semiconductor interface.

When the control signal from node 9 is at a high level and transfer gate 3 is in a conductive state, node 7
The level of is transmitted to node 10, and the level of
The High level is clamped at the height of the shot barrier between the gate and source of normally-off type MESFET 12 and normally-off type MESFET 5,
It will be about 0.6V. That is, regardless of whether the transfer gate 3 is conductive or non-conductive, the High level is always a constant value of about 0.6V. Therefore, when transfer gate 3 is in a non-conducting state, node 7 is in a non-conducting state.
At high level, the potential of node 7 is about 0.6V, then transfer gate 3 becomes conductive, and at the same time the potential of node 7 changes from high level to
Even when the potential of the node 7 changes to the Low level, the change in the potential of the node 7 is from about 0.6 V to the Low level (about the ground potential), as in the case where the transfer gate 3 was in a conductive state before the change in the potential of the node 7. This is from the power supply potential of node 26 in the conventional example.
The amplitude of the potential change is small compared to the change to the Low level, and therefore the time required for the change is short.

FIG. 3 shows a state in which transfer gates 3 and 23 are initially non-conductive and nodes 7 and 27 are at a high level, then the transfer gates become conductive and at the same time nodes 7 and 27 change from high level to low level. 7,27 changes are shown. In the figure, 41 represents a change in node 7, and 42 represents a change in node 27. Note that the power supply potentials of nodes 6 and 26 are both 1.0V. As is clear from FIG. 3, in the circuit according to the present invention, compared to the conventional circuit,
The change from High level to Low level is faster, and the delay time caused by the transfer gate 3 can be shortened.

In the above embodiment, in the E/D type DCEL circuit, the E/D inverter output is connected to one terminal other than the gate of the transfer gate, but the first and second logic circuits are configured. E/
A NOR circuit or a NAND circuit may be used instead of a D-inverter, and it is applicable in any circuit type other than a DCFL circuit, when the output of the inverter, NOR circuit, or NAND circuit is connected to one terminal other than the gate of the transfer gate. You can achieve the same effect.

FIGS. 4 and 5 show other embodiments of the present invention. Figure 4 shows node 7 in a normally-off type with the source and drain connected to ground potential.
This is an example in which node 7 is connected to the gate of MESFET 12, and FIG. 5 is an example in which node 7 is connected to the gate of normally-off type MESFET 12 with a source that constitutes an E/D inverter. Both can produce the same effect. .

〔Effect of the invention〕

As described above, according to the present invention, the transistor is configured of a plurality of semi-insulating gallium arsenide semiconductor field effect transistors, and the connection between the output node of the first logic circuit and the input node of the second logic circuit is In those connected by transfer gates, the first
Since the clamp means is provided with a semi-insulating gallium arsenide semiconductor field effect transistor whose gate is connected to the output node of the logic circuit and whose source is connected to the ground potential node,
Since the high level of the output from the front stage of the transfer gate can be clamped to a potential similar to the shot potential of the metal-semiconductor interface, the change time from high level to low level can be shortened, making this gallium arsenide semiconductor integrated circuit suitable for high-speed operation. is obtained.

[Brief explanation of drawings]

FIG. 1 shows an E/D type according to an embodiment of the present invention.
Circuit diagram of the DCFL circuit, Figure 2 is the conventional E/D type
The circuit diagram of the DCFL circuit, FIG. 3, is a potential change state diagram showing time changes in the potentials of the node 7 and the node 27. 4 and 5 are circuit diagrams showing other embodiments of the present invention. 1, 4, 21, 24 are normally on type
MESFET, 2, 3, 5, 12, 23, 25 are normally-off MESFETs, 6-11, 26-31
indicate each node. Further, 41 represents a change in the potential of the node 7, and 42 represents a change in the potential of the node 27.

Claims (1)

[Scope of Claims] 1. A transistor comprising a plurality of semi-insulating gallium arsenide semiconductor field effect transistors, having at least a first input node and a first output node, and having a gate connected to the first input node. a first logic circuit having a normally-off type semi-insulating gallium arsenide semiconductor field effect transistor connected between the output node and the ground potential node; at least a second transistor;
a normally-off type semi-insulating gallium arsenide semiconductor electric field having an input node and a second output node, a gate connected to the second input node, and connected between the output node and a ground potential node. a second logic circuit having an effect transistor, connected between a first output node of the first logic circuit and a second input node of the second logic circuit, and controlling conduction and non-conduction states; a transfer gate consisting of a semi-insulating gallium arsenide semiconductor field-effect transistor whose gate receives a control signal to control the output; the gate is connected to the first output node of the first logic circuit, and the source is connected to a ground potential node A gallium arsenide semiconductor integrated circuit with clamping means consisting of connected semi-insulating gallium arsenide semiconductor field effect transistors. 2 The first logic circuit is an inverter circuit or
Claim 1 characterized in that the circuit is either a NOR circuit or a NAND circuit.
The gallium arsenide semiconductor integrated circuit described in . 3 The first logic circuit includes a normally-off type semi-insulating gallium arsenide semiconductor field effect transistor whose gate is connected to the first input node, and a normally-off type semi-insulating gallium arsenide semiconductor field effect transistor connected between the first output node and a ground node. The inverter circuit is configured with a semi-insulating gallium arsenide semiconductor field effect transistor of the type, and is connected between the power supply potential node and the first output node, and has a gate connected to the first output node. 2. The gallium arsenide semiconductor integrated circuit according to claim 1, wherein the gallium arsenide semiconductor integrated circuit has a semi-insulating gallium arsenide semiconductor field effect transistor. 4 The second logic circuit is an inverter circuit or
Claim 1 characterized in that the circuit is either a NOR circuit or a NAND circuit.
The gallium arsenide semiconductor integrated circuit according to item 1 or 2. 5 The second logic circuit includes a normally-off type semi-insulating gallium arsenide semiconductor field effect transistor whose gate is connected to the second input node, and a normally-off type semi-insulating gallium arsenide semiconductor field effect transistor connected between the second output node and the ground node. A normally-on type semi-insulating gallium arsenide semiconductor field transistor is connected between the power supply potential node and the second output node, and the gate is connected to the second output node. A gallium arsenide semiconductor integrated circuit according to any one of claims 1 to 3, characterized in that it has a semi-insulating gallium arsenide semiconductor field effect transistor.