JPH0411130B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gallium arsenide semiconductor integrated circuit among semiconductor integrated circuits.

[Conventional technology]

Below, as a conventional technology, the E/D type shown in Fig. 1 of Proceedings of the 1986 Institute of Electronics and Communication Engineers General Conference Proceedings P2-306
A sense amplifier circuit in a Direct Coupled FET Logic circuit (hereinafter abbreviated as an E/D type DCFL circuit) will be described. FIG. 2 shows the circuit configuration of the prior art. 21 and 24 in the figure are normally-on metal-semiconductor field effect transistors (hereinafter metal-semiconductor field effect transistors).
(abbreviated as MESFET) 22, 23, and 25 are normally-off type MESFETs, and normally-on type MESFETs.
MESFET21 has a drain connected to a positive power supply (node 26), and a gate and source connected to a normally-off type
MESFET22 drain and normally-off type
The normally-off type MESFET is connected to the first terminal (node 27) other than the gate of MESFET23.
22 has a normally-on type MESFET2 drain.
1 gate and source and normally off type
The gate is connected to the input node (node 28) at the first terminal other than the gate of MESFET23 (node 27).
The sources of the normally-off MESFET 23 are connected to the ground potential, and the first terminal of the two terminals other than the gate is connected to the normally-on MESFET 2.
1 gate and source and normally off type
The second terminal is connected to the drain (node 27) of MESFET 22, and the second terminal is connected to the normally-off type MESFET 25.
The gate of the normally-on MESFET 24 is connected to the gate (node 30), and a signal for controlling conduction/non-conduction between the first terminal and the second terminal is input to the gate (node 29). The power supply (node 26) is connected to the drain (node 31) of MESFET 25 whose gate and source are normally off type.
The ohm-off type MESFET25 is connected to
The drain is connected to the gate and source (node 31) of the normally-on type MESFET 24, the gate is connected to a second terminal other than the gate (node 30) of the normally-off type MESFET 23, and the source is connected to the ground potential. Further, the node 31 becomes an output node.

Next, the operation will be explained. In Figure 2, normally-on type MESFET21 and normally-off type
MESFET22 and normally-on type MESFET2
4 and normally-off type MESFET25 each constitute an E/D inverter circuit, and normally-off type MESFET25 constitutes an E/D inverter circuit.
MESFET 23 is a transfer gate that controls conduction or non-conduction between node 27 and node 30 by a control signal from node 29 .

When a logic signal is input from node 28, normally-on type MESFET 21 and normally-off type
It is inverted by an inverter circuit composed of MESFET 22 and output from node 27. Here, when the control signal from node 29 is at a low level and transfer gate 23 is in a non-conducting state, the level at node 27 is not transmitted to node 30, and the high level at node 27 rises to the power supply voltage at node 26. .

Conversely, when the control signal from the node 29 is at a high level and the transfer gate 23 is in a conductive state, the potential of the output node 27 of the first stage inverter is transmitted to the node 30, and the normally-off type
The signal is further inverted by an inverter circuit including MESFET 24 and normally-off type MESFET 25, and output from node 31. By the way, in a MESFET, the potential between the gate and source cannot rise above about 0.6V, which is the shot barrier height between the gate metal and the gallium arsenide semiconductor substrate, and the power supply potential of node 26 is usually higher than the above shot barrier height. is also set high. Therefore, at this time, the High level of node 27 and node 30 is
The value is about 0.6V, which is the height of the shot barrier between the gate and source of the normally-off MESFET 25.

Further, the low level of the node 27 is always a constant value (approximately the ground potential) regardless of whether the transfer gate 23 is conductive or non-conductive.

[Problem that the invention seeks to solve]

Since the conventional E/D type DCFL circuit has the above configuration, when the transfer gate 23 is non-conductive, the high level of the output of the previous stage rises to the power supply potential, and then the transfer gate becomes conductive. At the same time, when the output node of the previous stage changes from High level to Low level, the voltage amplitude of this node becomes large, causing a problem that the change from High level to Low level is slow.

This invention was made to solve the above problems, and is composed of a plurality of semi-insulating gallium arsenide semiconductor field effect transistors, and has an output node of a first logic circuit and an output node of a second logic circuit. In a device connected to the input node of a logic circuit by a transfer gate, by always keeping the high level of the output node before the transfer gate at about the height of the shot barrier, the transfer gate changes from a non-conducting state to a conducting state. state, and at the same time the output node of the previous stage changes from High level to
The purpose of the present invention is to shorten the fall time of this node when it changes to a low level, and to provide a gallium arsenide semiconductor integrated circuit suitable for high-speed operation.

[Means for solving problems]

The gallium arsenide semiconductor integrated circuit according to the present invention has a Schottky diode connected between the output node at the front stage of the transfer gate and the ground potential.

[Effect]

In the Schottky diode of the present invention, the potential of the output node in the preceding stage of the transfer gate is always about the height of the Schottky barrier, regardless of whether the transfer gate is in a conductive state or in a non-conductive state.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In Figure 1, 1 and 4 are normally on type
MESFET, 2, 3 and 5 are normally off type
MESFET 12 is a shotgun diode, and the normally-on type MESFET 1 has its drain connected to the positive power supply (node 6), and its gate and source connected to the normally-off type MESFET 2 and the anode side of the shottock diode 12 and the normally-off type MESFET.
The normally-off type MESFET 2 is connected to the first terminal (node 7) other than the gate of the normally-off type MESFET 3, and the drain is connected to the gate and source of the normally-on type MESFET 1, the anode side of the Schottky diode 12, and the first terminal other than the gate of the normally-off type MESFET 3. The gate is connected to the terminal (node 7), the gate is connected to the input node (node 8), and the source is connected to the ground potential.
The gate and source of MESFET 1, the drain of normally-off type MESFET 2, and the anode side (node 7) of the Schottky diode are connected, the second terminal is connected to the gate (node 10) of normally-off type MESFET 5, and the gate is connected to the first
A signal for controlling conduction and non-conduction between the terminal and the second terminal is input (node 9). Normal-ion type
MESFET4 has a positive drain power supply (node 6)
The gate and source are normally off type.
The normally-off type MESFET 5 is connected to the drain of MESFET 5 (note 11), and the drain is connected to the gate and source (node 11) of the normally-on type MESFET 4, and the gate is connected to the normally-off type MESFET 4.
The source of the second terminal (node 10) other than the gate of MESFET 3 is connected to the ground potential, and the anode side of the Schottky diode 12 is connected to the gate and source of normally-on type MESFET 1, the drain of normally-off type MESFET 2, and the drain of normally-off type MESFET 3. It is connected to a first terminal (node 7) other than the gate, and its cathode side is connected to the ground potential. Further, node 11 becomes an output node.

Hereinafter, the effects of the above embodiment will be explained based on FIG. Normally-on type MESFET1 and normally-off type MESFET2, and normally-on type MESFET4 and normally-off type MESFET5 constitute first and second logic circuits each consisting of an E/D inverter circuit, and are normally-off type MESFET.
Reference numeral 3 designates a transfer gate that controls conduction or non-conduction between the node 7 and the node 10 in response to a control signal from the node 9. Further, the Schottky diode constitutes a clamping means for clamping the High level potential at the output node 7 of the first logic circuit to the potential at the Schottky barrier height.

The input logic signal from node 8 is inverted by an inverter circuit composed of normally-on type MESFET 1 and normally-off type MESFET 2, and is output from node 7. At this time, the control signal to node 9 is low level, and transfer gate 3
When is in non-conducting state, the high level of node 7 is
Not communicated to node 10. At this time, node 7
The high level cannot rise to the power supply voltage of node 6 due to the shotgun diode 12, and is suppressed to about 0.6V, which is the shottock barrier height.

When the control signal from node 9 is at a high level and transfer gate 3 is in a conductive state, node 7
The level of is transmitted to node 10, and the level of
The High level is suppressed by the shottock diode 12 and the shottock barrier height between the gate and source of the normally-off type MESFET 5, and becomes about 0.6V. In other words, regardless of whether the transfer gate 3 is conductive or not, the high level is always
It becomes a constant value of about 0.6V. Therefore, when the transfer gate 3 is in a non-conducting state and the node 7 is at a high level, the potential of the node 7 is about 0.6V,
Next, transfer gate 3 becomes conductive, and at the same time, the potential of node 7 changes from high level to low level. However, the change in the potential of node 7 will occur if transfer gate 3 was in the conductive state before the change in the potential of node 7. Similarly, the voltage ranges from about 0.6V to low level (about ground potential). This means that the amplitude of the potential change is smaller than the change from the power supply potential of the node 26 to the Low level in the conventional example, and therefore the time required for the change is short.

FIG. 3 shows a state in which transfer gates 3 and 23 are initially non-conductive and nodes 7 and 27 are at a high level, then the transfer gates become conductive and at the same time nodes 7 and 27 change from high level to low level. 7,27 changes are shown. In the figure, 41 represents a change in node 7, and 42 represents a change in node 27. Note that the power supply potentials of nodes 6 and 26 are both 1.0V. As is clear from FIG. 3, in the circuit according to the present invention, compared to the conventional circuit,
The change from High level to Low level is faster, and the delay time caused by the transfer gate 3 can be shortened.

In the above embodiment, in the E/D type DCFL circuit, the E/D inverter output is connected to one terminal other than the gate of the transfer gate, but the first and second logic circuits are configured. E/
A NOR circuit or a NAND circuit may be used instead of a D-inverter, and it is applicable to any circuit type other than a DCFL circuit, where the output of the inverter, NOR circuit, or NAND circuit is connected to one terminal other than the gate of the transfer gate. You can achieve the same effect.

As described above, according to the present invention, the transistor is configured of a plurality of semi-insulating gallium arsenide semiconductor field effect transistors, and is connected between the output node of the first logic circuit and the input node of the second logic circuit. In the case of a gate connected by an agate, the anode is connected to the output node of the first logic circuit, and a clamping means consisting of a Schottky diode whose cathode is connected to the ground potential node is provided, so that the transfer gate Since the high level of the output of the previous stage can be clamped to a potential similar to the shotgun potential of a diode,
A gallium arsenide semiconductor integrated circuit that can shorten the transition time from high level to low level and is suitable for high-speed operation can be obtained.

[Brief explanation of drawings]

FIG. 1 shows an E/D type according to an embodiment of the present invention.
Circuit diagram of the DCFL circuit, Figure 2 is the conventional E/D type
The circuit diagram of the DCFL circuit, Fig. 3 is a potential change state diagram showing the time change of the potential of node 7 and node 27. 1, 4, 21, 24 are normally-on type
MESFET, 2, 3, 5, 23, 25 are normally-off MESFETs, 12 is a Schottky diode,
6 to 11 and 26 to 31 indicate nodes, respectively. Further, 41 represents a change in the potential of the node 7, and 42 represents a change in the potential of the node 27.

Claims (1)

[Scope of Claims] 1. A transistor comprising a plurality of semi-insulating gallium arsenide semiconductor field effect transistors, having at least a first input node and a first output node, and having a gate connected to the first input node. a first logic circuit having a normally-off type semi-insulating gallium arsenide semiconductor field effect transistor connected between the output node and the ground potential node; at least a second transistor;
a normally-off type semi-insulating gallium arsenide semiconductor electric field having an input node and a second output node, a gate connected to the second input node, and connected between the output node and a ground potential node. a second logic circuit having an effect transistor, connected between a first output node of the first logic circuit and a second input node of the second logic circuit, and controlling conduction and non-conduction states; a transfer gate consisting of a semi-insulating gallium arsenide semiconductor field effect transistor whose gate receives a control signal, an anode connected to a first output node of the first logic circuit, and a cathode connected to a ground potential node; A gallium arsenide semiconductor integrated circuit with clamping means consisting of connected Schottky diodes. 2 The first logic circuit is an inverter circuit or
Claim 1 characterized in that the circuit is either a NOR circuit or a NAND circuit.
The gallium arsenide semiconductor integrated circuit described in . 3 The first logic circuit includes a normally-off type semi-insulating gallium arsenide semiconductor field effect transistor whose gate is connected to the first input node, and a normally-off type semi-insulating gallium arsenide semiconductor field effect transistor connected between the first output node and a ground node. The inverter circuit is configured with a semi-insulating gallium arsenide semiconductor field effect transistor of the type, and is connected between the power supply potential node and the first output node, and has a gate connected to the first output node. 2. The gallium arsenide semiconductor integrated circuit according to claim 1, wherein the gallium arsenide semiconductor integrated circuit has a semi-insulating gallium arsenide semiconductor field effect transistor. 4 The second logic circuit is an inverter circuit or
Claim 1 characterized in that the circuit is either a NOR circuit or a NAND circuit.
The gallium arsenide semiconductor integrated circuit according to item 1 or 2. 5 The second logic circuit includes a normally-off type semi-insulating gallium arsenide semiconductor field effect transistor whose gate is connected to the second input node, and a normally-off type semi-insulating gallium arsenide semiconductor field effect transistor connected between the second output node and the ground node. A normally-on type semi-insulating gallium arsenide semiconductor field transistor is connected between the power supply potential node and the second output node, and the gate is connected to the second output node. A gallium arsenide semiconductor integrated circuit according to any one of claims 1 to 3, characterized in that it has a semi-insulating gallium arsenide semiconductor field effect transistor.