JPS6022510B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and provides two methods for manufacturing a semiconductor device that has a high breakdown voltage, is easy to manufacture, and has good controllability.

For example, by applying the present invention to a vertical junction field effect transistor (1-FET), the gate
High breakdown voltage between source or gate and drain,
In addition, the number of mask alignment processes is significantly small, and since a self-alignment method is used in the mask alignment process, there is no need to worry about mask alignment misalignment during mask alignment.
-FET can be obtained.

First, let's talk about J-FET as an example.
In a structure in which the gate region of one FET is formed by buried diffusion and an epitaxial growth layer is formed on its surface, diffusion occurs from the gate region buried and diffused at a high concentration during epitaxial growth to the epitaxial growth layer, and the channel region is It was difficult to control the breakdown voltage between the gate and source.

A J-FET having a gate and source on the surface of a semiconductor substrate has been proposed as a method to improve these drawbacks. 1st
The figure shows a method for manufacturing the J-FET. First, an n-type epitaxial growth layer 2 is formed on an n-type semiconductor substrate 1,
An oxide film 3 having an opening at a predetermined location is formed, and a P-type impurity is diffused to form a gate diffusion region 4 [a}.

Next, an oxide film 5 having a closing part is formed between the gates, a source diffusion region 6 is formed from this closed part, and then a new oxide film 7 is formed, and then a predetermined area of the source and gate is formed. Make an opening again at the location, perform metal vapor deposition, and install metal wiring 8.
form [c'. Since this method is a method of forming the gate 4 on the surface, it does not close the channel unlike a buried gate.

However, the number of times of mask alignment is large, and the misalignment of the mask alignment when forming the source region 6 causes the source and gate to come into contact, lowering the withstand voltage between the source and gate, which poses a problem in achieving high integration. The present invention improves these drawbacks, eliminates the problem of mask alignment, improves the breakdown voltage, and simplifies the manufacturing process.

Next, the method of the present invention will be explained along with Example Z in which the method of the present invention is applied to a J-FET.

FIG. 2 shows a method for manufacturing a J-FET according to an embodiment of the present invention. Semiconductor substrate 10 containing n-type high concentration impurities
1 (drain region), forming an epitaxial growth layer 102 containing an n-type high concentration impurity, and diffusing the n-type high concentration impurity on the surface of the epitaxial growth layer 102.
'a} to form the source forming diffusion layer 103; Next game...
Source diffusion layer 1
b) Using this as a mask, by irradiating ultraviolet rays in a hydrogen fluoride solution to make it porous, only the region 103 where impurities are diffused at a high concentration becomes porous. As shown in FIG. 1c}, a porous layer is formed in the texture of the nitride film 104. Next, the porous layer is oxidized in an oxidizing atmosphere at 1100 pm to form the insulating region 105 'C'. Next, using this insulating region 105 as a mask, an n-type diffusion region 1 made of a diffusion layer 103 left with a hydrogen fluoride solution.
A predetermined portion of the insulating region 105 is removed leaving a part 106 of the insulating region 105 on the side of 03'[d'.

The thickness of the remaining insulating region 106 may be several meters, although it depends on the conditions of subsequent gate diffusion. Next, some remaining insulation area 1
Gate region 1 is formed by diffusing P-type impurities using 06 as a mask.
'd forming 07.

Next, the nitride film 104 is removed with hot phosphoric acid, and metal vapor deposition (A, Ti, etc.) is performed to form the gate 107 and source region 103.
Metals other than ' are removed to form a source electrode 108 and a gate electrode 109, and as shown in {f', the source region 103
', J having a gate region 107 and a drain region 101
-FET is formed. In the J-FET described above, the oxide insulating film 106 of several rms exists between the source and the gate, so that the withstand voltage between the source and the gate can be increased.

Furthermore, in the method shown in FIG. 2, the nitride film 104 can be used as a mask for forming the porous insulating material 106 by selective etching and for gate diffusion, so there is no mask alignment process when forming the gate. It has an excellent feature of not only preventing short-circuiting between the source and drain, but also controlling the diffusion depth and lateral expansion of the gate, which allows good controllability of breakdown voltage between the gate and the source. Another embodiment is shown in FIG.

An epitaxial growth layer 202 containing n-type low concentration impurities is formed on the main surface of a semiconductor substrate 201 (drain region) containing n-type high concentration impurities, and the n-type high concentration impurities are formed on the surface of the epitaxial growth layer 202. Diffusion is performed to form a source diffusion layer 203, and polycrystalline silicon 204 (source electrode) containing an n-type high concentration impurity is deposited on the surface of the source diffusion layer 203 [a'. Next, a nitride film 205 having an opening □ in the gate formation area is formed on the surface of the source electrode 204.
By using this as a mask and making it porous while irradiating ultraviolet rays in a hydrogen fluoride solution, only the regions 203 and 204 containing a high concentration of n-type impurities become porous, and [as shown in the table] A porous layer is formed at the end of membrane 205. Next, the porous layer is oxidized in an oxidizing atmosphere of 110 and 0,
An insulating region 206 shown in 'd is formed. Next, the insulating nitride pus 205 was left as a mask 203, 204
' and contains n-type high concentration impurities.
The other oxide insulating film 206 is removed leaving several m of insulating regions 207 on the sides of 03' and 204'[d'. Next, using the partially remaining oxidized region 207 as a mask, P-type impurities are diffused to form a gate region 208 'e'.

Next, metal (AZ, Ti, etc.) is deposited - metal layer 2
09 is formed, and further a vapor-deposited metal layer 2 1 0 of another metal (Pt, Au, etc.) is formed 'f}. This situation (g)
The details are shown in . As is clear from this figure, the metal layers 209 and 210 formed by vapor deposition are formed separately due to the existence of the gap between the nitride film 205 and the gap (step) between it and the insulating film 207. Next, nitride film 205 is formed using sulfuric acid or phosphoric acid.
When etching the metal layer 205 on the nitride film 205, the second vapor-deposited metal layer 210 is not dissolved in the etching solution.
9 and 210 are lifted off, and as shown in (h), a part of the polycrystalline silicon 204' is used as a source electrode, a part of the n-type diffusion layer 203' is used as a source, the P light diffusion layer 208 is used as a gate, and the drain region 201 is used as a source electrode. A J-FET is formed.

This embodiment also has the same excellent features as the case shown in FIG. 2, and is advantageous in terms of process since the gate electrode is formed in the steps shown in FIGS. 3b and 3c.

According to the above method, the mask alignment process can be reduced by one step in the first embodiment and two steps in the second embodiment compared to the conventional surface gate type J-FET shown in FIG. In addition to overcoming the drawbacks of the J-FET, it is possible to significantly improve the surface gate type FET.

Furthermore, in this example, when forming the gate region,
When ion implantation is used, the lateral diffusion of impurities in the gate region is further reduced, the thickness of the insulating film on the side of the source can be reduced, and the area of the source can be increased. In addition, in the example, an n-type substrate was used, but a p-type substrate was used,
The conductivity may be reversed, and the source and drain may be exchanged. Furthermore, the present invention is not limited to J-FETs, but can also be applied to other semiconductor devices. As described above, according to the present invention, a high breakdown voltage semiconductor region can be controlled with good controllability.
J-
This greatly contributes to semiconductor devices such as FETs.

[Brief explanation of drawings]

Figure 1 a, b, and c are J-FETs with gate regions on the surface.
FIGS. 2a to 2f are cross-sectional views of the manufacturing process of an embodiment of the J-FET according to the present invention, and FIGS. 3a to 3h are sectional views of the manufacturing process of another embodiment of the J-FET. FIG. 101, 201... N-type semiconductor substrate (drain), 102, 202... N-type epitaxial layer, 107
, 208... gate diffusion region, 103', 203'...
...Source diffusion region, 104,205...
Nitride film, 106, 207...Insulating region, 108
, 204'... drain or source electrode, 109, 21
0...Gate electrode. Figure 1 Figure 2 Figure 2 Figure 2 Figure 3 Figure 3

Claims (1)

[Scope of Claims] 1. An epitaxial growth layer of the same conductivity type as the substrate is formed on the main surface of a semiconductor substrate of a first conductivity type, and a highly concentrated impurity region of the first conductivity type is formed on the entire surface of the growth layer. a step of selectively making a part of this high concentration impurity region porous to form a porous region; a step of oxidizing this porous region to form an insulating region; selectively exposing the surface of the growth layer by leaving a part of the insulation region located on the side of the growth layer and removing the other insulation region; a step of forming a second conductivity type region by introducing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein an ion implantation method is used to introduce the second conductivity type impurity.