JPS60216564A - Manufacture of semiconductor ic - Google Patents
Manufacture of semiconductor icInfo
- Publication number
- JPS60216564A JPS60216564A JP7327984A JP7327984A JPS60216564A JP S60216564 A JPS60216564 A JP S60216564A JP 7327984 A JP7327984 A JP 7327984A JP 7327984 A JP7327984 A JP 7327984A JP S60216564 A JPS60216564 A JP S60216564A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- groove
- integrated circuit
- layer
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の践する技術分野〕
本発明は、半導体基板に掘られた縛に絶縁物を充てんし
て成る離層を有する半導体集積回路の製造方法に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a method for manufacturing a semiconductor integrated circuit having a separation layer formed by filling holes dug in a semiconductor substrate with an insulating material.
半導体集積回路の素子間の分離のために従来は表面から
拡散により異なる尋′亀形からなる分離層を形成し、P
N接合を利用して分離していた。しかし拡散による分離
層は横方向の拡散もあるため幅を狭くすることが難しい
ので集積回路構造の微細化に伴ない基板に鴫を掘ってそ
の韓に絶縁物を充てんする方法が用いられるようになっ
た。このような幅の狭い溝はプラズマエツチングで形成
されるが、この場合反応性の高いラジカルは高周波iE
源などで発生させるため、その分布が非局所的であり、
選択的なエツチングをするKはレジストバターニングが
必要であった。そのうえ結晶に損傷が起きやすいという
問題もあった。Conventionally, in order to separate the elements of a semiconductor integrated circuit, a separation layer consisting of different turtleneck shapes is formed by diffusion from the surface.
They were separated using an N junction. However, it is difficult to narrow the width of the isolation layer due to diffusion because it also involves lateral diffusion, so as integrated circuit structures become smaller, a method of digging holes in the substrate and filling the holes with insulators has been used. became. Such narrow grooves are formed by plasma etching, in which highly reactive radicals are exposed to high-frequency iE.
Since it is generated at a source, its distribution is non-local,
K, which performs selective etching, required resist buttering. Furthermore, there was also the problem that the crystals were easily damaged.
本発明は、これに対して分離のために幅の狭い溝が容易
に形成でき、結晶に及ぼす影響も小さいような半導体集
積回路の製造方法を提供することを目的とする。In contrast, it is an object of the present invention to provide a method for manufacturing a semiconductor integrated circuit in which narrow trenches for isolation can be easily formed and the influence on crystals is small.
本発明によれば、素子間分離のために光ビームの照射に
より半導体基板を加工して溝を形成し、その溝を絶縁物
で埋めて分離層を形成することにより上述の目的が達せ
られる。半導体基板の加工は、光イオン化により生じた
イオンを電界により基板に向けて加速するかあるいはレ
ーザ加工を利用することにより行うことができる。また
溝の中に埋める絶縁物を光化学反応により生成すること
も有効である。According to the present invention, the above object can be achieved by processing a semiconductor substrate by irradiating a light beam to form a groove for isolation between elements, and filling the groove with an insulating material to form an isolation layer. Processing of a semiconductor substrate can be performed by accelerating ions generated by photoionization toward the substrate using an electric field or by using laser processing. It is also effective to generate an insulator buried in the trench by photochemical reaction.
以下図を引用して本発明の実施例について説明する。第
1図において、シリコン基板1を反応室2の底部3のF
の陽極板4の上に置き、反応室2の内部を真空ポンプ5
により排気したのちボンベ6より塩素ガスをマスフロメ
ータフにより流量制御して導入し、反応室内の圧力を0
.2Torrに調整し、5144Aの波長のAr レー
ザ光8をレンズ9により基板lの直上に焦点を結ぶよう
に照射する。Embodiments of the present invention will be described below with reference to the drawings. In FIG. 1, the silicon substrate 1 is placed at the bottom 3 of the reaction chamber 2.
is placed on the anode plate 4 of the reaction chamber 2, and the inside of the reaction chamber 2 is
After exhausting the air, chlorine gas was introduced from cylinder 6 with the flow rate controlled by a mass flow meter, and the pressure inside the reaction chamber was reduced to 0.
.. The temperature is adjusted to 2 Torr, and Ar laser light 8 having a wavelength of 5144 A is irradiated through a lens 9 so as to be focused directly above the substrate 1.
この光により塩素ガスはイオン化して塩素イオンが生ず
る。光路を囲む陰極板10と陽極板4との間に電源11
により直流バイアスを印加することにより、塩素イオン
は加速されてシリコン基板lに衝突し、基板をエツチン
グする。レーザ光8のビームを繰り返し走査することK
より第2図(、)に示すような所定の形状と深さのe
12を形成することができる。この場合シリコン基板1
を底部3に内蔵される図示しないヒータで加熱すること
は、塩素イオンとの反応を促進し、基板結晶の損傷を少
なくするのに有効である。次いで反応室内のふん囲気を
ボンベ13からの酸素に切換え、波長800〜900貫
に透択された80R光(シンクロトロン軌道幅射光)1
4に、捌換え基板1の上を走査すると、高密度遠紫外光
で酸素イオンが生じ、同様に陽極板4と陰極板lOの間
に印加される直流バイアスにより加速されて基板1の上
面および溝12の内面に当たり、第2図(b)に示すよ
うに酸化シリコン膜15を生ずる。This light ionizes chlorine gas to produce chlorine ions. A power source 11 is provided between the cathode plate 10 surrounding the optical path and the anode plate 4.
By applying a DC bias, the chlorine ions are accelerated and collide with the silicon substrate 1, etching the substrate. Repeatedly scanning the beam of laser light 8
e of a predetermined shape and depth as shown in Figure 2 (,).
12 can be formed. In this case, silicon substrate 1
Heating with a heater (not shown) built into the bottom part 3 is effective in promoting the reaction with chlorine ions and reducing damage to the substrate crystal. Next, the atmosphere in the reaction chamber was changed to oxygen from the cylinder 13, and 80R light (synchrotron orbital beam radiation) 1 transmitted at a wavelength of 800 to 900 nm was added.
4, when the top of the replacement substrate 1 is scanned, oxygen ions are generated by high-density deep ultraviolet light, which are similarly accelerated by the DC bias applied between the anode plate 4 and the cathode plate IO, and are blown onto the top surface of the substrate 1 and A silicon oxide film 15 is formed on the inner surface of the groove 12, as shown in FIG. 2(b).
さらに反応室2内のfR素を排気したのち、ボンベ16
かもの5IH4ガス、ボンベ17からのHeガスを導入
し、人r レーザ光8により基板lの上を走査すると、
第2図(b)に示すように多結晶シリコン層18が堆積
する。溝12の内部以外の多結晶シリコン層18はこの
あとエツチングにより除去して表面を平滑化する(図C
)。このエツチングも溝12の形成と同様に元の照射に
よる垣累イオンエツチングによって行うことができる。Furthermore, after exhausting the fR element in the reaction chamber 2, the cylinder 16 is
Introducing Kamo 5 IH4 gas and He gas from cylinder 17 and scanning the substrate l with laser beam 8.
A polycrystalline silicon layer 18 is deposited as shown in FIG. 2(b). The polycrystalline silicon layer 18 outside the groove 12 is then removed by etching to smooth the surface (see Figure C).
). Similar to the formation of the grooves 12, this etching can also be performed by layered ion etching using the original irradiation.
このようにして分離層18を形成された基板にソース領
域19 、ドレイン領域加、グー)d化膜21を介して
の不純物なドープされた多結晶シリコンゲート22、ア
ルミニウム配&123を形成することにより絶縁分離1
m tsによって分離されたMO8)ランジスタ累子を
集積回路内&CM成することができる。酸化膜15は基
板と絶縁層の界閘の制御に役立つ、このために必要な不
純物尋人、酸化、多結晶81層あるいはAa?層の生成
を元CVD法あるいは光化学反応を利用して行うことが
できる。また溝の形成はC02ふん囲気中でAr レー
ザを用いたレーザ加工によってもよい。By forming a source region 19, a drain region, a polycrystalline silicon gate 22 doped with an impurity via a d-oxide film 21, and an aluminum interconnection layer 123 on the substrate on which the separation layer 18 has been formed in this manner. Insulation isolation 1
MO8) transistor resistors separated by m ts can be constructed within the integrated circuit &CM. The oxide film 15 serves to control the interface between the substrate and the insulating layer, and is made of impurity, oxide, polycrystalline 81 layer or Aa? The layer can be produced using a CVD method or a photochemical reaction. Further, the grooves may be formed by laser processing using an Ar laser in a CO2 atmosphere.
しかし溝の形成のみを光を用いて行い、酸化膜15を熱
酸化、あるいは充てん絶縁物をプラズマCVDKよって
形成することもできる。また表面の平滑化を液体による
エツチングによって行うこともできる。However, it is also possible to form only the grooves using light and to form the oxide film 15 by thermal oxidation or by forming the filling insulator by plasma CVDK. The surface can also be smoothed by etching with a liquid.
本発明は、半導体集積回路の素子間分離のための鴫の形
成を光イオン化によるイオンを打ち当てることによるエ
ツチングあるいはレーザ加工などの光の照射により行う
ことにより、半導体基板の結晶に、損傷を与えることが
少なく、マスクパターニングの必要なしに幅の狭い分離
層を形成することができる。さらに溝内の絶縁物の充て
んも同一反応室で光の照射によって行うことかできるた
め、基板の清浄の保持が容易であるなど、高集植展の半
導体集積回路の製造に対する効果は大きい。The present invention damages the crystals of the semiconductor substrate by performing etching by bombarding ions by photoionization or irradiation with light such as laser processing to form a dot for separating elements of a semiconductor integrated circuit. Therefore, a narrow separation layer can be formed without the need for mask patterning. Furthermore, since the filling of the insulating material in the groove can be performed in the same reaction chamber by irradiation with light, it is easy to maintain the cleanliness of the substrate, which has a great effect on the production of semiconductor integrated circuits with high concentration.
第1図は本発明の−・実施例のための装置の断面口、第
2図は本発明の一実施例の工程を11次示す断面図であ
る。
1・・・シリコン基板、2・・・反応室、4・・・lQ
N&:板、6・−塩素ボンベ、8・= Ar レーザ光
、10・・・陰極板、12・・・溝、13−・酸素ボン
ベ、14・−5OR光、15・・・酸化i、16・・・
5i)I4ボンベ、17・・・Heボンベ、 1B・・
・多結晶シリコン層。
画人!+埋上 山 口 忌
第1図FIG. 1 is a cross-sectional view of an apparatus for an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing an eleventh step of the process of an embodiment of the present invention. 1... Silicon substrate, 2... Reaction chamber, 4... lQ
N&: plate, 6.-chlorine cylinder, 8.=Ar laser beam, 10.. cathode plate, 12.. groove, 13-. oxygen cylinder, 14.-5 OR light, 15.. oxidation i, 16 ...
5i) I4 cylinder, 17...He cylinder, 1B...
・Polycrystalline silicon layer. artist! + Burial of Yamaguchi's death Figure 1
Claims (1)
分離層を有する半導体集積回路の製造方法において、元
ビームの照射により半導体基板を加工して溝を形成する
ことを特徴とする半導体集積回路の製造方法。 2、特許請求の範囲第1項記載の方法において、半導体
基板の加工を光イオン化によって生じたイオンを電界に
より基板に向けて加速することにより行うことを特徴と
する半導体集積回路の製造方法。 3)%許請求の範囲第1項記載の方法において、半導体
基板の加工をレーザ加工によって行うことを特徴とする
半導体集積回路の製造方法。 4)特許請求の範囲第1項ないし第3項のいずれかに記
載された方法において、形成された溝の中に充てんされ
る絶縁物を光化学反応により生成することを特徴とする
半導体集積回路の製造方法。[Claims] 1) In a method for manufacturing a semiconductor integrated circuit having a separation layer formed by filling a groove dug in a semiconductor substrate with an insulating material, the semiconductor substrate is processed by irradiation with an original beam to form the groove. A method for manufacturing a semiconductor integrated circuit, characterized by: 2. A method for manufacturing a semiconductor integrated circuit according to claim 1, wherein the semiconductor substrate is processed by accelerating ions generated by photoionization toward the substrate using an electric field. 3) % Permissible A method for manufacturing a semiconductor integrated circuit according to claim 1, characterized in that the semiconductor substrate is processed by laser processing. 4) A semiconductor integrated circuit characterized in that, in the method according to any one of claims 1 to 3, an insulator filled in the formed groove is produced by a photochemical reaction. Production method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7327984A JPS60216564A (en) | 1984-04-12 | 1984-04-12 | Manufacture of semiconductor ic |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7327984A JPS60216564A (en) | 1984-04-12 | 1984-04-12 | Manufacture of semiconductor ic |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60216564A true JPS60216564A (en) | 1985-10-30 |
Family
ID=13513542
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7327984A Pending JPS60216564A (en) | 1984-04-12 | 1984-04-12 | Manufacture of semiconductor ic |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60216564A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62230024A (en) * | 1986-03-31 | 1987-10-08 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
-
1984
- 1984-04-12 JP JP7327984A patent/JPS60216564A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62230024A (en) * | 1986-03-31 | 1987-10-08 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
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