JPS6021599A - Method of producing multilayer wiring board - Google Patents
Method of producing multilayer wiring boardInfo
- Publication number
- JPS6021599A JPS6021599A JP12980983A JP12980983A JPS6021599A JP S6021599 A JPS6021599 A JP S6021599A JP 12980983 A JP12980983 A JP 12980983A JP 12980983 A JP12980983 A JP 12980983A JP S6021599 A JPS6021599 A JP S6021599A
- Authority
- JP
- Japan
- Prior art keywords
- metal foil
- circuit
- wiring board
- multilayer wiring
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Laminated Bodies (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 ［技術分野］ 本発明は多層配線基板の製造方法に関するものである。[Detailed description of the invention] [Technical field] The present invention relates to a method for manufacturing a multilayer wiring board.
し背景技術］
従来、この種の多層配線基板を製造するにあたっては、
第１図（ａ）乃至（ｃ）に示すように表面にバターシ状
に回路（１）が形成された基板（２）の表面にスルーホ
ール（３）が穿孔された電気絶縁層付金属箔（４）を載
置すると共にスルーホール（３）と回Ｍ （Ｉ＋とを位
置合わせし、次いでこれらのものを成形プレート間にセ
ットして加熱加Ｅ ［Ｎ−ｊることによって積層一体化
し、その後表面側より半田吟の導電材料（７）をスルー
ホール部（６）に充填して回路（１）と表面の金属箔（
６）と？電気的に接続させることによって多層配線基板
を製造している。ところが、第２図に示すように加熱成
形時に電気絶縁層ａ場の樹脂がスルーホール部（６）内
に流れ込むために半田が分離したり又半田の接続不良が
発生し易く、そのため第１層と第２＃の回路間のスルー
ホール接続の信頼性が低いという欠点があった。Background technology] Conventionally, in manufacturing this type of multilayer wiring board,
As shown in FIGS. 1(a) to (c), a metal foil with an electrically insulating layer ( 4) and align the through hole (3) and the turn M (I+), then set these between the molding plates and heat them to integrate them by laminating them, and then Fill the through hole part (6) with conductive material (7) of Handa Gin from the front side to connect the circuit (1) and the metal foil on the surface (
6) And? Multilayer wiring boards are manufactured by making electrical connections. However, as shown in Fig. 2, the resin in the electrical insulating layer a flows into the through-hole part (6) during heat molding, which tends to cause separation of the solder or poor solder connection. There was a drawback that the reliability of the through-hole connection between the #2 and #2 circuits was low.
［発明の目的］
不発りＪは上記の点に鑑みて成されπものであって、第
１＃と第２層の回路間のスルーホール接続の信頼性を向
上することができる多層配線基板の製造方法ケ提供する
ことを目的とするものであゐ［発明の開示〕
すなわち、本発明は表面に回路ｆｌ＋が形成された基板
（２）の表面にスルーホール（３）が穿孔された電気絶
縁層付金属箔（４）を金属箔（６１が表面側にくるよう
に載置すると共にスルーホール（３）全回路［１１位置
に合わせ、次いで基板（２）と電気絶縁層付金属箔（４
）？成形プレート間にセットして加熱加圧成形し、その
後スルーホール部（６）に導電材料（７）？充填して回
路＋１１と金属箔（５）と全接続せしめた多層配線基板
の製造方法であってミ電気絶縁層付金属箔（４）のスル
ーホール（３）エリも大きい開口部（８）が穿孔された
絶縁材（９）を開口部（８）が回路＋１１上に位置する
ように基板（２）と箱、気絶縁層付金属箔（４）との間
に挿入して積層成形することを特徴とする多層配線基板
の製造方法により上記目的を達成したものである。[Object of the Invention] The misfire J was made in view of the above points, and is a multilayer wiring board that can improve the reliability of through-hole connection between the first # and second layer circuits. DISCLOSURE OF THE INVENTION That is, the present invention provides an electrical insulator in which a through hole (3) is formed on the surface of a substrate (2) on which a circuit fl+ is formed. Place the layered metal foil (4) so that the metal foil (61 is on the front side) and align the through hole (3) with the entire circuit [11], then place the metal foil (4) on the board (2) and the electrically insulating layered metal foil (4).
)? The conductive material (7) is placed between the molding plates and heated and pressed, and then the conductive material (7) is placed in the through hole (6). A method for manufacturing a multilayer wiring board in which a circuit +11 and a metal foil (5) are fully connected by filling the through hole (3) of the metal foil (4) with an electrically insulating layer and a large opening (8). Insert the perforated insulating material (9) between the substrate (2), the box, and the metal foil with an insulating layer (4) so that the opening (8) is located above the circuit +11, and perform lamination molding. The above object has been achieved by a method for manufacturing a multilayer wiring board characterized by the following.
以下本発明を第５図以下の実施例により詳述する。基板
（２）としては、何ら限定するものではないが例えば金
属ベース基板、横１旨基板、フレ千シづル基板、あるい
はそれらの片面基板、両面基板、多層基板等を使用する
ことができ、表面には第５図（ａ）に示すように銅箔等
で形成されπ回路ｆｉｌがパターン形状に形成しである
。この基板（２）の上に第３図（ｂ）に示すように開口
部（８）が穿孔された絶縁材（９）を載置する。この絶
縁材（９）としては、紫外線硬化樹脂や熱硬化性樹脂、
プリプレグ又はポジディジタシート等で形成することが
でき、１に開口部（８）の大きさは基板（２）の（ロ）
路（１１の巾よりもやや小さく形成してあって、開口部
（８）が回路（１）上に位置するように絶縁材（９）全
基板（２）上に載置するものである。次に第３図（ｅ）
に示すようにスルーホール（３）が穿孔された電、気絶
縁層付金属箔（４）會その金属箔（５）が表面側にくる
ように絶縁材（９）上に重ねると共にスルーホール（３
）全基板（２７の回路＋ＩＩに位置合わせる。ここで、
金属箔（６）としては銅箔を使用することができ、また
電気絶縁層（１騰としては樹脂層やプリプレグ等で形成
することができる。次に、このようにして積載した基板
（２）、絶縁材（９）、電気絶縁層付金属箔（４＋ｉそ
れぞれ成形プレート間にセットすると共に最上面の金属
箔（５）と成形プレートとの間にクッション材（Ｉｌｌ
Ｔｈ介挿した状態で加熱加圧成形し、基板（２１、絶
枢材（９）及び電気絶縁層付金属箔（４）全積層一体化
するものである。スルーホール部（６）では電気絶縁層
付金属ｆｆｉ＋４１の開口周縁が第５図（ｄ）のように
下方に屈曲して表向の金属箔（５）先端が回路（１１と
接する工うにな石。次いで、第４図に示すように表面側
より牛１１Ｊ等の導電材料（７）をスルーホール部（８
）に充填して回路１１）と金属箔］５）とを電気的に接
続するものである。The present invention will be explained in detail below with reference to the embodiments shown in FIG. 5 and below. As the substrate (2), for example, a metal base substrate, a horizontal single-sided substrate, a flexible substrate, a single-sided substrate, a double-sided substrate, a multilayer substrate, etc. thereof can be used, but there is no limitation. On the surface, as shown in FIG. 5(a), a π circuit fil made of copper foil or the like is formed in a pattern shape. As shown in FIG. 3(b), an insulating material (9) with an opening (8) perforated therein is placed on the substrate (2). This insulating material (9) includes ultraviolet curing resin, thermosetting resin,
It can be formed from prepreg or positive digitizer sheet, etc., and the size of the opening (8) in 1 is the same as (b) of the substrate (2).
The insulating material (9) is formed to be slightly smaller than the width of the circuit (11), and is placed on the entire substrate (2) so that the opening (8) is located above the circuit (1). Next, Figure 3(e)
As shown in the figure, a metal foil (4) with an electrically or electrically insulating layer with a through hole (3) is placed on top of the insulating material (9) so that the metal foil (5) is on the front side, and the through hole ( 3
) Align all boards (27 circuits + II. Here,
Copper foil can be used as the metal foil (6), and the electrical insulating layer (1) can be formed of a resin layer, prepreg, etc.Next, the substrate (2) loaded in this way , an insulating material (9), a metal foil with an electrically insulating layer (4+i) are set between the molding plates, and a cushioning material (Ill) is placed between the uppermost metal foil (5) and the molding plate.
The board (21), the integral member (9), and the metal foil with an electrically insulating layer (4) are all laminated into one piece by heating and press molding with the Th inserted.The through hole part (6) is electrically insulated. The opening periphery of the layered metal ffi+41 is bent downward as shown in FIG. 5(d), and the tip of the metal foil (5) on the front side is in contact with the circuit (11).Next, as shown in FIG. From the surface side, insert a conductive material (7) such as Ushi 11J into the through hole part (8
) to electrically connect the circuit 11) and the metal foil]5).
しかして、電気絶縁層付金属箔（４）のスルーホール（
３）エリも大きい開口部（８）を有する絶縁材（９）４
基板１２ノと電気絶縁層付金属箔（４）との間に挿入し
た状態で積層成形することにより、金属箔（６）のスル
ーホール（３）の開口周縁が屈曲して電気絶縁層０３）
の樹脂がスルーホール部（６）内に流れ込むの全防止す
ることができ、従ってその後スルーホール部（６）内に
充填された半田等の導電材料（７）が分離するというこ
とがないものであり、しかも回路＋１１と表面の金属箔
（５）とを導電材料（７）で確実に電気接続することが
できるものである。このようにして形成された多層配線
基板はその後表面の金属箔（５）をパターン形状にエツ
チングして別の回路が形成される。However, the through hole (
3) Insulating material (9) 4 with a large opening (8)
By laminating and molding the metal foil (4) with an electrically insulating layer inserted between the substrate 12 and the electrically insulating layer, the opening periphery of the through hole (3) in the metallic foil (6) is bent and the electrically insulating layer 03) is formed.
It is possible to completely prevent the resin from flowing into the through-hole portion (6), and therefore there is no possibility that the conductive material (7) such as solder filled in the through-hole portion (6) will separate afterwards. Moreover, it is possible to reliably electrically connect the circuit +11 and the metal foil (5) on the surface using the conductive material (7). After that, the metal foil (5) on the surface of the multilayer wiring board thus formed is etched into a pattern to form another circuit.
を発明の効果〕
上記のように本発明は電気絶縁層付金属箔のスルーホー
ル接続も大きい開口部が穿孔された絶縁材を開口部が回
路上に位置するように基板と電気絶縁層付金属箔との間
に挿入して積層成形したので、電気絶縁層付金属箔のス
ルーホールの開口周縁が屈曲して金属箔が回路表面に接
続すると共に電気絶縁層の樹脂が回路上へ流れ込むのを
防止することができ、このスルーホール部に充填された
導電材料で第１層の回路と第２層の金属箔とを確実に接
続することができてスルーホール接続の侶軸性を向」二
することができるものである。[Effects of the Invention] As described above, the present invention enables through-hole connection of metal foil with an electrically insulating layer, and connects an insulating material with a large opening to a substrate and a metal with an electrically insulating layer so that the opening is located on the circuit. Because the metal foil with the electrically insulating layer is inserted between the foil and laminated, the opening edge of the through hole in the metal foil with the electrically insulating layer bends, connecting the metal foil to the circuit surface and preventing the resin of the electrically insulating layer from flowing onto the circuit. The conductive material filled in this through-hole section can reliably connect the circuit on the first layer and the metal foil on the second layer, thereby reducing the axial nature of the through-hole connection. It is something that can be done.
４．し１面のＩＶ１］里な脱り４
第１図（ａ）乃至（ｃ）は従来例の製造法會示す一部切
欠断面図、第２図は同上の問題点を示−ｊ要部拡大断面
図、第３図（ａ）乃至（ｄ）け不発Ｆｊ１１一実施例の
一部切欠断面図、第４図は同上の要部拡大断面図である
。4. Page 1 IV1] Sato Nadori 4 Figures 1 (a) to (c) are partially cutaway cross-sectional views showing the conventional manufacturing method, and Figure 2 shows the same problems as above - j Enlarged view of main parts 3(a) to 3(d) are partially cutaway sectional views of one embodiment of the unexploded Fj11, and FIG. 4 is an enlarged sectional view of the same essential parts.
（１）は回路、（２）は基板、＋８１ Ｖｉミスルーホ
ール（４）は電気絶縁廣付金属箔、＋５＋は金属箔、（
６）はスルーホール部、（７）は導電材料、（８）は開
口部、（９）は絶縁材である。(1) is a circuit, (2) is a board, +81 Vi miss through hole (4) is a metal foil with electrical insulation, +5+ is a metal foil, (
6) is a through-hole portion, (7) is a conductive material, (8) is an opening, and (9) is an insulating material.
代理人 弁理士 石 １）長 七 （７） 第１図 第２図 ２Agent Patent Attorney Ishi 1) Choshichi (7) Figure 1 Figure 2 2
Claims (2)
ルが穿孔された電気絶縁層付金属箔を金属箔が表面側に
くるように載置すると共にスルーホール？回路位買に合
わせて、次いで基板と電気絶縁層付金属箔全成形プレー
ト間にセットして加熱加圧成形し、その後スルーホール
部に導電相別全充填して回路と金属箔とを接続せしめた
多層配線基板の製造方法であって、電、気絶線層付金属
箔のスルーホールよりも大きい開口部が穿孔された絶縁
材を開口部が回路上に位階するように基板と電気絶縁層
付金属箔との間に挿入してｍ層成形すること全特徴とす
る多層配線基板の製造方法。(1) Place a metal foil with an electrically insulating layer on the surface of a board on which a circuit is formed, with a through hole punched therein, so that the metal foil is on the front side, and place the metal foil on the surface of the board with a circuit formed thereon. According to the circuit position, it is then placed between the board and the fully formed plate of the metal foil with an electrically insulating layer, and heated and pressed, and then the through holes are completely filled by conductive phase to connect the circuit and the metal foil. A method for manufacturing a multilayer wiring board, comprising: forming an insulating material with an opening larger than a through hole in a metal foil with an electrical insulation layer on the board and an electrical insulation layer in such a way that the opening is located above the circuit; A method for manufacturing a multilayer wiring board, which is characterized in that m layers are formed by inserting the wiring board between metal foils.
ショシ材會介挿して加熱加圧成形することｔ特徴とする
特許請求の範囲第１項記載の多層配線基板の製造方法。(2) A method for manufacturing a multilayer wiring board according to claim 1, characterized in that a cushioning material is inserted between the molding plate and the metal foil with an electrically insulating layer and the molding is performed under heat and pressure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12980983A JPS6021599A (en) | 1983-07-15 | 1983-07-15 | Method of producing multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12980983A JPS6021599A (en) | 1983-07-15 | 1983-07-15 | Method of producing multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6021599A true JPS6021599A (en) | 1985-02-02 |
| JPH0359597B2 JPH0359597B2 (en) | 1991-09-11 |
Family
ID=15018754
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12980983A Granted JPS6021599A (en) | 1983-07-15 | 1983-07-15 | Method of producing multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6021599A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5648442A (en) * | 1991-07-05 | 1997-07-15 | Biocompatibles Limited | Polymeric surface coatings |
| US5705583A (en) * | 1991-07-05 | 1998-01-06 | Biocompatibles Limited | Polymeric surface coatings |
| US6090901A (en) * | 1991-07-05 | 2000-07-18 | Biocompatibles Limited | Polymeric surface coatings |
| US6420453B1 (en) | 1990-10-29 | 2002-07-16 | Biocompatibles Limited | Contact lens material |
| US6743878B2 (en) | 1991-07-05 | 2004-06-01 | Biocompatibles Uk Limited | Polymeric surface coatings |
| US6769871B2 (en) | 2001-08-13 | 2004-08-03 | Sun Medical Technology Research Corporation | Blood pump and ventricular assist device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54159664A (en) * | 1978-06-07 | 1979-12-17 | Shin Kobe Electric Machinery | Method of producing printed circuit board |
| JPS5797970U (en) * | 1980-12-08 | 1982-06-16 |
-
1983
- 1983-07-15 JP JP12980983A patent/JPS6021599A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54159664A (en) * | 1978-06-07 | 1979-12-17 | Shin Kobe Electric Machinery | Method of producing printed circuit board |
| JPS5797970U (en) * | 1980-12-08 | 1982-06-16 |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6420453B1 (en) | 1990-10-29 | 2002-07-16 | Biocompatibles Limited | Contact lens material |
| US6423761B1 (en) | 1990-10-29 | 2002-07-23 | Biocompatibles Limited | Contact lens material |
| US5648442A (en) * | 1991-07-05 | 1997-07-15 | Biocompatibles Limited | Polymeric surface coatings |
| US5705583A (en) * | 1991-07-05 | 1998-01-06 | Biocompatibles Limited | Polymeric surface coatings |
| US5783650A (en) * | 1991-07-05 | 1998-07-21 | Biocompatibles Limited | Polymeric surface coatings |
| US6090901A (en) * | 1991-07-05 | 2000-07-18 | Biocompatibles Limited | Polymeric surface coatings |
| US6743878B2 (en) | 1991-07-05 | 2004-06-01 | Biocompatibles Uk Limited | Polymeric surface coatings |
| US7160953B2 (en) | 1991-07-05 | 2007-01-09 | Biocompatibles Uk Limited | Polymeric surface coatings |
| US6769871B2 (en) | 2001-08-13 | 2004-08-03 | Sun Medical Technology Research Corporation | Blood pump and ventricular assist device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0359597B2 (en) | 1991-09-11 |
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