JPS6021598A - Method of producing multilayer wiring board - Google Patents

Method of producing multilayer wiring board

Info

Publication number
JPS6021598A
JPS6021598A JP12980883A JP12980883A JPS6021598A JP S6021598 A JPS6021598 A JP S6021598A JP 12980883 A JP12980883 A JP 12980883A JP 12980883 A JP12980883 A JP 12980883A JP S6021598 A JPS6021598 A JP S6021598A
Authority
JP
Japan
Prior art keywords
metal foil
electrically insulating
substrate
insulating layer
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12980883A
Other languages
Japanese (ja)
Other versions
JPH0359595B2 (en
Inventor
徹 樋口
村上 久男
武司 加納
慧 森本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP12980883A priority Critical patent/JPS6021598A/en
Publication of JPS6021598A publication Critical patent/JPS6021598A/en
Publication of JPH0359595B2 publication Critical patent/JPH0359595B2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は多層配線基板の製造方法に関するものである。[Detailed description of the invention] 〔Technical field〕 The present invention relates to a method for manufacturing a multilayer wiring board.

〔背景技術〕[Background technology]

従来より、この種の多層配線基板を製造するにあたって
は、第1図fa)乃至(e)に示すように表面に回II
 (11が形成された基板(2)上にスルーホール]3
)が穿孔された電気絶縁層付金属箔(4)を重ね合わせ
て回路(11とスルーホール(3)との位置を合わせ、
次いでこの状態で基&(2)と電気絶縁層付金属箔(4
)とを成形プレート間に挟んで加熱加圧成形することに
゛より積層一体化し、その後スルーホール)3)内に半
田等の導電材料(6)を充填して回路(1)と金属箔(
5)とを電気的に接続しているものであった。しかし乍
ら、この方法では基板(2)と電気絶縁層付金属箔(4
)とを成形する際に、回路(1)を形成する銅箔の表面
が空気酸化されるという問題があり、そのためその後こ
のスルーホール(31内に導電材料(6)を充填して回
路(1)と表面の金属箔(5)とを接続させる場合に信
頼性に欠けるという欠点があった。
Conventionally, when manufacturing this type of multilayer wiring board, as shown in FIG.
(Through hole on the substrate (2) on which 11 is formed) 3
) are perforated with an electrically insulating layer (4), and the circuit (11) and the through hole (3) are aligned,
Next, in this state, base & (2) and metal foil with electrical insulating layer (4
) are sandwiched between molding plates and heated and pressure-molded to form an integrated layer.Then, the through holes (3) are filled with conductive material (6) such as solder to bond the circuit (1) and the metal foil (6).
5) were electrically connected. However, in this method, the substrate (2) and the metal foil with an electrically insulating layer (4)
), there is a problem that the surface of the copper foil that forms the circuit (1) is oxidized in the air, so the through hole (31) is then filled with conductive material (6) to form the circuit (1). ) and the metal foil (5) on the surface are unreliable.

〔発明の目的〕[Purpose of the invention]

本発明は上記の点に鑑みて成されたものであって九成形
時に回路表面が酸化されるのを防止することによって信
頼性を高めることができる多層配線基板の製造方法を提
V(することを目的とするものである。
The present invention has been made in view of the above points, and provides a method for manufacturing a multilayer wiring board that can improve reliability by preventing the circuit surface from being oxidized during molding. The purpose is to

〔発明の開示〕[Disclosure of the invention]

すなわち、本発明は表面に回路filが形成された基板
(2)の表面にスルーホール(3)が穿孔された電気絶
縁層付金属箔(4)を金属箔(5)が表面側にくるよう
に載置すると共にスルーホール(3)を回路(1)位置
に合わせ、次いで電気絶縁層付金属箔(4)を基板(2
)に仮接着し、次にスルーホール(3)内に導電材料を
充填し、その後基板(2)と電気絶縁層付金属箔(4)
を成形プレート間に挟んで積層成形することを特徴とす
る多層配線基板の製造方法によシ上記目的を達成したも
のである。
That is, in the present invention, a metal foil (4) with an electrically insulating layer, which has through holes (3) formed on the surface of a substrate (2) on which a circuit film is formed, is placed so that the metal foil (5) is on the surface side. Place the metal foil (4) with an electrically insulating layer on the circuit board (2) and align the through hole (3) with the circuit (1) position.
), then fill the through hole (3) with a conductive material, and then bond the substrate (2) and the metal foil with an electrically insulating layer (4).
The above object has been achieved by a method of manufacturing a multilayer wiring board, which is characterized in that the multilayer wiring board is sandwiched between molding plates and laminated and molded.

以下本発明を実施例により詳述する。基板(2)として
は金属ベース基板、樹脂基板、フレナシプル基板、又は
それらの片面基板、両面基板、多層基板等を使用するこ
とができ、限定するものではない。この基板(2)の表
面には第2図(a)に示すように回v&fl)が形成し
である。基板(2)の上に第2図(b)に示すようにス
ルーホール(3)が穿孔された電気絶縁層付金属箔(4
)を金属箔(5)が表面側にくるように重ねて載置する
と共にスルーホ」ル(3)を回路fl)位置に合わせる
。ここで、金属箔(5)としては銅箔で形成することが
でき、また電気絶縁層03)としてfi紫外線硬化樹脂
や熱可塑性樹脂等の樹脂層やプリプレグ、ボンヂイシジ
シート等で形成することができる。次に、この基板(2
)と電気絶縁層付金属箔(4)を一対の成Iビプし一ト
間にセラ)・シて電気絶縁層(13)の硬化に不十分な
熱を加える等で電気絶縁層付金属箔(4)を基板(2)
に仮接着させる。次に、第2図(blに示すように表面
よりスルーホール(3)内に半田ペースト、導電ペース
ト等の導電材料(6)を印刷、あるいは塗布等の方法で
埋め込み、その後必要に応じて基板(2)をやや加熱し
て半田ペースト等の導電材$+181中の離削を蒸発さ
せ、その後さらに基板(2)と電気絶縁層付金属箔(4
)とを電気絶縁層(1萄の完全硬化に十分な熱を加えて
加熱加圧成形するものである。その際の加熱温度は上記
導電材料(6)の溶融温度又はそれ以上の温度で成形す
るのが望ましい。このようにして基板(2)に電気絶縁
層付金属箔(4)が積層一体化された多層配線基板Aを
得るものである。
The present invention will be explained in detail below with reference to Examples. As the substrate (2), a metal base substrate, a resin substrate, a flexible substrate, a single-sided substrate, a double-sided substrate, a multilayer substrate, etc. thereof can be used, and the present invention is not limited thereto. As shown in FIG. 2(a), grooves (v&fl) are formed on the surface of this substrate (2). A metal foil (4) with an electrically insulating layer is formed on the substrate (2) with through holes (3) as shown in FIG.
) are placed on top of each other so that the metal foil (5) is on the front side, and the through hole (3) is aligned with the circuit fl) position. Here, the metal foil (5) can be formed of copper foil, and the electrical insulating layer 03) can be formed of a resin layer such as fi ultraviolet curing resin or thermoplastic resin, prepreg, bondi-shiji sheet, etc. be able to. Next, this board (2
) and the metal foil with the electrically insulating layer (4) are put together in a pair, and the metal with the electrically insulating layer is heated by applying insufficient heat to harden the electrically insulating layer (13). Foil (4) to substrate (2)
Temporarily adhere to. Next, as shown in Figure 2 (bl), a conductive material (6) such as solder paste or conductive paste is embedded into the through hole (3) from the surface by printing or coating, and then the substrate is coated as necessary. (2) is slightly heated to evaporate the abrasions in the conductive material such as solder paste, and then the substrate (2) and the metal foil with an electrically insulating layer (4) are heated.
) and the electrically insulating layer (1 layer) is heat-pressed and molded by applying sufficient heat to completely cure the electrically insulating layer.The heating temperature at that time is the melting temperature of the above-mentioned conductive material (6) or higher. In this way, a multilayer wiring board A is obtained in which the electrically insulating layer-coated metal foil (4) is laminated and integrated on the board (2).

しかして、基板(2)と電気絶縁層付金属箔(4)とを
積層成形するにあたって、予め基板(2)に電気絶縁層
付金属箔(4)を仮接着した状態でスルーホール(3)
内に導電材料(6)を充填しておくことによシ、その後
の加熱加圧成形時に基板(2)の回路f1表面が導電材
料(6)で保護されていて酸化されるということがない
ものである。また、半田ペースト等の4電材料(6)で
スルーホール(3)を埋め込むことにより、スルーホー
ル(3j内に空気が入るのを防ぐことができて信頼性を
高めることができるものである。さらに、スルーホール
(3)をとるために半田ペーストの印刷がし易く、スル
ーホール信頼性を高めることができるものである。また
、このように形成された多層配線基板A表面に2層目の
回路を形成する場合には、エッチシフレジストが半田ペ
ーストによく密着し、エツチシタ時にスルーホールラン
ドの保護が完全に行なえる。ものである。
Therefore, when laminating and molding the substrate (2) and the metal foil with an electrically insulating layer (4), the through holes (3) are formed while the metal foil with an electrically insulating layer (4) is temporarily bonded to the substrate (2) in advance.
By filling the inside with the conductive material (6), the surface of the circuit f1 of the substrate (2) is protected by the conductive material (6) and will not be oxidized during subsequent heating and pressure molding. It is something. Furthermore, by filling the through hole (3) with a four-electrode material (6) such as solder paste, it is possible to prevent air from entering the through hole (3j) and improve reliability. Furthermore, it is easy to print solder paste to form the through holes (3), and the reliability of the through holes can be improved.Also, a second layer is applied to the surface of the multilayer wiring board A formed in this way. When forming a circuit, the etch resist adheres well to the solder paste, and the through-hole lands can be completely protected during etching.

〔発明の効果〕〔Effect of the invention〕

上記のように本発明は、表面に回路が形成された基板の
表面にスルーホールが穿孔された電気絶縁層付金属iを
金属箔が表面側にくるように載置すると共にスルーホー
ルを回路位置に合わせ、次いで電気絶縁層付金属箔を基
板に仮接着し、次にスルーホール病に導電材料を充填し
、その後基板と電気絶縁層付金属箔を成形づレート間に
挟んで積層成形したので、予めスルーホール内に導電材
料を充填することにより基板の回路表面を導電材料で保
展することができ、成形時に回路の表面が酸化されるの
を防止することができて半田でスルーホールをとる場合
の信頼性を高めることができるものである。
As described above, the present invention involves placing a metal i with an electrically insulating layer on which a through hole is formed on the surface of a substrate on which a circuit is formed so that the metal foil is on the surface side, and placing the through hole at the circuit position. Next, the metal foil with an electrically insulating layer was temporarily bonded to the board, and then the through-hole was filled with a conductive material, and then the board and the metal foil with an electrically insulating layer were sandwiched between molding plates and laminated. By filling the through holes with a conductive material in advance, the circuit surface of the board can be protected with the conductive material, and the circuit surface can be prevented from being oxidized during molding. This can improve reliability when

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a) (b)(c)は従来例の製造法を示す要
部断面図、第2図(a) (b) (c)は本発明−実
施例の要部断面図である。 111は回路、(2)は基板、(3)はスルーホール、
(4)は電気絶縁層付金属箔、(6)は金属箔、(6)
は導電材料である。 代理人 弁理士 石 1)兼 七
FIGS. 1(a), (b), and (c) are sectional views of essential parts showing a conventional manufacturing method, and FIGS. 2(a), (b), and (c) are sectional views of essential parts of an embodiment of the present invention. . 111 is a circuit, (2) is a board, (3) is a through hole,
(4) is metal foil with electrical insulation layer, (6) is metal foil, (6)
is a conductive material. Agent Patent Attorney Ishi 1) Kenshichi

Claims (1)

【特許請求の範囲】[Claims] +1)表面に回路が形成された基板の表面にスルーホー
ルが穿孔された電気絶縁層付金属箔を金属箔が表面側に
くるように載置すると共にスルーホールを回路位置に合
わせ、次いで電気絶縁層付金属箔を基板に仮接着し、次
にスルーホール内に導電材料を充填し、その後基板と電
気絶縁層付金属箔を成形プレート間に挟んで積層成形す
ることを特徴とする多層配線基板の製造方法。
+1) Place the metal foil with an electrically insulating layer on the surface of the board with the circuit formed on its surface so that the metal foil is on the surface side, align the through hole with the circuit position, and then remove the electrically insulating layer. A multilayer wiring board characterized in that a layered metal foil is temporarily bonded to a substrate, a conductive material is then filled in the through holes, and then the substrate and the electrically insulating layered metal foil are sandwiched between molding plates and laminated and molded. manufacturing method.
JP12980883A 1983-07-15 1983-07-15 Method of producing multilayer wiring board Granted JPS6021598A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12980883A JPS6021598A (en) 1983-07-15 1983-07-15 Method of producing multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12980883A JPS6021598A (en) 1983-07-15 1983-07-15 Method of producing multilayer wiring board

Publications (2)

Publication Number Publication Date
JPS6021598A true JPS6021598A (en) 1985-02-02
JPH0359595B2 JPH0359595B2 (en) 1991-09-11

Family

ID=15018729

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12980883A Granted JPS6021598A (en) 1983-07-15 1983-07-15 Method of producing multilayer wiring board

Country Status (1)

Country Link
JP (1) JPS6021598A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009113602A1 (en) * 2008-03-13 2009-09-17 株式会社村田製作所 Method for manufacturing a resin substrate and a resin substrate

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54159664A (en) * 1978-06-07 1979-12-17 Shin Kobe Electric Machinery Method of producing printed circuit board
JPS5797970U (en) * 1980-12-08 1982-06-16

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54159664A (en) * 1978-06-07 1979-12-17 Shin Kobe Electric Machinery Method of producing printed circuit board
JPS5797970U (en) * 1980-12-08 1982-06-16

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009113602A1 (en) * 2008-03-13 2009-09-17 株式会社村田製作所 Method for manufacturing a resin substrate and a resin substrate

Also Published As

Publication number Publication date
JPH0359595B2 (en) 1991-09-11

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