JPH0359595B2 - - Google Patents
Info
- Publication number
- JPH0359595B2 JPH0359595B2 JP58129808A JP12980883A JPH0359595B2 JP H0359595 B2 JPH0359595 B2 JP H0359595B2 JP 58129808 A JP58129808 A JP 58129808A JP 12980883 A JP12980883 A JP 12980883A JP H0359595 B2 JPH0359595 B2 JP H0359595B2
- Authority
- JP
- Japan
- Prior art keywords
- metal foil
- insulating layer
- electrically insulating
- circuit
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000002184 metal Substances 0.000 claims description 36
- 229910052751 metal Inorganic materials 0.000 claims description 36
- 239000011888 foil Substances 0.000 claims description 35
- 239000004020 conductor Substances 0.000 claims description 14
- 238000000465 moulding Methods 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 description 23
- 229910000679 solder Inorganic materials 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 239000011889 copper foil Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
Landscapes
- Laminated Bodies (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
〔技術分野〕
本発明は多層配線基板の製造方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for manufacturing a multilayer wiring board.
従来より、この種の多層配線基板を製造するに
あたつては、第１図ａ乃至ｃに示すように表面に
回路１が形成された基板２上にスルーホール３が
穿孔された電気絶縁層付金属箔４を重ね合わせて
回路１のスルーホール３との位置を合わせ、次い
でこの状態で基板２と電気絶縁層付金属箔４とを
成形プレート間に挟んで加熱加圧成形することに
より一層一体化し、その後スルーホール３内に半
田等の導電材料６を充填して回路１と金属箔５と
を電気的に接続しているものであつた。しかし乍
ら、この方法では基板２と電気絶縁層付金属箔４
とを成形する際に、回路１を形成する銅箔の表面
が空気酸化されるという問題があり、そのためそ
の後このスルーホール３内に導電材料６を充填し
て回路１と表面の金属箔６とを接続させる場合に
信頼性に欠けるという欠点があつた。
Conventionally, when manufacturing this type of multilayer wiring board, as shown in FIGS. The coated metal foils 4 are overlapped and aligned with the through holes 3 of the circuit 1, and then, in this state, the substrate 2 and the electrically insulating layer coated metal foils 4 are sandwiched between molding plates and heated and press-molded to further improve the shape. The circuit 1 and the metal foil 5 were electrically connected by integrating the circuit 1 and the metal foil 5 by filling the through hole 3 with a conductive material 6 such as solder. However, in this method, the substrate 2 and the metal foil 4 with an electrically insulating layer are
When molding the circuit 1, there is a problem that the surface of the copper foil forming the circuit 1 is oxidized in the air, so after that, the through hole 3 is filled with a conductive material 6 and the circuit 1 and the surface metal foil 6 are formed. The disadvantage was that it lacked reliability when connecting.
本発明は上記の点に鑑みて成されたものであつ
て、成形時に回路表面が酸化されるのを防止する
ことによつて信頼性を高めることができる多層配
線基板の製造方法を提供することを目的とするも
のである。
The present invention has been made in view of the above points, and it is an object of the present invention to provide a method for manufacturing a multilayer wiring board that can improve reliability by preventing the circuit surface from being oxidized during molding. The purpose is to
すなわち、本発明は表面に回路１が形成された
基板２の表面にスルーホール３が穿孔された電気
絶縁付金属箔４を金属箔５が表面側にくるように
載置すると共にスルーホール３を回路１位置に合
わせ、次いで電気絶縁層付金属箔４を基板２に仮
接着し、次にスルーホール３内に導電材料を充填
し、その後基板２と電気絶縁層付金属箔４を成形
プレート間に挟んで積層成形することを特徴とす
る多層配線基板の製造方法により上記目的を達成
したものである。
That is, in the present invention, an electrically insulated metal foil 4 having a through hole 3 formed thereon is placed on the surface of a substrate 2 on which a circuit 1 is formed, with the metal foil 5 facing the surface side, and the through hole 3 is formed on the surface of the substrate 2. Align the position of the circuit 1, then temporarily adhere the metal foil 4 with an electrically insulating layer to the board 2, fill the through hole 3 with a conductive material, and then connect the board 2 and the metal foil 4 with an electrically insulating layer between the molded plates. The above object has been achieved by a method for manufacturing a multilayer wiring board, which is characterized in that the multilayer wiring board is laminated and formed by sandwiching the wiring board between the two.
以下本発明を実施例により詳述する。基板２と
しては金属ベース基板、樹脂基板、フレキシブル
基板、又はそれらの片面基板、両面基板、多層基
板等を使用することができ、限定するものではな
い。この基板２の表面には第２図ａに示すように
回路１が形成してある。基板２の上に第２図ｂに
示すようにスルーホール３が穿孔された電気絶縁
層付金属箔４を金属箔５が表面側にくるように重
ねて載置すると共にスルーホール３を回路１位置
に合わせる。ここで、金属箔５としては銅箔で形
成することができ、また電気絶縁層１３としては
紫外線硬化樹脂や熱可塑性樹脂等の樹脂層やプリ
プレグ、ボンデイングシート等で形成することが
できる。次に、この基板２と電気絶縁層付金属箔
４を一対の成形プレート間にセツトして電気絶縁
層１３の硬化に不十分な熱を加える等で電気絶縁
層付金属箔４を基板２に仮接着させる。ここで、
電気絶縁層付金属箔４の電気絶縁層１３として例
えばエポキシ樹脂プリプレグを用いた場合には、
この第１段での加熱加圧条件は140〜160℃、10〜
20Kg／cm2、10〜30分間に設定するのがよい。次
に、第２図ｂに示すように表面よりスルーホール
３内に半田ペースト、導電ペースト等の導電材料
６を印刷、あるいは塗布等の方法で埋め込み、そ
の後必要に応じて基板２をやや加熱して半田ペー
スト等の導電材料６中の溶剤を蒸発させ、その後
さらに基板２と電気絶縁層付金属箔４とを電気絶
縁層１３の完全硬化に十分な熱を加えて加熱加圧
成形するものである。その際の加熱温度は上記導
電材料６の溶融温度又はそれ以上の温度で成形す
るのが望ましく、電気絶縁層付金属箔４の電気絶
縁層１３としてエポキシ樹脂プリプレグを用いた
場合には、この第２段での加熱加圧条件は160〜
180℃、30〜50Kg／cm2、60〜80分間に設定するの
がよい。このようにして基板２に電気絶縁層付金
属箔４が積層一体化された多層配線基板Ａを得る
ものである。 The present invention will be explained in detail below with reference to Examples. As the substrate 2, a metal base substrate, a resin substrate, a flexible substrate, a single-sided substrate, a double-sided substrate, a multilayer substrate, etc. thereof can be used, and the present invention is not limited thereto. A circuit 1 is formed on the surface of this substrate 2 as shown in FIG. 2a. As shown in FIG. 2b, the electrically insulating layer-coated metal foil 4 with the through holes 3 is placed on the substrate 2 so that the metal foil 5 is on the front side, and the through holes 3 are connected to the circuit 1. Adjust to position. Here, the metal foil 5 can be formed of copper foil, and the electrical insulating layer 13 can be formed of a resin layer such as an ultraviolet curing resin or a thermoplastic resin, a prepreg, a bonding sheet, or the like. Next, this substrate 2 and the metal foil 4 with an electrically insulating layer are set between a pair of molded plates, and the metal foil 4 with an electrically insulating layer is attached to the board 2 by applying insufficient heat to harden the electrically insulating layer 13. Attach temporarily. here,
For example, when epoxy resin prepreg is used as the electrical insulating layer 13 of the electrically insulating layer-attached metal foil 4,
The heating and pressurizing conditions in this first stage are 140~160℃, 10~
It is best to set it at 20Kg/cm 2 for 10 to 30 minutes. Next, as shown in FIG. 2b, a conductive material 6 such as solder paste or conductive paste is embedded into the through hole 3 from the surface by printing or coating, and then the board 2 is heated slightly if necessary. The solvent in the conductive material 6 such as solder paste is evaporated, and then the substrate 2 and the metal foil 4 with an electrically insulating layer are heated and press-molded by applying sufficient heat to completely cure the electrically insulating layer 13. be. The heating temperature at that time is preferably the melting temperature of the conductive material 6 or higher, and when an epoxy resin prepreg is used as the electrical insulating layer 13 of the electrically insulating layer-attached metal foil 4, this The heating and pressurizing conditions in the second stage are 160~
It is preferable to set the temperature at 180°C, 30-50Kg/cm 2 , and 60-80 minutes. In this way, a multilayer wiring board A is obtained in which the electrically insulating layer-coated metal foil 4 is laminated and integrated on the board 2.
しかして、基板２と電気絶縁層付金属箔４とを
積層成形するにあたつて、予め基板２の電気絶縁
層付金属箔４を仮接着した状態でスルーホール３
内に導電材料６を充填しておくことにより、その
後の加熱加圧成形時に基板２の回路１表面が導電
材料６で保護されていて酸化されるということが
ないものである。また、半田ペースト等の導電材
料６でスルーホール３を埋め込むことにより、ス
ルーホール３内に空気が入るのを防ぐことができ
て信頼性を高めることができるものである。さら
に、スルーホール３をとるために半田ペーストの
印刷がし易く、スルーホール信頼性を高めること
ができるものである。また、このように形成され
た多層配線基板Ａ表面に２層目の回路を形成する
場合には、エツチングレジストが半田ペーストに
よく密接し、エツチング時にスルーホールランド
の保護が完全に行なえるものである。 Therefore, when laminating and molding the substrate 2 and the metal foil 4 with an electrically insulating layer, the through holes 3 are preliminarily bonded to the metal foil 4 with the electrically insulating layer of the substrate 2.
By filling the inside with the conductive material 6, the surface of the circuit 1 of the substrate 2 is protected by the conductive material 6 and will not be oxidized during subsequent heating and pressure molding. Further, by filling the through hole 3 with a conductive material 6 such as solder paste, it is possible to prevent air from entering the through hole 3, thereby improving reliability. Furthermore, it is easy to print solder paste to form the through holes 3, and the reliability of the through holes can be improved. Furthermore, when forming a second layer circuit on the surface of the multilayer wiring board A formed in this way, the etching resist should come into close contact with the solder paste, and the through-hole lands can be completely protected during etching. be.
次ぎに本発明を具体的な実施例及び比較例によ
つて例証する。 Next, the present invention will be illustrated by specific examples and comparative examples.
実施例
表面に回路１が形成されたガラスエポキシ積層
板で形成される基板２の表面に、スルーホール３
が穿孔されたエポキシ樹脂付銅箔で形成される電
気絶縁層付金属箔４を、銅箔が表面側にくるよう
に載置すると共にスルーホール３を回路１に位置
合わせし、150℃、10Kg／cm2の条件で20分間加熱
加圧して基板２に金属箔４を仮接着した。次ぎに
半田ペーストをスクリーン印刷してスルーホール
３に充填してから、成形プレートにはさんで170
℃、40Kg／cm2の条件で70分間加熱加圧成形するこ
とによつて、接着を完全にして多層配線基板を得
た。Example A through hole 3 is formed on the surface of a substrate 2 made of a glass epoxy laminate on which a circuit 1 is formed.
A metal foil 4 with an electrically insulating layer made of a copper foil with an epoxy resin perforated with holes is placed so that the copper foil is on the front side, and the through hole 3 is aligned with the circuit 1, and heated at 150℃ and 10 kg. The metal foil 4 was temporarily bonded to the substrate 2 by heating and pressing for 20 minutes under the condition of /cm 2 . Next, screen print the solder paste and fill it into the through hole 3, then sandwich it between the molding plates and
A multilayer wiring board was obtained by heat-pressing molding at 40 Kg/cm 2 at 40° C. for 70 minutes to ensure complete adhesion.
比較例
実施例と同様にして基板２の表面に電気絶縁層
付金属箔４を載置してスルーホール３を回路１に
位置合わせしたのち、170℃、40Kg／cm2の条件で
90分間加熱加圧して基板２に金属箔４を完全接着
させた。こののち、スルーホール３内に半田ペー
ストを充填して多層配線基板を得た。Comparative Example After placing the metal foil 4 with an electrically insulating layer on the surface of the board 2 and aligning the through hole 3 with the circuit 1 in the same manner as in the example, it was heated at 170°C and 40 kg/cm 2 .
The metal foil 4 was completely bonded to the substrate 2 by heating and pressing for 90 minutes. Thereafter, the through holes 3 were filled with solder paste to obtain a multilayer wiring board.
上記実施例及び比較例で得た多層配線基板につ
いて、スルーホール３内の気泡の有無を検査した
ところ、実施例のものでは気泡はなかつたのに対
して比較例のものでは気泡が存した。また回路１
が酸化されてあるか否かを検査したところ、実施
例のものでは酸化が発生していなかつたのに対し
て比較例のものでは酸化が発生していた。 When the multilayer wiring boards obtained in the above Examples and Comparative Examples were inspected for the presence of air bubbles in the through holes 3, there were no air bubbles in the Examples, but bubbles were present in the Comparative Examples. Also circuit 1
When inspected to see if it was oxidized, it was found that no oxidation had occurred in the examples, but oxidation had occurred in the comparative examples.
上記のように本発明は、表面に回路が形成され
た基板の表面にスルーホールが穿孔された電気絶
縁層付金属箔を金属箔が表面側にくるように載置
すると共にスルーホールを回路位置に合わせ、次
いで電気絶縁層付金属箔を基板に仮接着し、次に
スルーホール内に導電材料を充填し、その後基板
と電気絶縁層付金属箔を成形プレート間に挟んで
積層成形したので、予めスルーホール内に導電材
料を充填することにより基板の回路表面を導電材
料で保護することができ、成形時に回路の表面が
酸化されるのを防止することができて半田でスル
ーホールをとる場合の信頼性を高めることができ
るものである。
As described above, the present invention involves placing a metal foil with an electrically insulating layer on which through holes are formed on the surface of a substrate on which a circuit is formed, so that the metal foil is on the surface side, and placing the through holes at the circuit positions. Then, the metal foil with an electrically insulating layer was temporarily bonded to the board, the through holes were filled with a conductive material, and then the board and the metal foil with an electrically insulating layer were sandwiched between molding plates and laminated. By filling the through holes with a conductive material in advance, the circuit surface of the board can be protected with the conductive material, and the circuit surface can be prevented from being oxidized during molding. It is possible to increase the reliability of
第１図ａ，ｂ，ｃは従来例の製造法を示す要部
断面図、第２図ａ，ｂ，ｃは本発明一部実施例の
要部断面図である。
１は回路、２は基板、３はスルーホール、４は
電気絶縁層付金属箔、５は金属箔、６は導電材料
である。
FIGS. 1A, 1B, and 1C are sectional views of main parts showing a conventional manufacturing method, and FIGS. 2A, 2B, and 2C are sectional views of main parts of some embodiments of the present invention. 1 is a circuit, 2 is a substrate, 3 is a through hole, 4 is a metal foil with an electrically insulating layer, 5 is a metal foil, and 6 is a conductive material.
Claims (1)
ホールが穿孔された電気絶縁層付金属箔を金属箔
が表面側にくるように載置すると共にスルーホー
ルを回路位置に合わせ、次いで電気絶縁層付金属
箔を基板に仮接着し、次にスルーホール内に導電
材料を充填し、その後基板と電気絶縁層付金属箔
を成形プレート間に挟んで積層成形することを特
徴とする多層配線基板の製造方法。1. Place a metal foil with an electrically insulating layer on which a circuit is formed on the surface of the board, with the metal foil formed with through holes on the surface, and align the through holes with the circuit position. A multilayer wiring board characterized in that a metal foil with an electrically insulating layer is temporarily bonded to a board, then a conductive material is filled in the through holes, and then the board and the metal foil with an electrically insulating layer are sandwiched between molding plates and laminated and molded. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12980883A JPS6021598A (en) | 1983-07-15 | 1983-07-15 | Method of producing multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12980883A JPS6021598A (en) | 1983-07-15 | 1983-07-15 | Method of producing multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6021598A JPS6021598A (en) | 1985-02-02 |
| JPH0359595B2 true JPH0359595B2 (en) | 1991-09-11 |
Family
ID=15018729
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12980883A Granted JPS6021598A (en) | 1983-07-15 | 1983-07-15 | Method of producing multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6021598A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009113602A1 (en) * | 2008-03-13 | 2009-09-17 | 株式会社村田製作所 | Method for manufacturing a resin substrate and a resin substrate |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54159664A (en) * | 1978-06-07 | 1979-12-17 | Shin Kobe Electric Machinery | Method of producing printed circuit board |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5797970U (en) * | 1980-12-08 | 1982-06-16 |
-
1983
- 1983-07-15 JP JP12980883A patent/JPS6021598A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54159664A (en) * | 1978-06-07 | 1979-12-17 | Shin Kobe Electric Machinery | Method of producing printed circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6021598A (en) | 1985-02-02 |
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