JPS60214142A - Modulator - Google Patents

Abstract

PURPOSE:To attain low cost for a modulator by applying the MSK conversion of an NRZ signal by means of software while dividing it into plural samples per 1 bit in a personal radio equipment or the like. CONSTITUTION:The NRZ signal is applied with the MSK conversion at the inside of a microprocessor 13, the converted result is outputted to a D/A converting section 15 as 3-bit data and outputted from the converting station 15 as an analog signal. When 1-bit transmission data is inputted, the processor 13 discriminates whether the data is 1 or 0, and when 0, an output inverting flag is inverted and the address of the MSK conversion data table corresponding to the transmission data is set initially. The conversion data of the address is read, the 2's complement of the data is calculated according to output inverting flag information and the data subjected to the MSK conversion is outputted to the converting section 15. After the address of the MSK conversion data table is incremented by one, whether or not one-bit data transmission is finished is discriminated and this operation is repeated. The machine cycle number in this repetitive interval is brought into a prescribed number.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to MSK of control signals in personal radios, etc.
The present invention relates to a modulation device that performs modulation.

The configuration of the conventional example and its problems Figure 1 shows the MS of the control signal in the conventional personal radio.
A K modulator is shown. The configuration of this conventional example will be explained below with reference to FIG. 1.

In FIG. 1, 1 is a microprocessor, and this microprocessor 1 connects a signal line 8 to an NRZ signal receiving section 2.
It is connected at 3 is an address generation section, and this address generation section 3 is connected to the NRZ signal reception section 2 through a signal line 9, and is also connected to a PLA section (program logic array section) 6 through a signal line 10. There is. 7 is D
/A converter (digital-to-analog converter), and this D
The /A conversion section 7 is connected to the PLA section 6 through a signal line 11, and the MSK signal, which has become an analog signal, is connected to the PLA section 6 through a signal line 12.
Outputs a modulated signal. 5 is a synchronous clock generator;
This synchronous clock generator 5 includes a microprocessor 1,
NRZ signal receiving section 2, address generating section 3 and PLA section 6
are connected to each other by a signal line 4, and their timings are synchronized.

Next, the operation of the above conventional example will be explained.

In FIG. 1, a microprocessor 1 is responsible for producing an NRZ signal that is MSK modulated.

Therefore, the NRZ signal is actually MSK modulated by the five component elements from the NRZ signal receiving section 2 to the D/A converting section 7 in FIG. The NRZ signal section 2 is
It functions to receive an NRZ signal sent from the outside in synchronization with the synchronization clock generated by the synchronization clock generation section 5, and to control the address generation section 3 through the signal line 9 using the received signal. The address generating section 3 controls the address of the output pattern data to the PLA section 6 through the signal line 10 based on the signal received by the NRZ signal receiving section 2. Based on this address information, the PLA section 6 performs MSK conversion on the input NRZ signal, and outputs the digital signal to be outputted to the next D/A conversion section 7 through the signal line 11. These NRZ signal receiving section 2, address generating section 3, and PLA section 6 operate in synchronization with the clock signal generated by the synchronous clock generating section 5, so that they move smoothly without malfunction.

In this way, the output pattern signal created by the PLA section 6 is sent to the D/A conversion section 7 through the signal line 11, converted into an analog signal, and outputted from the signal line 12.

However, in the above conventional example, each component is made of hardware, and therefore a synchronization clock generator is required to synchronize the whole, resulting in an expensive problem in terms of cost. there were.

OBJECTS OF THE INVENTION The present invention eliminates the drawbacks of the above-mentioned conventional examples, and aims to make MSK modulation of control signals in personal wireless etc., which was conventionally realized only by hardware, into software.

Structure of the Invention In order to achieve the above object, the present invention arranges the synchronization of each component by the number of software steps, and also
When converting an RZ signal to MSK, it is realized by decomposing each bit into a plurality of samples.

DESCRIPTION OF EMBODIMENTS The configuration of an embodiment of the present invention will be described below with reference to the drawings.

In FIG. 2, 13 is a microprocessor, and this microprocessor 13 is connected to a D/A converter 15 through three signal lines 14.

The D/A converter 15 includes a 3-bit D/A converter, and the result is outputted from a signal line 16 as an analog signal.

Next, the operation of the above embodiment will be explained. NRZ is converted to MSK inside the microprocessor 13, and the converted result is converted into 3-bit data by the D/A converter 15.
Output to. In this way, the NRZ signal is MSK converted by software and becomes an analog signal in the D/A converter.

Next, details of the procedure for converting the NRZ signal into MSK will be explained below with reference to FIG. 3.

In FIG. 3, 17 is a step of inputting 1 bit of data to be transmitted after MSK conversion. 18 is a step in which it is determined whether the input data is 1 or 0, and if it is 0, the output inversion flag is inverted in step 19. This output inversion flag is M which is output when it is 1.
Two's complement is calculated for the SK-converted data. 2
0 corresponds to the data input in step 17
This is a step of setting the initial address of the SK conversion table. 21 is a step of reading data according to the address of the MSK conversion table. Next, in step 22, it is determined whether the output inversion flag is 1 or 0, and in step 21, 2 of the data read from the MSK conversion table is
Determine whether to calculate the complement of . If the output inversion flag is 1, a two's complement number is calculated in step 23. In step 24, the MSK converted data is output to the D/A converter.

Next, in step 25, the address of the MSK conversion table is incremented, and in step 26, the 1-bit MSK
Determine whether K conversion is completed.

For each bit, 12 data are held in the MSK conversion table, and step 2 is repeated until the data is output 12 times.
According to address 1, the process returns to the table reading routine.

After outputting one bit of data, it is determined in step 27 whether all transmission has been completed, and if it has been completed, the process returns to the main routine. If the process has not yet been completed, the process returns to step 17, the 1-bit data input routine.

In this MSK conversion routine, by determining the interval at which data is output to the D/A conversion constant by the number of machine cycles of the software, it can be performed with the precision of a crystal that determines the machine cycle time. By adopting this method, the frequency tolerance of the MSK signal required for personal radio can be ±
It becomes possible to suppress the amount within 200 ppm.

Next, the MSK conversion table is shown in FIG.

FIG. 4(a) is an MSK conversion table corresponding to data 0. There are 12 pieces of data, each consisting of 3-bit data. FIG. 4(b) is an MSK conversion table corresponding to data 1.

FIG. 5 shows the results of MSK conversion using this table.

In FIG. 5, (a) shows data subjected to MSK modulation. FIG. 5(b) shows the result of MSK modulation of data (a). While keeping the phase continuous, MSK modulation is performed while making data 1 correspond to a 1200 Hz signal and data 0 to a 1800 Hz signal. (C)
is the output inversion flag, and the output inversion flag is the data (a
) is inverted when it is 0. In this way, the output inversion flag becomes 1.
In the interval, two's complement is calculated for the data in the MSK conversion table and output to the D/A converter.

In this way, according to this embodiment, MSK modulation, which was conventionally possible only with hardware, can be achieved with software.

Effects of the Invention The present invention has the above-described configuration, and provides the following effects.

(a) The MSK modulation method can be realized by software.

(b) Since the MSK modulation method can now be implemented using software, costs can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional modulation device, FIG. 2 is a block diagram of a modulation device in an embodiment of the present invention, FIG. 3 is a flowchart of the same device, and FIGS. 4(a) and (b) are the same. FIG. 5, which is a diagram showing table data of the device, is an explanatory diagram of the operation of the device. 13...Microprocessor, 14...D/A conversion unit. Name of agent: Patent attorney Toshio Nakao and 1 other person
4 Figure (α)

Claims (1)

[Claims] A means for inputting 1 bit of transmission data and a means for inputting 1 bit of transmission data.
means for determining whether the transmitted data is 0, means for inverting an output inversion flag when the transmitted data is 0, and means for determining whether the transmitted data is 0;
means for initializing the address of the SK conversion data table; means for reading conversion data from the MSK conversion data table corresponding to the set address; and means for detecting an output inversion flag and reading data from the MSK conversion data table according to the flag information. means for calculating the two's complement of;
A means for outputting the MSK converted data to the D/A converter, a means for incrementing the address of the MSK conversion data table by 1, and after incrementing the address of the MSK conversion data table by 1, the 1-bit data transmission is completed. means to repeat the table reading and output to the D/A converter until the 1-bit data transmission is completed, and if the 1-bit data transmission is completed, input 1 bit of data again and perform MSK conversion. 1. A modulation device having a means for outputting data to a D/A converter, the number of machine cycles being a constant number at a repetition interval of outputting to a D/A converter.