JPH04238441A - Error generation circuit for test - Google Patents

Abstract

PURPOSE:To execute a processing with digital signals and to make an error test to be accurate by adding a digital error generation circuit. CONSTITUTION:A data center 23 inputs the digital signal 11 outputted from a digital signal processing circuit 1 and the digital signal 45 obtained by inverting the digital signal 11 by an invertor 22, and outputs the digital signal 11 outputted from the digital signal processing circuit 1 at regular time when there is no error in output signal 46 by using a pulse signal 44 from a panel generator 21 as a data selection input. When an error occurs, the digital signal 45 obtained by inverting the pulse signal 44 as active is controlled by the error pulse signal 44 and it is outputted. Thus, signals into which error data synchronized with the digital signal 11 inputted to the output signal 12 of a data selector 23 is inserted can be outputted as a polarity inversion error signal by the number of pulses which the pulse generator 21 generates.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error generation circuit for testing, and more particularly to an error generation circuit for testing digital signals created for testing digital reception circuits of digital wireless communication equipment.

0002

2. Description of the Related Art As shown in FIG. 3, a conventional test error generating circuit converts digital data 201 outputted from a transmitting side digital signal processing circuit 101 into an analog signal using a modulator 102, and converts the analog data into an analog signal. signal 20
2, the noise signal 20 from the analog noise generator 106
5 is added by the signal synthesizer 103, and this synthesized analog signal 203 is input to the demodulator 104 to be converted into the original digital signal, and the digital data 204 output from the demodulator 104 is sent to the digital signal processing circuit on the receiving side. 105 to measure data errors.

0003

[Problems to be Solved by the Invention] In the conventional test error generation circuit described above, since noise is synthesized by converting it into an analog signal, it is difficult to give the same amount of noise as a digital value. Even if , the amount of error in the reproduced digital data is not necessarily the same due to the reproduction characteristics of the demodulator, and there is a drawback that it is difficult to perform error tests on the digital signal processing circuit on the receiving side under the same conditions. .

Furthermore, in this method, since the error occurrence rate on the receiving side depends on the reproduction characteristics of the demodulator, it is difficult to accurately test the digital signal processing circuit on the receiving side, which is the original purpose of this error test. The drawback is that it cannot be done.

Furthermore, a modulator for analog conversion and a demodulator for analog-to-digital conversion are required when testing the digital signal processing circuit on the receiving side for errors.

[0006]

[Means for Solving the Problems] The test error generation circuit of the present invention is a test error generation circuit that tests by inputting a test signal including a test error pulse in a pseudo manner to a digital signal processing circuit on the receiving side. A digital error generating means is provided for inputting a digital data signal from a digital signal processing circuit on the transmitting side and generating a test signal converted into a predetermined number of error pulses whose polarity is inverted in synchronization with the digital data signal.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a digital error generator 2, which is the main part of this embodiment. In the embodiment shown in FIG. 1, a digital signal 11 output from a digital signal processing circuit 1 on the transmitting side is input to a digital error generation circuit 2, and a digital signal 1 with an error added thereto.
2, an error test is performed on the digital signal processing circuit 3 on the receiving side.

Next, this digital error generation circuit 2
It is composed of a pulse generator 21, an inverter 22, and a data selector 23.

The operation of this digital error generating circuit 2 will be explained. The pulse generator 21 uses a clock 41 synchronized with data, a frame timing 42, and an error number input 43 to uniformly generate a predetermined number of one-clock width error pulse signals 44 per unit time in accordance with the frame timing 42. This outputs the following. The data selector 23 transfers the digital signal 11 output from the digital signal processing circuit 1 and the digital signal 11 to the inverter 2.
By inputting the digital signal 45 inverted by 2 and using the pulse signal 44 from the pulse generator 21 as the data selection input, the output signal 46 is outputted from the digital signal processing circuit 1 under normal conditions without error. A digital signal 11 is output. When an error occurs, the pulse signal 44 is activated and an inverted digital signal 45 is output under the control of the error pulse signal 44. Therefore, a signal containing error data synchronized with the digital signal 11 input to the output signal 12 of the data selector 23 by the number of pulses generated by the pulse generator 21 can be output as a polarity inverted error signal.

[0011]

As explained above, the present invention adds a digital error generation circuit during error testing of the digital signal processing circuit on the receiving side, thereby eliminating the need for the modulator and demodulator required for analog signal conversion as in the conventional example. No noise generator or signal synthesizer is required, and all digital signals can be processed. Therefore, since an accurate number of errors is given, there is an effect that an accurate error test can be performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a test error generation circuit according to an embodiment of the present invention.

[Figure 2] Digital error generation circuit 2 of the main part of this embodiment
FIG.

FIG. 3 is a block diagram of a conventional test error generation circuit.

[Explanation of symbols]

1 Transmitting side digital signal processing circuit 2 Digital error generation circuit 3 Receiving side digital signal processing circuit 21 Pulse generator 22 Inverter 23 Data selector

Claims (2)

[Claims] Claim 1: In a test error generation circuit that tests a test signal including a test error pulse by inputting a pseudo test signal to a digital signal processing circuit on a receiving side, a digital data signal from a digital signal processing circuit on a transmitting side is input. 1. A test error generation circuit comprising digital error generation means for generating a test signal converted into a predetermined number of error pulses whose polarity is inverted in synchronization with the digital data signal. 2. The digital error generating means uniformly generates a predetermined number of errors of the same width as the clock per unit time by inputting a clock synchronized with the digital data signal on the transmitting side, frame timing, and a predetermined number of errors. an inverter that inverts the digital data signal on the transmitting side; and an inverter that inverts the digital data signal on the transmitting side, and a 2. The test error generation circuit according to claim 1, further comprising a data selector for inputting a number of inverted pulses.