JPS5896485A - Color test signal generating circuit - Google Patents

Abstract

PURPOSE:To obtain a chroma test signal which can find out a failure point easily, by converting an output value of a binary counter into a complement for 2 for a half period of a color subcarrier wave and outputting the value. CONSTITUTION:A pulse in about 7.16MHz outputted from a frequency divider 4 is counted at a binary counter 1 and outputs 0-225 in the binary expression of sequential 8-bit. A bit output A0 of the least significant digit of the counter 1 is applied as a control signal X as a polarity inversion circuit 2 and an adder 3. Thus, when the least significant digit of the counter 1 is ''1'', the output value A of the binary counter 1 is inverted for the polarity and ''1'' is added and D which is a complement for 2 is outputted. Then, in response to the increase/ decrease in the output value of the binary counter 1, a color test signal stepwise changed from the negative maximum saturation to the positive maximum saturation, can be generated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for generating a test signal (particularly a color test signal) for various devices that handle digitized television signals.

Most commonly used devices are those that convert a television signal into a -C digital PCM signal using an A/D converter, perform necessary processing through digital signal processing, and then return it back to an analog signal.

In such digital equipment, it is difficult to trace the flow of No. 116 when the equipment malfunctions or during inspection, and it is very difficult to find the location of the malfunction. Regarding the bright component of the television signal, it is relatively easy to obtain a signal that makes it easy to find the failure point during tracking.

For example, a signal whose amplitude changes stepwise can be obtained by correspondingly changing the digital values.

However, since a chrominance signal is a signal obtained by modulating a carrier wave with a chrominance signal, it would be difficult to easily create an arbitrary test signal, and it would be difficult to obtain a test signal that would make it easy to find fault points. do not have.

SUMMARY OF THE INVENTION An object of the present invention is to provide a color test signal generation circuit that generates a chromaticity test signal that makes it easy to find failure points.

Generally, when converting a television signal of the NT8C standard to a digital PCM signal, the sampling frequency is selected to be four times the color subcarrier frequency (approximately 3.58 MHz), and the sampling phase is 1.Q axis of the color subcarrier. Therefore, at each sampling point, the chromaticity component signals I, Q, -I.

This is a repeating signal of the −Q axis component. Above - ■.

-Q means that the polarities of the I and Q signals are reversed after 1800 seconds. The present invention focuses on the above point, and the present invention provides that during one cycle of the color subcarrier, 1, Q, -1, -
The test signal is generated so that the four components of Q are sequentially output, a waveform that is easy to test is selected, and the configuration is reconfigured so that the waveforms are output in the above order.

The signal generation circuit of the present invention includes a binary counter, a polarity inversion circuit that inverts the output value of the binary counter in accordance with a control signal to be described later, and means for generating a rectangular wave having the same period as a color subcarrier as a control signal. , a 7111 multiplier that adds 1 to the output value of the polarity inverting circuit using the control (g), converts the output value of the binary counter into a two's complement number for a half period of the color subcarrier, and outputs the result. This is expressed as a percentage.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

That is, an 8-bit binary counter I.

A polarity inversion circuit 2 that inverts the polarity of the output value of the counter 1 when the control signal X is 11". The control # signal X is 1".
an adder 3 which adds 1 to the output value of the polarity inversion circuit 2 when . It consists of a divider 4 that divides a clock of approximately 1432 MHz (four times the frequency of the color 1!II carrier wave) by h. Then, the output of the division period 4 is about 7.
Count the 16 MHz pulses with binary counter 1. The two-way counter 1 counts the 7.16 MHz pulses and sequentially outputs 4 outputs of θ to 255 in 8-bit binary representation.

Further, the counter output uses offset binary. That is, the output value 1128'' represents the amplitude O of the I and Q signals, the output value ``0'' represents the negative maximum value, and the output value ``255'' represents the negative maximum value.
" represents the maximum positive value.Then, the bit output A0 of the least significant digit of the counter 1 is added as the control signal '', the polarity of the output value A of the binary counter l is inverted and 1 is added to it. That is, a two's complement number is output.

In offset binary, two's complement means inversion of sign. Also, the lowest VrFi of counter 1, 7.1
Because it is inverted by the 6 MHz pulse E,
It is a 3.58 MHz square wave.

That is, in this embodiment, the least significant bit output of the counter 1 also serves as means for generating a rectangular wave having the same period as the color subcarrier as the control signal X. When the control signal X is '0', the polarity inversion circuit 2 outputs the output of the binary counter l as it is, and when the control signal
outputs the inverted state of each bit of the input signal. For example, it can be easily constructed using an exclusive OR circuit. The output C of the polarity inverting circuit 2 is sent to the adder 3 as a control signal X.
and the color test signal is sent out. Therefore, when the control signal
In this case, the output value A of the counter 1 becomes a two's complement value.

FIG. 2 shows each bit output A6-A71 of the output signal A (8 bits) of the binary counter 1 (in the time chart shown, the lowest pix) Ao is also the control signal X.

Signal A is a repeating signal with values from 0 to 255,
θ to 255Vi of the signal A, as described above, corresponds to the negative maximum value to the positive maximum value of the Q signal.

And in the process of increasing the signal person from 0 to 255, 1
A color test signal whose polarity is inverted every time No. 6 The signal person is clocked at 14.32 MHz per jcI@+Qe + L t Ql
t-..., I s + Q It transmits color difference signals up to 1 liter. The steps of the above change are monotonically increasing by one. Older names such as ``green'' and ``cyan'' at maximum saturation gradually decrease in saturation to gray, and then change from low chroma (red-magenta) to maximum saturation (red-magenta). This is a signal to If the above-mentioned test signal is employed as a chromaticity signal, it will be easy to check the operation of the device at each point, and it will be most suitable as a key signal for testing.

In the embodiment described above, the counter 1 also serves as a means for obtaining the control signal X, but in another embodiment of the invention shown in FIG. 3, the flip-flop 5 is triggered by a pulse of approximately 7.16 MHz. generates a rectangular wave of about 3.58 megacycles, and the flip-flop 5
A control signal xE is obtained by the output of Of course, the top 6 piflips 70 are synchronized to the color carrier. Then, the inertial inversion circuit 2. and controls adder 3. Therefore, when the control signal X is ``0'', the output value of the counter 1 is directly output as the color test signal, and when the control signal In this case, counter 1 is output as
It is Loe's ability to count arbitrary periodic pulses,
Also, fix it to an arbitrary value. This is very convenient for testing because it is possible. In this case as well, as described above, @0" of the counter l means the negative maximum saturation, the output "128" of the counter 1 means all achromatic colors, and 1255" means the positive maximum saturation. However, it is needless to say that the counter is not limited to 8 bits.

As described above, in the present invention, the output value of the binary counter is converted into a two's complement number (7) in synchronization with the inversion of the color-carrier wave. It is possible to generate a color test signal that changes stepwise from the maximum negative saturation to the maximum positive saturation in response to the increase or decrease in the output value of the counter. This has the effect of making it easier to test the chromaticity signal circuits of television equipment and to trace failure points.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a time chart showing output signals of the binary counter of the above embodiment, and FIG. 3 is a block diagram showing another embodiment of the present invention. It is. In the figure, 1: binary counter, 2: polarity inversion circuit, 3: adder, 4: frequency divider, 5: 70 flips. Agent Patent Attorney Sumi 1) Toshi So Figure 1 Figure 2v! J IoQoI, ΩII2α2−

Claims (1)

[Claims] A binary counter, a polarity inversion circuit that inverts the output value of the binary counter by a control signal described later, and a color #&l.
means for generating a rectangular wave having the same period as the 1la transmission wave as a control signal, and an adder for adding 1 to the output value of the polarity inverting circuit according to the control signal, A color test signal generation circuit whose characteristic is to convert into a two's complement number and output it only during the half period of the carrier wave.