JPS63187842A - Vlsi for modem - Google Patents

Abstract

PURPOSE:To attain one chip of a high speed MODEM by adding a PLL for timing matching among a logic circuit specific to a prescribed S/N, a conventional digital signal processor, a digital linear CODEC and a sampling timer. CONSTITUTION:The titled VLSI consists of a digital signal processor (DSP)1, a digitized linear CODEC2, a MODEM exclusive circuit (MLOGIC)3 comprising devices such as a serial interface and a sampling timer and a digital phase locked loop (DPLL)4 comprising two sets of circuits. A data from a terminal equipment is subject to modulation processing by the DSP1, inputted to the CODEC2, where the digital LPF is applied, the result is subject to D/A conversion and outputted to an I/F(interface)8. A reception signal is inputted from the I/F8 and subject to A/D conversion by the CODEC3 decoded at the DSP1 and outputted as a reception data from the I/F10 of the MLOGIC3. In such a case, the DPLL4 acts to match the sample timing designated by the MLOGIC3 with the actual timing of the CODEC2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a VLSI for a modem and a modem, and particularly preferably to a VLSI for a modem suitable for one-chip integration.
It relates to LSI and modems using it.

[Conventional technology]

Modem (MODEM = Modulator)
A demodulator is a modem device that transmits data using an analog line such as a telephone line.There are various types of communication methods and modem methods, but in recent years the semiconductor device that realizes this modem has been developed. LSIs that apply digital signal processing are progressing.

Regarding the status of modem conversion to LSI, as shown in 1 Japanese magazine Electronics October 1981 issue, pages 51 to 55, miniaturization, that is, LSI conversion, is essential as modems become more sophisticated and multifunctional. A digital signal processor (DSP) is used in high-speed modems with transmission speeds of 4,800 bps, 9,600 bps, etc. in order to utilize digital signal processing technology, which has been particularly developed in recent years.

There is RAM inside the DSP to temporarily store data.
, a data ROM that stores constants necessary for operations, a high-speed parallel multiplier, an addition/subtraction and logic unit (ALU), an input/output function (I10 port), and an instruction ROM that stores signal processing procedures. In order to efficiently execute calculations, it is common to have two sets of data bus lines and RAM. Other features include address pointers, interrupt control, and an automatic instruction repeat function for high functionality and high-speed calculations.

On the other hand, even if the conversion is performed using digital signal processing, an analog circuit is required for the interface with the line, and an analog front-end LSI is also used for this part.

The main parts of an analog front-end LSI are a transmitting/receiving filter that removes out-of-band signals, an A/D, and a D/A converter, and an attenuator (ATT) that sets the transmitting level.
), automatic gain control circuit to cover changes in input level,
Cable equalizer that equalizes the frequency characteristics of the aging line, W
A delay equalizer that equalizes the group delay distortion of the i-transmission link.

Some have built-in carrier detectors, zero-cross detectors, etc.

As for manufacturing methods for these LSIs, DSPs use the same digital IC process as microprocessors and the like, and analog front-end LSIs use an analog-only process similar to A/D converters and the like.

FSK or PSK modulation methods are used for low-speed modems with transmission speeds of 1200 bps or less, but these methods can be implemented with a simple circuit configuration.9 They are less susceptible to line distortion and do not require an automatic equalizer. Since then, a one-chip modem has been realized in which a digital part and an analog part are integrated into one chip. The most suitable conventional example of the present invention is an American academic journal, IEEE Journal.
of 5solidState C1rcuit VoL
, SC-19, Nα6 P 869-877 (19
A Single-Ch shown in December 1984)
ip Frequency-5hift Keyed
ModemImplemented Using Di
digital Sjgnal Processj, ng. Although this modem is a low-speed modem that incorporates only the FSX modulation method, it shows one direction for LSI implementation. In other words, this modem has 9 data modes and 19 operation modes, but the modulation required for this,
All functions such as demodulation and filtering are realized by digital signal processing of two DSPs integrated on one chip together with A/D and D/A converters. Others, R5232C and v,
A serial interface defined by the 24 standard.

Built-in loopback test function, etc. As for hardware, each of the two DSPs has data RAM.
, coefficient ROM, instruction ROM, and two DSPs.
operate independently. Also, the A/D and D/Ai converters select a high sampling rate based on Nyquist's sampling theorem, but a much higher sampling rate is selected to further eliminate foldback noise due to sampling. In addition, a complementary sigma-delta method is used for the A/D converter, which reduces the number of pure analog circuits and uses digital circuits such as decimators and intabolators in parallel to convert A/D converted signals at the required sampling rate. It has gained. For this reason, even if digital circuits are mainly integrated on a single chip, the characteristics of the semiconductor device will be stable with little variation, and the characteristics will be reproducible even in mass production.Furthermore, software control allows for numerous operating modes. The company claims that it has the advantage of being able to implement complex functions without significantly increasing the chip size.

[Problem that the invention seeks to solve]

The above-mentioned conventional technology has the following drawbacks:
Unless this problem is solved, it will be difficult to integrate a high-speed modem into a one-chip LSI, which is the object of the present invention.

Traditional high-speed modems require multiple DSPs even in the most advanced devices.
It was a multi-chip system using analog front end I and SI, and had a large number of parts, which limited miniaturization. Therefore, there is a drawback that the device becomes expensive.

In addition, the analog front end LS of the conventional high-speed modem
The internal part of the LSI occupies a large proportion of the entire pure analog circuit, which has the drawback of large variations in product characteristics, and for this reason, techniques such as laser trimming have been used, making it difficult to reduce the price of the LSI itself.

In addition, conventional high-speed modems are equipped with multiple processors, and since mutual cooperation is unavoidable, processing time is wasted, and twice the hardware is required, resulting in poor resource utilization. There was a drawback.

In addition, in conventional high-speed modems, internal software processing is divided into sample processing and baud processing, but in order to control the basic timing with baud processing, a baud rate timer is required in addition to the sampling timer and bit rate timer. However, it had the disadvantage of requiring a large amount of hardware.

In addition, the above sampling processing is a filter, modulation, and demodulation function that needs to be synchronized with the timing of A/D and D/A conversion, and baud processing is processed in synchronization with the timing of generation or determination of the signal point to be modulated. A3 point allocation processing, automatic equalization processing, differential encoding, scrambler, etc. need to be performed, and in order to process these two types of timing, two DSPs are dedicated to sampling processing and baud processing, respectively. Alternatively, it is necessary to arrange the timing by providing a microcomputer as a third processor, which has the disadvantage of complicating the setting of processing timing.

Furthermore, since it is thought that the single-chip system was realized because of the technically simple transmission system of a low-speed modem, the following problems arise when applying it to a high-speed modem.

DSP is 10 times smaller than a normal general-purpose microprocessor.
It has a calculation execution performance that is twice to 100 times faster, but the conventional example uses two built-in low-speed modems of 300bps.
An A/D is processed by SP, and its computational performance is too low to apply directly to high-speed modems, and its program capacity is small.

It cannot be applied to high-speed modems because of problems such as a small number of D/A conversion bits, non-linear characteristics of A/D conversion, and failure to reproduce timing signals from received signals.

In addition, conventional single-chip modems require A/D conversion and D/D conversion.
By significantly converting the A conversion circuit into digital signal processing, for example,
This is achieved through DSP signal processing, including the involator and decimator, but in order to obtain conversion characteristics equivalent to conventional analog signal processing, modulation and demodulation are required for the arithmetic processing of the A/D and D/A converters. This method requires much higher calculation accuracy than processing, and has the drawback of placing a heavy burden on the DSP.

Note that the DSP and analog front-end LSI used in conventional high-speed modems cannot be integrated into one chip using conventional circuit configuration methods because their manufacturing processes are different. In other words, DSPs are composed of digital circuits, and as the degree of integration increases with the miniaturization of semiconductor manufacturing processes, high-performance DSPs can be integrated on one chip, or multiple DSPs can be integrated on one chip. However, conventional analog front-end LSIs use switched capacitor filter technology, and in this method, the area to obtain the necessary capacitance does not depend on the semiconductor process to realize the capacitor in the area of the semiconductor surface. This has the drawback that the wiring rules are constant and are several times as large as digital circuits, making it impossible to downsize. In addition, this switched capacitor method achieves its characteristics through charge transfer and storage, so it is easily affected by noise, and in particular, the noise generated by the digital circuits of DSPs that are integrated into one chip may prevent normal operation. Therefore, it is difficult to apply high-speed modems that require a high S/N ratio in the analog part.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a VLSI for a modem and a modem that can be applied to a high-speed modem and eliminate the drawbacks of the prior art described above.

[Means for solving problems]

The purpose of the present invention is to provide a relatively high S/H digital linear codec of 15 bits or more, a programmable sampling timer, a serial interface, one general-purpose digital signal processor, and a digital linear codec and sampling timer as follows. and a PLL for timing matching between the
This can be achieved by performing software processing within the DSP using sampling timing interrupts as a reference.

In this case, the digital linear codec includes a digimole A/D, a D/A converter, a smoothing filter, a test circuit, and a transmission/reception filter using a digital circuit.

Further, the VLSI of the present invention is provided with a serial interface, a sampling timer, and a register that enables configuration control of each element in the linear codec.

Further, the VLSI of the present invention has a built-in DSP Ilo that monitors internal signals and timing signals.

[Effect]

In the present invention, VLSI has a relatively high S/P of 15 bits or more.
Built-in N digital linear codec. The digital linear codec used in the present invention performs coarse quantization at a high sampling rate of 1 megasample per second or more and obtains high conversion precision through digital signal processing, which can reduce the manufacturing precision of the analog circuit portion. For this,
If anything, it can be manufactured using a manufacturing process suitable for 5 digital circuits, and is effective in integrating analog circuits and digital circuits.

Further, in the present invention, the bandpass filter characteristics of the codec are made to match the transmitting and receiving filters of the modem.

Therefore, there is an advantage that the processing amount and accuracy of signal processing in a general-purpose DSP can be reduced.

In addition, in the present invention, since a programmable sampling timer is built into the VLSI, the DSP performs A/D conversion at the optimal timing for the eye pattern of the signal obtained by demodulating the received signal. This has the advantage that the sampling timing can be adjusted by the command of Furthermore, the present invention has a function of synchronizing the sample timings of transmission and reception in hardware, and it is possible to share the A/D and D/A conversion timings.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 26.

1 to 22 are explanatory diagrams of hardware of a VLSI modem to which the present invention is applied, and FIG. 1 is a block diagram showing the overall configuration of the hardware. The entire configuration shown in FIG. 1 is preferably integrated on the same semiconductor substrate.

The modulation and demodulation method to which this embodiment can be applied is preferably PSK (PhaseShift), which modulates and demodulates by switching the carrier phase corresponding to 1.0 of the data signal.
QAM (Quadrature Amplitude) system modulates and demodulates by changing not only the carrier phase but also the amplitude in response to
For example, a relatively high-speed orthogonal amplitude modulation/demodulation method such as a deModulation method may be used.

In FIG. 1, 1 is a digital signal processing processor (hereinafter referred to as DSP), and 2 is a digitized linear codec (hereinafter referred to as DSP).
3 is a modem dedicated circuit (hereinafter referred to as MLOGIC) consisting of a serial interface, a sampling timer, etc., and 4 is a digital phase-locked loop (hereinafter referred to as DPLL) having two sets of circuits. The DSPI includes an interface with the terminal device (hereinafter referred to as H-BUS I/F) 4, C0DEC2
Interface (hereinafter referred to as G) that sends and receives data to and from
(referred to as ODEC-I/F) 5. Peripheral bus that exchanges digital data with MLOGIC3 (hereinafter referred to as ■/〇-BU
In addition to the interface (hereinafter referred to as C0DEC-I/F) signal 6 from the DSPI, the C0pEC2 has an interface (hereinafter referred to as PLLT-I/F) for the coDEC basic timing signal from the DPLL4.
(referred to as F)9. In addition, there is an analog interface (hereinafter referred to as A-I/F) 8, and in addition to the 11O-BUS7 from the DSPL, the MLOGIC has a serial interface terminal (hereinafter referred to as S-I/F) 9 with the terminal. and sample timing signal interface (
(hereinafter referred to as SMPLT) 10, and DPLL4
is C0DEC by SMPLTIO and PLLT7
2 and MLOGIC3. Data SD from terminal (SEND.

DATA) is input at a predetermined speed through the S-I/F9 of the MLOGIC3, modulated by the DSPI, and then input to the GODEC2 through the C0DEC-4/F6, where the digital low-pass filter (L
After passing through the PF), it is D/A converted and output to the A-I/F 8 for transmission. Further, the received signal is inputted through the A-I/F 8, A/D converted by the GODEC 2 to a digital signal, which is passed through a low pass filter LPF to remove noise outside the required band, and then handed over to the DSPI. The DSPL2 demodulates this through digital signal processing to restore the original data, and then outputs it to the S of the MLOGIC3.
-Receive data RD from I/F (RECEIVE DA
TA) is output. In addition, DPLL4 is MLO
Sample timing specified by GIC3 and C0DEC2
The H-I/F of the DSPL receives and receives startup signals, mode signals, parameter signals, or transmission data necessary for modem operation from the terminal, and vice versa. It is used to return received data to the terminal and to notify the terminal of internal status.

The DSPI has a configuration as shown in FIG.

That is, in FIG. 2, 100 is an HO3T-I/F circuit, 11o is a data memory, and 120 is an arithmetic unit.

130 is a control unit (CONT), 140 is C0DEC-I
/F circuit, each of which has X-BUS, Y-BUS,
In addition to being connected by three D-BUS data buses, each block receives and receives data and controls internal functions by a control signal (not shown) (generated from CONT 130).

As shown in FIG. 3, the HO8T-I/F circuit 10o includes an input register 101 and an output register 102 for exchanging data with the terminal. A flag register 103 for displaying the interface status; a circuit 104 for accessing these registers from the terminal side; It also consists of a DSPI basic operation timing generation circuit 105, and the terminals are data buses (Do to 7) and access signals (R/W).

IE, AO~3. It is connected to the inside of the DSP via D-BUS, and exchanges the various data described above.

The data memory 110 includes a RAM 111 as shown in FIG.
and ROM 112, address pointer RA113. of RAM III. RB114. The selector 115, the address pointer 116 of the ROM 112 and the selector 117, and the data bus side are X-BUS and Y-B.
It consists of RAM selectors 118 and 119 for US. RAM III consists of four pages. It is a readable and writable memory, and the address selector 11
5 specifies the selected address. These include addresses specified directly by software instructions, pointer RA
There are three output addresses: 113 or RB114.
The selected address is entered into the memory address.

On the data bus side of the memory, four pages are accessed simultaneously, but on the data bus side, there are two sets of selectors, 11
8 and 119, and one of these can be independently selected and output to Y-BUS and X-BUS. For this reason, it is possible to exhibit the dual port RAM function. Address pointer RA, 11
3°RB114. R○ 116 is a counter whose value can be read and written directly by software or indirectly through an accumulator, and the value of the counter can be automatically updated following a memory reference. R.O.
M112 is mostly RAMI except that it is read-only.
It has the same functions as II. All reading and writing of selectors and pointers can be specified with one software instruction.

therefore.

In addition to being able to directly refer to an address designated by a command, these data memories can be accessed in a variety of ways using address pointers, simultaneous multi-page reading, multi-input switching selectors, two read buses, and the like.

The calculation unit 120 is configured as shown in FIG.

That is, in FIG. 5, 121 is a parallel multiplier (M
ULT) 122 is a temporary storage register (MOUT) that stores the multiplication result, and always multiplies the values of Y-BUS and X-BUS every DSPI operation clock. Also 123
is an addition/subtraction/logic operation circuit (ALU), 124 is one input selector, 125 is the other input selector, and the result of the (FUNC) operation specified by the instruction is sent to the accumulator (ACC) 127. The status of is stored in the status register (OCR). There are a plurality of ACCs 127, and they are selected and used depending on the command. As is clear from FIG. 5, the arithmetic unit 120 connects the MULT 121 and the ALU 123 with a well-known pipeline, and MOUTs the results of each.

It is stored in ACC, for example A=A+BX
A product-accumulation operation such as C can be executed seemingly every single DSP operation clock. Also, ALU1
The inputs of 23 can also be switched in a variety of ways by software instructions using selectors 124 and 125, and are suitable for modem signal processing that involves a lot of calculations that can be expressed by the above equation. Furthermore, since the single arithmetic unit supports the floating point representation format, it not only allows for a wide signal dynamic range, but also facilitates bit manipulation processing such as scramblers and differential encoding, which are unique to high-speed modems. It has its features.

In other words, floating point operations facilitate bit shift operations, and such instruction words can be easily created.

The control section 130 is as shown in FIG. 6th
In the figure, 131 is a program counter (PC), 1
32 is a stack (STACK), 133 is an instruction storage memory (I-ROM), and 134 is an instruction register (I-Reg).
), 135 is an instruction decoder (I-Dec), 136 is a repetition counter (RC), and 137 is a state control register (CT
R) and 138 are status display registers (CR), which are connected to the D-BUS as shown in the figure. PCl31
generates an address that specifies an instruction in the l-ROM 133, and normally its value is updated one by one each time an instruction is executed, but when a jump instruction is executed, the jump destination address in the instruction is , I-REG134. D-BUS
, the data is input to the PC and the contents are replaced. Also,
In the case of a subroutine reference instruction, the reference address in the instruction is similarly replaced, but in this case, the old PC address is temporarily stored in the stack 132 until the processing of the subroutine is completed.

It is also possible to further reference subroutines during execution of the subroutine by using multiple stacks. When the subroutine processing is completed, the processing can be restarted by returning the newest old address from the stack 132. Also,
Interrupts are something that uses the stack. An interrupt is a process that forcibly interrupts the flow of processing that is currently being executed and executes a pre-prepared interrupt process.This interrupt uses the stack, similar to the case of subroutines, to prepare for restarting. old pc
Temporarily store the value of . In order to execute interrupts in a circuit,
In the interrupt processing sequence, it is not possible to accurately know the interrupt timing, so there is a risk that data or status flags that are being processed may be destroyed, so the interrupt processing side needs to know the status of the processor at the time of the interrupt. It is necessary to save it accordingly. Note that the numerical value specified by the command is directly
I- also when storing in CC127 or other registers.
A part of the instruction word temporarily stored in REG134 is D-BUS
transmitted through. The instruction decoder 135 is a CoNT
It interprets commands and generates control signals in order to control the entire operation of the DSPI including the DSPI section. Also RC
1 and 36 are registers for controlling instruction repetition; 5 The number of repetitions set in this register is controlled by an RC control instruction, and the circuit controls repeatedly executing the same instruction or a series of processing instructions a specified number of times. This feature allows the processing to be repeated without interrupting the arithmetic processing, resulting in high instruction execution efficiency. Status control register CTR
Reference numeral 137 controls the macro operation of C0NT 130, and can enable or disable interrupts using instructions. The status display register CR138 is a register that reflects the input status of interrupts, the operating status of external interfaces, the status of calculations, etc., and can be read and written by instructions. These functions of C0NT1'30 are basically known as microcomputer technology.

C0DEC-1/F slow A is a serial interface circuit as shown in FIG. In Figure 7, 14
1, when serial data (Sl) is input, it is converted to 16-bit parallel data, read out by a command, and sent to D-
Register (SIR) that can be input to BUS
SI is input to SIR by transfer lock 5ICK. Reference numeral 142 denotes a status register that recognizes the end of transfer by an external signal 5IEN and notifies this to the C0NT section 130;
It also controls data input to IR141. 144 is a register (SOR) that converts 16-bit parallel data written via the D-BUS according to a command into serial data (SO) and outputs the same.

SO is output from SOR to the outside by transfer lock 5OCK. Reference numeral 145 denotes a status register that detects the end of transfer using an external signal 5OEN and notifies this to the C0NT section 130. The signal 5OEN also controls data output from the 5OR 144 through a gate 146. SIF and SOF are used as interrupt signals in the C0NTL30 section. Interrupts can be independently masked by CTRL37.

Furthermore, since the CR138 can directly provide SIF and SOF, data input/output without using interrupts is also possible.

FIG. 8 is a timing chart of this transfer operation.

The signal names in Figure 8 are the same as in Figure 7, and 5IR
141 and 5OR144 operate similarly. Data input is operated by S I and 5ICK generated by a circuit not shown, and normally 5IEN is set to 16 clock intervals It Hu of 5ICK to indicate the valid interval of data BI. This falling edge of 5IEN is the transfer end timing, and at this timing the transfer end flag SIF rises (“H
II). The DSP program knows the end of transfer in SIF and sends 5IR by internal import command (S IR-RD).
141, data can be taken into the D-BUS. The SIF is returned to the 11 LI+ level upon execution of this instruction.

In the case of 5OR144, they have the same meaning except that SIF is a capture permission flag on the DSP, while SOF is a write permission flag on the DSPI.

肚0GIC3 has a configuration as shown in FIG.

In FIG. 9, 200 is a control section, 220 is a transmission section, 2
40 is a receiving section, and 260 is a common section. @l1O-BUS7 is connected to the control unit 200 from the DSP,
This is the output signal I- of the command knee Reg134 from the DSP.
These are BUS, D-BUS, timing signals, etc., and the entire MLOGIC 3 is controlled by these signals. The control section 200 includes a transmitting section 220. Receiving unit 240. It generates the timing necessary to operate the common section 260 and is connected to the DSPI via Bt and 7S.

Among the output signals of the control section 200, the signals with -WP and -RD are decoded signals of the I-BUS, and thereby control data transfer with the data input/output circuit in each block. Further, the signal with -8W is a switch changeover signal that changes over the elements in each block according to the operation mode. The transmitter 220 is connected to an external S-r/FI.
Connect with O, transmit data SD as timing signal, STI
, ST2, or TBT signal, or S
A transmission sample timing TxS is generated through the MPLT interface 11. In addition, loop signals RD' and RT' are input from the receiving section 240, and the common section 26
0 outputs monitor signals SD' and ST'.

The receiving unit 240 is connected to the outside via S-I/FIO, and receives the received data RD as a timing signal RT.

It outputs by RBT and generates reception sample timing R×S through SMPLT interface 11. RT' is a monitor signal. In addition to the general-purpose input/output circuits PO to P7, the common section 260 also receives internal signals SD',
It has a function to monitor STI' and RT''.The feature of this configuration is that it extracts the command signal of DSP 1,
This part is where the command is interpreted. For this reason, there is an advantage that new instructions can be added without affecting the instructions originally included in the DSPI.

As shown in FIG. 10, the control unit 200 includes a frequency divider 201, an instruction decoder 202 . D-BUS and M from DSPI
It consists of a path transceiver (B'US-T/R) 203 that connects to the BUS in LOGICA, and a configuration control register (SW) that controls the connection of each element in NLOGICA. The frequency divider 201 uses the basic clock φ of the DSPI.
0 is frequency-divided and converted into a signal CLK having a frequency of 1/2. The instruction decoder 202 receives an instruction signal I from the DSP.
-Bus and basic timing signals φ0 to 3, ML
Read/write signal for registers in OGIC3 (-RD: Read.

-WR:Write) is generated. BUS-T/112
03 operates the signal receiver and bus driver according to the direction of signal flow using the output T/R-SW of the instruction decoder 202. 5W204 is a register dedicated to configuration control, and is controlled by the command (SW-WR).
It is possible to write and control the contents of the DSPI ACC127.

The transmitter 220 is a timing frequency divider that generates sample timing for transmission, as shown in FIG.

It consists of a serial/parallel conversion circuit that inputs transmission data, a transfer rate generator, a timing control circuit, etc.
221 is a changeover switch, 221 is a 1-bit shift register (DFF) that primarily latches the SD, and 223 is DFF2.
224 is a gate that inputs the output of S/P 223 to BUS by a command (SD-RD); 225 is a gate for these SDs; The frequency divider (ST) 226 that generates the transfer timing of
The register (ST) 228 set by C
A frequency divider (TXS) that divides the frequency of LK and generates sampling timing, 229 is a changeover switch 230 is an STI
An edge gate circuit 231 generates narrow edge pulses by capturing falling changes in the input signal, and an AND gate circuit 232 inhibits edge pulses.
233 is a transmission timing control register.

In the case of transmission by the internal timing operation of the synchronous modem, the operation is as shown in the timing chart of FIG. 12(a). In the case of synchronous type and normal transmission, the number of switches is a.
Set it to the side or OFF state. The TXS 228 divides the CLK output generated by the control unit 200 and outputs the TXS.
Generate a signal. The output CO of TXS generates a clock for the ST frequency divider 225 that is synchronized with the falling edge of TXS. Also, if the frequency division ratio is written in the ST register 227, the 5EL 226 does nothing in a synchronous modem. The ST2 signal according to the frequency division ratio of the ST register 227 is generated without any effect. This ST2 is supplied to an external terminal device and used as the sending timing of the transmission data SD, and is also supplied to the internal DFF 222 and S/P 223 to receive the transmission data SD. In this case, the output T of the SCR register 233
SYNC functions to initially reset the ST frequency divider 225 and the TXS frequency divider 228 to achieve timing synchronization. At this time, the DFF 222 latches data at the rising edge of ST2, and the S/P 223 inputs this output at the falling edge of ST2. Furthermore, since the SOF rises at a timing substantially synchronized with the TXS signal, the DSPI can operate in synchronization with these timings.

Therefore, the modulation timing can be determined by exceeding the number of SOF interrupts.

A transmit port timing signal (SET) can be generated accordingly.

When using a synchronous modem such as QAM or PSK and transmitting in synchronization with external transmission timing STI (ST
I mode), the operation is performed as shown in FIG. 12(b).

The STI monitor (STI') can monitor signals using the general-purpose input circuit Ei, so when the STI is input and the STI mask signal is released ("H"), the output of the Edge circuit 230 passes through the gates 231 and 230. hand,
Since the ST frequency divider 225 and the TXS frequency divider 228 can be reset and synchronized, the STI mask (“L”
''), and thereafter, at each po timing, release the mask at the TXS timing before the po timing, and set the mask at the TXS timing of the po timing to synchronize the STI and internal timing. Can be done.

Note 1: Originally, the timing difference between STI and internal ST2 is less than 1/10,000 according to the standard.
Even if the TXS timing is longer than the TXS timing, the mask will not be set before synchronization due to software processing delays.

In the case of an asynchronous modem such as an FM modem or an FSK modem, a predetermined Sr1 is generated for convenience of data input, as shown in FIG. 12(c).
ps example), but modulation is performed at TXS timing, and TFS
K-3W is tilted to side b and SD is captured and processed at each TXS timing.

Therefore, in the case of a synchronous modem, the SD
In this case, the S/P 223 is simply used as a latch function, whereas the S/P 223 is used as a simple latch function.

In the case of the G2 modem, there is no originally specified data transfer rate, but in this case, the internal processing is 9.6kbps.
, and generates and provides convenient timing to external terminal devices. In the case of this embodiment, two frequency division ratios are prepared, and the selector 226 switches between them for each appropriate Sr1.

In this case, the data transfer rate is 10368bps and the modulation method is asynchronous, internal processing is performed in synchronization with TXS, and S
The input of the T frequency divider is 56.2kHz.The frequency divider is switched every 9 ST2 signals. To limit the band of transmission data, the upper bits of the ST frequency divider 225 may be set.

LOOP2 mode is a remote digital loop test mode in which the received data is modulated again and transmitted. In this case, the 5EL221 and 229 are used to set the received data RD' and the received timing RT to SD and ST, respectively.
Enter it as I and use it.

If all operations are performed in STI mode, a remote digital loop can be realized by simply specifying the mode without an external switching circuit. The circuit of this embodiment has the advantage that it can be used to isolate RD multiple signal failures.

As shown in FIG. 13, the receiving unit 240 consists of a sampling timer for reception, a transfer rate generator, a parallel/serial conversion circuit for outputting received data, a timing control circuit, etc. 241 is a DSPI command (RD- WR), the demodulated data is written via the BUS of the control unit 200, and the shift register (P/S) converts the parallel signal into a serial signal, which is output as received data (RD) via the 1-bit shift register (OFF) 242. ), 243 is a gate that can inhibit the transfer lock input of P/5241, and 244 is a switching circuit (SE
L), 245 is an RT register that sets the frequency division ratio of the transfer rate (RT) frequency divider 246 by the DSPI command (RT-WR), and 247 is the reception sample timing R.
The division ratio of the RXS frequency divider 248 that generates XS is [)SP
The Rx register 249 set by the I instruction (RX 5-WR) is the timing control register (RX 5-WR) on the receiving side.
RCR), 250 is the rising edge of the received data RD.

An edge detection circuit (Edge) 251 that detects a falling change and generates a pulse synchronized with CLK synchronizes this edge signal with the RXS signal and outputs a switching signal R.
The circuit 252 gated by -9YNC-SW is
The output of this gate 251.

R8YNC signal generated by DSPI program
An OR gate 253 for feeding to the T frequency divider is a switching circuit (SEL) 254 for outputting an RT-multiplied signal of the timing signal for data transfer generated by the ST frequency divider on the transmitting side in the G2 mode. is a 1-bit shift register (O
FF).

For synchronous modems, 'RCR is reset.

5EL244 and 253 are tilted to side a. When the RXS frequency divider 248 generates the reception sample timing signal RXS according to the prescribed frequency division ratio set in the R'XS register 247, the A/D converter in the C0DEC2 quantizes the modem input signal at this timing. This is DSPI 5
It is received by the IR 141 and processed by the DSP program. Once the optimum timing is obtained through the reception process, the sampling timing is adjusted by adjusting the frequency division ratio set in the RXS register 247. This operation confirms that the RXS timing is synchronized with the demodulated signal timing, and at the same time, the RSYNC signal synchronizes the received data transfer timing RT with the R×S timing. DS at timing synchronized with RXS
An interrupt is entered in the PI, signal processing is performed in this interrupt unit, and reception processing is first performed at an arbitrary timing.As a result, an arbitrary demodulation timing can be achieved in internal processing, and a timing difference between the demodulation timing and the demodulated signal is detected. First, correct this timing deviation by adjusting the RXS frequency division ratio.
The R8YNC signal is used to adjust the timing of the RT frequency divider 246 to the demodulation timing synchronized with the corrected RXS timing.

That is, the RS Y N C is generated from the DSPI at the SIF interrupt timing at the po timing of timing adjustment. In this way, the original RRT frequency divider 246 becomes R
The timing synchronization between the two continues because it operates in response to the output CO of the XS frequency divider.

After the above synchronization is completed, as shown in FIG. 14(a), the command on the DSP (
When demodulated data is written to the P/S 241 using the DFF 242 (RD-WR), data transfer is performed with the output RD' delayed by one bit by the DFF 242. The DFF 242 has the effect of eliminating irregularities in RD-WR timing caused by software processing.

In the case of an asynchronous modem such as FM mode or FSK mode, as shown in Fig. 14(b), the clock R is set for convenience.
However, the 5EL 244 is turned to the b side and the received data demodulated at the timing of the RXS signal is output at the timing of the RXS signal. In this case, theoretically it could change for each RXS signal like the RD″′ signal shown in parentheses, but the transmitted signal is transmitted at a sufficiently low rate and this will not happen.However, the influence of the transmission line Therefore, it is not completely synchronized with RT.

Figure 14(c) shows a circuit that synchronizes this (Edge2
50) shows the function of R3YNC-3EL signal “H” even if the change point of the received data is shifted forward or backward.
”, the RT frequency divider can be synchronized with the changing point of RD.

In this case, during the DSPI demodulation process, R-3YNC-
It is possible to suppress timing reset irregularities by applying a gate to the 3EL-8W signal as shown in FIG. 14(c) for fine control, or by applying a filter to the received data itself through DSPI processing.

Note that the RBT signal and the RD multiplied signal are outputted through a 1-bit shift register 254.

The common section 260 consists of general-purpose input/output registers, as shown in FIG. In FIG. 15, reference numeral 261 is a general-purpose input unit which inputs the signals SD', STI', and RT' to be monitored in addition to the LSI external input PO"4, and inputs the signals SD', STI', and RT' to be monitored. RD) by A
It can be input to CC127. Further, 262 is a general-purpose output unit, and ACC1 is output by the instruction (EO-WR).
27 values can be output.

The terminal PO"P12 is a simple interface signal of the modem, for example, the R8 input in the 24 standard, the CD
, C3 output terminal.

As described above, MLOGIC can support various modem modes.

The digital PLL 4 has a configuration as shown in FIG. In FIG. 16, 300 and 310 are phase comparator circuits, 320 and 330 are variable frequency divider circuits, and 301 and 31
1 is the or gate.

Input signals from MLOGIC3 TXS, RXS, C
Compare the phases of sampling timings RXS' and RXS' inside C0DEC2 with respect to LKRES, and
Reset signals RES-T and RES for 0DEC2
-R, and by correcting the cycles of CLK-T and CLK-R, the CLK-T enters one cycle of sample timing even if the sample timing is being corrected.
(or CLK-R) does not change and CLK-T
(or CLK-R) by dispersing it so that the period does not fluctuate rapidly.

The phase is adjusted so that it operates at the frame timing specified by DSPI without impairing the characteristics of C0DEC2.

FIG. 17 is a timing chart illustrating the operation of the digital PLL 4. In the figure, only TXS is shown, but the same applies to RXS. Immediately after powering on the modem, a reset signal (RES) is sent from the external circuit.
enters and resets sequential circuits such as flip-flops and counters. From this state, operate the internal TXS (=T
If XS') is larger than RXS, then ((1,
), a pulse (RES-
T) and resets the C0DECI transmitter, which mainly performs DA conversion. TXS and TXS' by reset
After synchronization (2), if the TXS is intentionally shortened slightly by signal processing on the DSP (3)
, Synchronization (4), the cycle of CLKT in which the variable division cycle occurs is shortened, and the end timing of internal TXS' is delayed to achieve synchronization. Whether the phase comparison circuit 300 generates a reset signal (RES-T) or responds by changing the width of CLK-T is determined by the characteristics of the phase comparison circuit 300. , approximately 1.5 μs for a sample period of 1/9600 second
A window was created, inside which fine adjustments were made, and outside was reset. Also, in this case, the sampling period is 768
Regarding the clock period, the operating clock of C0DEC2 is 128, and when modifying the sampling period by assuming 6 CLKs per clock period, for example, in case (4) to shorten the period by about 1 μs, it is variable. The frequency divider 320 is ordered to increase the frequency. As a result, the variable frequency divider 320 narrows the width by 1 CLK for every 16 operating clocks (CLK-T), and by making the clocks slightly denser, the sample timing is improved. Fix it. Conversely, in case (5) in which the sampling period TXS is slightly extended (approximately 1 μs in the example), the phase comparator 300 uses the variable frequency divider 320 to
As a result, variable frequency divider 320 outputs CLK-
The width of the clock CL is narrowed by one CLK for every 16 T.
Correct the sample timing by coarsening K-T slightly. The same is true on the RXS side. Note that the modem standard specifies the modulation frequency and its accuracy, and the accuracy is ±0.01%. Therefore, even if the maximum deviation occurs, the necessary correction amount of about 1 μs will only be achieved after several pulses of TXS and RXS, and normally, except for the initial phase alignment, RES-T and RES-
R does not occur.

As shown in Figure 18, C0DEC2 includes a D/A section that converts digital signals into analog signals, an interface between the A/D section that converts analog signals into digital signals, and external circuits, a control circuit, a timing circuit, etc. 400 is a transmission buffer register, l (T-BUF), 4
10 is a D/A conversion circuit (DA), 420 is an attenuation circuit (A
T), 430 is a smoothing filter (PF), 440
is a switch (SW) that changes the signal flow for testing,
450 is an analog output buffer, 460 is a 1/16 frequency divider, and 470 is a transmitting side timing signal generator (TTMG).
, 500 is a digital output buffer, 510 is an out-of-band signal processing filter (PF), 520 is an amplifier circuit (AM
P), 530 is an A/D converter (AD), 540 is a reception buffer register (R-BUF), 550 is a changeover switch (SEL), 560 is a 1/16 frequency divider, and 570 is a reception side timing signal generator. (RTMG), 580 is C0
This is the system control register (CONT) for the entire CEC.

The signal on the left side of Figure 18 is the C0DEC-I/F on the DSP.
This is signal 6, and a 16-bit wide digital signal is input at the timing shown in FIG.

FIG. 19 is a timing chart showing how the CODEC 2 of FIG. 18 operates when the CODEC-1/F signal 6 is output. When you turn on the power to the modem LSI,
A system reset signal is generated immediately after the power is turned on, and this
On SP, MLOGIC″3, R through DPLL4
It becomes an EST signal and is input. In this case, -T is continuously input to CL', and T×S' is D P
It is assumed that the MLOGIC date is synchronized with the TXS generated by the L L date. RES signal is II L I
When returning to I, the DSPI program starts running and initializes each part. Initialization of C0DEC2 begins with C0NT580. C0NT580 is attenuation amount 5 of ATT420
In addition to controlling the switching of W440 and the amplification factor of AMP520, it also has the function of displaying the internal status.
Control signals are exchanged through the EC-I/F6. That is, C0NTl is from SO.

This is a signal to input the control signal to C0NT580, and C0NT2 inputs the control signal to C0N758 through SI.
This is a signal to read from 0, which causes (:0
Shift register in N7580 is ready for loading TB
The UF400 is in a capture prohibited state, and the frequency divider 460 also outputs the 5OEN signal (3,6864MHz clock CL).
During the 16-pulse period of K-T, a 'H' signal indicating data transfer is valid is generated.This signal causes the DSPI 5O
A control signal written to R143 by a DSPI command is stored in a shift register in C0N7580. The above acquisition state is reset at the falling edge change timing of 5OEN, and the input data input to the DA410 is TBUF for the subsequent sample timing TXS.
400.

Like the C0NT580, the TBUF400 is also composed of a shift register, and as shown in FIGS. 8 and 19, receives and takes a 16-bit transmission signal from S○ at each falling timing of TXS. The received sent data is DA
410, the signal size is adjusted by ATT420, and the out-of-band signal is removed by PF430.
0 drives the Aout terminal and outputs it. These are created using timing signals generated by the 77MG470. TTMG divides the CLK-T input and outputs TXS'
It consists of a counter that generates TXS' and a combination circuit that synthesizes the frequency-divided pulses of each stage of the counter, and is initialized at the REST timing and generates TXS' and others at almost uniformly distributed timing every 768 CLK-Ts. generates the necessary timing on the sending side. Therefore, again RES
Unless T becomes 1H'', the whole.

It operates by being assigned a timing of 768 CLK-T signals in one cycle.

On the receiving side, when an analog reception waveform Ain is given, it is received by the reception buffer 500 and enters the filter PF 510 via the switching circuit 440. PF510 is
It is a low-pass filter that removes out-of-band signals prior to AD conversion, and this output is amplified by AMP520, converted to a digital signal by AD5.30, and then
It is stored in the RBUF 540, which is a shift register. This digital signal is outputted as a signal SI via the 5EL550, and inputted to the DSPI via the 5IR141. As shown in parentheses in FIG. 19, the receiving side is also operated by a timing signal generated by a timing generation circuit (RTMG) consisting of a counter and a combinational circuit, similar to the transmitting part. Similar to the transmitting side, it is initialized by RESR and generates the timing necessary for RXS' and other operations on the receiving side at timings that are almost uniformly distributed every 768 CLKRs. Therefore, RESR is again
'', the entire unit operates by assigning timings with 768 CLK-R signals as one cycle.The reason for uniformly distributing each timing is to prevent noise generated by digital circuits from becoming unevenly large noise. This is because it has the effect of preventing strong effects on analog circuits.For this reason, the DA410 and AD530 are
As shown in FIG. 20, it is an oversampling type that operates at the timing of a ratio of a power of 2 and is configured using a serial arithmetic circuit. In other words, there is a hold circuit (which holds the 6-bit digital signal output at a sample timing of 1 second at 9.6) while it is resampled at a sample timing of 4 times the sampling speed (38.4K samples at 7 seconds). HOLD) 411, low pass filter (LPF) that processes this output and removes unnecessary high frequency signal components 412.38.4 sample 7
A complementary circuit (INTP) 4.13 samples the output of the LPF 412, which is output in seconds, at a fine interval of 7 seconds, and a high-speed 8-bit D/A conversion circuit ( D/A) 414, receiving the output of TBUF400,
Hand over to 420. The transfer function of each block is expressed by the formula shown below each block, and these are calculated by a serial calculation circuit.

Among these, the analog circuit is a part of the D/A414 and is limited, and as a whole, these
Since it is operated at a power of 2 synchronized with K-T and at almost uniformly distributed timing, the analog signal output at 614.4 K samples in 7 seconds contains almost nothing other than quantization noise and switching noise. , thus a high signal-to-noise ratio is obtained. In addition, since the final sample timing is as high as 7 seconds for 614 samples, and the signal band is approximately 3kHz, filter 4, which requires low accuracy, is used.
30 can be used. Furthermore, in the case of a modem, the LPF 412 is required to have much higher accuracy than the characteristics of the transmission line, but since it is realized by a 32-bit operation using a digital circuit, excellent characteristics can be achieved. Further, as shown in the lower part of FIG. 20, the AD 530 operates so as to be able to send out an AD-converted analog signal to the 5IR 141 of the DSPI at a sampling period of RXS', that is, 9.6 samples and 7 seconds. First, an 8-bit A/D converter (A/D) 631 converts 1.2288 Mt (with a sampling period of z,
Converts the input analog signal into an 8-bit digital signal. Next, convert this output digital signal into 307.2K
The first thinning circuit (D
ECMI) 532 and then LC307, 2KHz
(7) The digital signal with a sampling period is input to the second thinning circuit (DECM2) 533 and converted into a digital signal with a sampling period of 38.4 KHz. This signal is then input to a low-pass filter (LPF) 534 to remove unnecessary signals of 3.4 KHz or higher to the modem, and further input to a decimation circuit (DUMP) to reduce the number of samples to 9.6.
Obtain a digital signal with a period of seconds. The transfer function of each of these blocks is expressed by the formula shown below each block.

These circuits operate at sampling frequencies that are much higher than the AD and DA conversion cycles required by the system.
This method is generally called an oversampling type A/D, D/A conversion method for operating a D/DA converter. The transfer function and sample frequency as in this example, AD531.
If the DA414 converter is used and the calculation accuracy of these transfer functions is made sufficiently high, only quantization noise and noise generated in the analog circuits of the AD and DA sections will affect the conversion accuracy.

Regarding AD conversion, 8-bit accuracy can be obtained with AD531, but by thinning this, the amount of noise can be reduced. In this case, by thinning out 1/8, theoretically 7-bit accuracy can be achieved. An improvement is expected, resulting in an overall 15-bit accuracy. Also, LPF53
4 can also remove noise, and in this example, approximately 3 d
It is B. Theoretically, a conversion accuracy of about 95 dB can be obtained by summing these values. In reality, it is a finite-length calculation, and the generation of noise due to the calculation is unavoidable, and the noise input from the analog circuit is also unavoidable, so the accuracy is a little less than 90 clB.

FIG. 21 shows the frequency characteristics of AD530. According to this, outside the band above 3.4, there is about -3 in the 10kHz band.
Although it has a peak of 3 dB, it has sufficient characteristics as a modem bandpass filter. This is a comprehensive characteristic that includes the characteristics of the thinning circuit.

FIG. 22 shows that the above-mentioned AD accuracy can be fully utilized in a high-speed modem. In other words, AD conversion (
For the accuracy AD in A), the reception level range DR of the modem
If the sum (B) of the peak factor PF of one signal and the minimum signal-to-noise ratio SN required to obtain a specified reception quality is sufficiently small and the deterioration of SN is small, no problem will occur. In the case of this embodiment, DR=43. PF=15. When the SN is set to 22, the deterioration of the SN is 0.3 dB or less, and the deterioration is not a problem at all.

23 to 26 are flowcharts of software built into the DSPI in the VLSI modem of this embodiment.

FIG. 23 shows the overall configuration of the software, which consists of a main process starting with the symbol ``■'' and interrupt processes ``■'' and ``■''. Main processing ■ mainly handles signal processing such as modulation and demodulation, and interrupt processing ■ and ■ mainly handle signal processing such as modulation and demodulation.
The signal input/output processing, in which the timing of processing such as AD conversion, DA conversion, transmission data, and reception data is important, is divided, and most of the processing as a modem is executed in the main processing. The processing details will be explained below according to the flowchart.

In main processing ■, at initial 1000, DS
Internal (CTR, 5TR) register on P.

RAM, SOR, flag, CONT register of CODEC, SW, ST, SCR, RD of MLOGIC.

In addition to storing the RCREO5 initial value, TSYNC.

Issue R8YNC to synchronize ST and TXS, and RXS and RT. Next, a processing program for the modem operation mode specified from the outside such as a terminal is prepared, and since the initialization is completed, reception interruption is permitted (1010).Next, operation acceptance processing (1020) is performed. Signal detection processing 1030. Signal detection determination 1040. A processing loop of operation presence determination 1050 is entered. In this loop, it is assumed that the line to be received is connected.

Is a signal being sent through that line? (103
0) or whether this modem is commanded to transmit by operation (1020) and also determines (io40)
．． 1050). As for the signal to be received, A/D conversion data is taken in during the interrupt signal processing part, so for example, this value can be monitored to determine whether the signal is large enough to be received. Just do it. If a signal is coming, for example, FCC (
The meaning of early carrier detection) is defined on the EO terminal, and from this it is notified externally, and internally, since this is a half-duplex modem, operation reception processing for transmission is prohibited. do. Next, end determination 1070. A loop of po timing determination 1080 is entered. Here, it is determined whether to start or end the reception process. In this case, the FCD signal has just been displayed and is currently waiting for the po timing to arrive. When the interrupt process (2) operates multiple times during the pause period, it notifies the main process of the pause timing in the form of a count value or a flag. In the main processing, knowing this, reception processing 109o is performed. Interrupt processing (2) will now be explained. When the AD conversion in synchronization with RXS is completed and the AD conversion value is entered in 5IR 144, the interrupt flag SIF is set, and the contents of the DSPI program counter 131 are saved to the stack 132, and a predetermined address is set to store the start address of the interrupt processing. A PC address (vector address) is set in the PC. This starts interrupt processing. In the interrupt processing (2), first, the contents of the SIR are read and stored in the AD conversion buffer area defined in RAMIII in the memory 110 in the DSPI (1200). Next, a sample counter value DAMIIII that counts the number of interrupts is read out, and if the timing is a predetermined timing, sample timing processing 1, for example, RBT output processing is performed (1210). Next, the sample counter value set on RAMIII is updated (subtracted) (122
0).

If the update result is "○", it is po timing (1230). In the case of Paw timing, the Paw timing process first initializes the sample counter value, and then passes the AD conversion data stored in the receive buffer by interrupt processing to the main receiving process, or transfers the receive processing result through RD. Send it to the terminal (1240
), and then updates the po counter set on RAMIII and notifies the main process of the elapsed time (1
25.0).

When the processing is completed, the PC is returned to the state before the interruption and the main processing is restarted (1260). Note that the explanation of the interrupt time register saving process has been omitted.

This shall be implemented as necessary. The end of reception is when the other party stops transmitting. In this case, there is no reception signal, so this is detected and the operation reception process 102 is performed again.
All you have to do is return to 0.

To transmit, the terminal or operator writes R3 (request to transmit) to 1RO 101 of the DSOI. Note that since RS is also defined in general-purpose IOs PO to 3, this may be set to LL HII.

If R3 rises, this is detected (1050) and the transmitting operation begins. First, it is necessary to prohibit the receiving operation or to
It allows interrupts for A conversion and initializes transmission processing (1100).

Next, the transmission continuation determination process reconfirms that R3 is set, and waits for notification of the pause timing from the transmission side interrupt process (1120). When the baud timing comes, reception processing per baud is performed (1130). here,
In interrupt processing (2) on the transmitting side, processing is performed in substantially the same sequence as on the receiving side, but in the reverse order.When a 6-reception interrupt, ie, SOF, is raised, an interrupt occurs and processing (2) is activated. In (1), the DA data stored in the transmission DA buffer is first read out and written to the 5OR 141 (1300). next,
The transmission sample counter value on RAM III is read out, the timing is determined, and sample timing processing, for example, STI mask processing is performed (1310).

Next, update (subtract) the sample counter, and
Return to 1 (1320). If the count result is "OII", it is determined that it is a bow timing (1330).

In the case of bow timing, for example, the sample timer value is initialized, the empty DA buffer is handed over to the main processing, and instead, the DA data to be output for one baud is received. In addition, the transmission data SD is input through the gate 224 (134
0). Then, it updates the baud counter and informs the main process of the baud timing and time elapsed. .

As described above, apart from the content of signal processing, the processing sequence is simplified, program construction is easy, and processing performance is improved. Best of all, since the AD and DA buffers are provided for one cycle of one button, the processing is unified to the main processing of the port timing, which greatly improves execution efficiency.

Next, the operation as a modem will be explained with reference to FIG.

Figure 24 shows the modem transmission side sequence, transmission waveform,
3 is a timing chart showing a sequence on the receiving side.

In the case of a high-speed modem, when R3 is set, the transmitting side first estimates the line status called a training signal, sends a signal to initialize the receiving side, and after this is completed, C
It converts the S (clear-to-send) signal into It HII, receives the transmission data SD from the terminal, modulates it, and sends it to the line. On the receiving side, the receiving side notifies the terminal side of the detection of the arrival of the training signal using the signal FCD (assigned P, ~7) and enters the receiving process. In reception processing, the training signal is processed and automatic gain control (A
GC), timing regeneration, carrier regeneration, automatic equalization, etc., performs initialization called initial pull-in. This continues even after the training signal ends and becomes a data signal. The switching to a data signal is notified to the terminal by the signal CD, and the terminal is made to receive the subsequent RD.

The transmission is terminated by R80FF on the transmitting side. As a result, when C8 is stopped and the remaining data in the modem is modulated and transmitted, the transmitting side ends. The receiving side also becomes aware of this when the signal reception is interrupted.

FIG. 25 is an example of a reception processing program. Each processing BO
Known techniques can be used for the content of X. (For example, "Applications of Digital Signal Processing" edited by Institute of Electronics and Communication Engineers, Vol. 6?t (1982-7)
) This process starts when the baud timing is obtained, sets the number of loops (2000), reads the AD buffer data (2010), and passes the AD conversion data for the baud period passed from the interrupt process to the high frequency band. Perform filter processing to remove DC noise (2020) = Automatic gain control (AGC) is controlled from the received power value (2030), passed through a fixed line characteristic equalization characteristic filter (2040), and then demodulated. (2050) Remove the carrier (2060) @Know the reception timing from these signals and change the setting value of the RXS register to optimize the AD conversion timing (2070) These processes from 2010 to 2070 is looped for the number of samples within the baud period and processed repeatedly,
Once this is finished.

The original port timing processing begins (2080).

In port timing, the line characteristics, mainly the transport link characteristics, are equalized (2o9Q),! ! '1. The revealed signal is compared with a reference and identified (2100). This identification result is compared with the equalization output to obtain an equalization error, and the equalization characteristics are updated based on this (2110). The identification result is further decoded.
120), is descrambled (2130), and becomes the received data for one voice, so this is sent to R in RAM III.
Store in D buffer (2140), write L, if training is in progress (2150) disable this 2160
), performs reception sequence processing such as time measurement (217
0), the process returns to the main process in FIG. 23 (2180). In this way, there is no need to measure special timing during these reception processes, and the processing sequence and processing structure of the program are free, making it easy to program and improve processing efficiency.

The same goes for the transmitting side, which is shown in FIG.

In Figure 26, when the program is started, first 1
3000) The transmission data inputted in the interrupt processing is retrieved from the SD buffer. In the case of a training signal section (3010) transmit data.

Transmission data that is converted into a training signal and then processed (3020) is subjected to scrambler processing to randomize the signal (3030), and encoding processing to facilitate phase detection (3040). The output of such processing is used to determine the signal coordinate point to be transmitted, and the corresponding data is created (3050). This completes the original baud processing, and next, DA conversion data is created to be handed over to the interrupt processing. First, the number of loops for the baud period is set (3060), the baud processing result is waveform-shaped (3070), and then multiplied and modulated with the carrier carrier (3080). Next, this is put into an equalizer with fixed characteristics (3090), adjusted with the transmission level (by software processing) (3100), and stored in the DA buffer on RAM (3120'). These steps are performed a predetermined number of times. After completing the sample signal processing (3120), transmission sequence processing is performed (3130), and the process returns to the main processing shown in FIG.

This implementation also has an effect on the transmitting side.

As explained above, the modem of the embodiment to which the present invention is applied has many features and advantages, and the effects will be summarized below.

1. According to this embodiment, the high-speed modem is a one-chip VLSI
can be converted into The reason for this is that we devised and combined the DSP, a digitized linear codec that provides a high S/N ratio, modem-specific logic, and timing matching means. This enables highly efficient production using digital semiconductor processes.

2. DSP filter processing is relaxed. The reason is,
This is because the filters that lower the sample rate from oversampling in the CODEC to the desired sample rate are constructed with dedicated circuits, and the bandpass filter is matched to the transmission/reception filter characteristics of the modem.

3. Various timing synchronization is easy. DPLL.

R5YN, TSYNC, R-T-5YNC, also T
It is easy to synchronize with software and maintain it with hardware by connecting XS and ST and RXS and RT.

4. Internal control of the codec is easy and simple.

That is, write control data to 5OR1.

Issue a C0NTl pass or issue a C0NT2
Codec control information can be read and written by reading the IR, and no special I/F is required.

5. Since software monitoring of major timings can be performed, software processing of special timings is easy.

For example, initial reset settings in ST1 mode can be easily performed.

6. HO5T-I/F register is simple. That is, there are no IR, ○R, and 5TRL.

7. Easy AGC control, high S/N digital linear codec allows all AGC to be executed by DSP processing, ideal controllability 68. Includes WOT to prevent runaway monitoring. It is possible.

9. Since the dedicated I10 is controlled by the instruction decoder in the dedicated 110 section, the dedicated I1
0 is also highly scalable.

10. Since data density conversion is performed by switching between two types of frequency division ratios, it is possible to easily handle transmission timings with different basic clock specifications.

11. The hardware configuration is simplified because external timing synchronization can be performed using software monitoring and a soft mask. (S
TI synchronization) 12. The RD timing appears at the terminal one bit later than the software's baud processing, but since the status information is similarly delayed by the hardware, there is no need to be conscious of it in the software, simplifying the processing timing.

13. Since the interrupt processing is simplified and limited to the work/○ processing and timing adjustment, the structure of the main processing is simplified and the processing efficiency is high.

14. Processing is performed by one DSP, so the transmission/reception interaction is simple and processing efficiency is high.

〔Effect of the invention〕

As explained above, according to the present invention, one high-speed modem
In addition to being easy to integrate into semiconductor chips, it has many advantages, including:

That is, the present invention uses a relatively high S/N digital linear codec of 15 bits or more, such as an AC/DC amplitude modulation method, which is an oversampling type, has a small number of analog circuit parts, and can realize a highly accurate filter. Furthermore, it can be manufactured using a manufacturing process suitable for digital circuits, and can be integrated into one chip.

Further, in the present invention, since the bandpass filter of the codec is made to match the transmitting/receiving filter of the modem, there is an advantage that the accuracy and processing amount of signal processing of a general-purpose DSP can be relaxed.

Furthermore, since it has a programmable and maskable sample tire, it is possible to follow the sump timing of the received signal, and has the advantage that timing frequency division is simpler than in conventional modems.

In addition, the present invention has a serial interface circuit, which is an interface for digital transmission and reception signals between the modem and the communication terminal, and a serial-to-parallel (S/P) interface between the data bus of the general-purpose DSP. ), parallel-to-serial CP/S) data string conversion, and a rate generator that generates the serial data transfer rate. For this purpose, DSP
There is no need to convert data strings through processing, and the load on the DSP can be reduced. In addition, the rate generator described above can change the rate by the DSP, or change the rate by the DSP.
It is possible to reset the timing by Therefore, it is possible to support multi-mode modem functions, and it is also possible to synchronize sampling interrupts and serial interfaces. That is, there are advantages in that timing can be unified, DSP software can be structured, and timing settings can be simplified.

Further, the VLSI of the present invention has one built-in digital signal processor, and this digital signal processor is general-purpose, and the interface with the digital linear codec is an interrupt type. That is, the fact that A/D or D/A conversion has been performed at the above-mentioned sampling timing can be notified to the DSP program by interrupt 5. Since this interrupt operates independently in the A/D section and the D/A section, full-duplex modem processing is possible.

In addition, the modem VLSI of the present invention has a bus interface for data communication between the built-in DSP and external data generation or control equipment, and the data is synchronized by interrupts or flags to the external equipment. It can communicate and has high compatibility with external devices.

As described above, since the internal timing of the DSP is simplified, there is an advantage that the software structure of the DSP and processing timing settings can be easily set.

In addition, in the VLSI of the present invention, a PL for timing matching is provided between the digital linear codec and the sampling timer.
The addition of L ensures correct codec operation. For this purpose, oversampled A/D, D/A
Even if a codec using a converter is used, there is an advantage that the programmable sampling timer can smoothly follow the sample timing of the received signal and the A/D converted signal will not deteriorate. In other words, oversampled A/D and D/A converters are high sampling rate A/D converters that actually interface with analog signals.
, D/A part and this integer ratio (generally 1 in a power of 2)
interpolator, decimator, dump,
It consists of digital arithmetic circuits such as holds and bandpass filters, but because it is equipped with a timing PLL, even if there is a sample timing tracking operation to the received signal, the above-mentioned integer ratio does not collapse, and correct arithmetic is guaranteed. No signal deterioration.

According to the VLSI of the present invention described above, the use of a high S/N digital linear codec makes it possible to significantly digitize analog circuits and digital signal processing of filters, which has a great effect on stabilizing characteristics. be. In addition, because it uses a high S/N digital linear codec, automatic gain control using DSP signal calculation is possible.
Fine-grained and stable control can be achieved.

Furthermore, the modem using VLSI of the present invention can process all modulation/demodulation functions and operating procedures with one software, and can simplify the processing structure. Furthermore, since almost all modem functions are realized by DSP software, there are advantages of multi-mode single-chip integration and easy change and modification of programs and parameters.

FIG. 27 shows an example of a facsimile to which the VLSI modem of the present invention is applied. In FIG. 27, 400o is D
IPP, 4100 is the operation panel, 42oO is the microcomputer,
4300 is an address decoder, 4400 is a program memory, 4500 is a random access memory, 4600
4700 is a hybrid circuit, and 4800 is an NCU. With the above circuit, the control section of a facsimile machine using a high-speed modem can be realized with a small number of ICs.

Although the present invention is applied to a half-duplex modem in the embodiment, it is naturally applicable to a full-duplex modem as well.

Further, in the embodiment, the reception HPF is processed by DSP, but it may be incorporated into the CODEC as hardware.

Furthermore, the transmitted and received data SD and RD may be input and output through IR and OR.

In this case, the extra S/P or P/S conversion circuit is replaced by a variable length S/P.
It may also be used for P, P/S conversion and octet editing.

[Brief explanation of the drawing]

1 is an internal block diagram of a circuit according to an embodiment of the present invention, FIG. 2 is a block diagram of an internal circuit on the DSP of FIG. 1, FIG. 3 is a host interface circuit diagram of the DSP of FIG. 2, and FIG. Figure 5 is a circuit diagram of the data memory section, Figure 5 is a circuit diagram of the calculation unit, Figure 6 is a circuit diagram of the control unit, Figure 7 is the circuit of the codec interface unit, and Figure 8 is its timing chart. , FIG. 9 is an internal circuit block diagram of the MLOGIC3 shown in FIG. 1, FIG. 10 is a circuit diagram of its control section, and FIG.
Figure 12 is a circuit diagram of the transmitter, Figure 12 is a timing chart, Figure 13 is a circuit diagram of the receiver, Figure 14 is a timing chart, Figure 15 is a circuit diagram of the common part, and Figure 15 is a circuit diagram of the common part.
Figure 6 is an internal circuit block diagram of DPLL4 in Figure 1.
Figure 7 is the timing chart, and Figure 18 is C of Figure 1.
0DEC internal circuit block diagram, FIG. 19 is its timing chart, FIG. 20 is a detailed block diagram of the DA section 41o and AD section 530 in FIG. 18, and FIG. 21 is the C0DE
A diagram showing the frequency characteristics of the A/D section of C2, Figure 22 is a signal level and dynamic range comparison diagram, Figure 23 is an example of a flowchart of a program built into the VLSI of the present invention, and Figure 24 is its timing. Chart, No. 25
26 is a flowchart of reception processing, FIG. 26 is a flowchart of transmission processing, and FIG. 27 is a diagram showing an application example. 1...Digital signal processor, 2...Digitized linear codec, 3-...Modem dedicated logic, 4...Digital face-locked loop circuit.

Claims (1)

[Claims] 1. A digital linear codec with a predetermined S/N, a programmable sampling timer, a modem-specific logic circuit such as an interface, one general-purpose digital signal processor, and a timing link between the digital linear codec and the sampling timer. A VL for modems that is integrated into one chip with the addition of a PLL for matching.
S.I. 2. A VLSI for a modem according to claim 1, characterized in that internal processing is performed by software based on sampling timing interrupts. 3. The VLSI for a modem according to claim 1, wherein the linear codec includes a set of digitizing transmitting and receiving filters, a digitizing A/D, a D/A converter, a smoothing filter, and a test circuit. .