JP2901619B2 - Modem for full-duplex communication - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a modem (modem), and more particularly to a modem for full-duplex communication capable of processing full-duplex communication by one-chip integration.

[Conventional technology]

A modem is a modem device for transmitting data using an analog line such as a telephone line. There are various communication systems and modulation / demodulation systems. Recently, digital signal processing has been used as a semiconductor device for realizing this modem. Applied
LSI implementation is progressing. Along with the high performance and multi-functionality of modems, miniaturization, that is, LSI implementation is indispensable. In particular, in order to use digital signal processing technology with advanced technology, high-speed modems with transmission speeds of 4800 bps and 9600 bps require digital signals. A processor (DSP) is used.

Inside the DSP, RAM for temporarily storing data, data ROM for storing constants required for operation, high-speed parallel multiplier, addition / subtraction and logical operation unit (ALU), input / output function (I / O port), signal It incorporates an instruction ROM for storing the processing procedure. In particular, it usually has two sets of data bus lines and RAM for efficient execution of operations. For this purpose, various measures such as an address pointer and an automatic instruction repeat function have been devised.

On the other hand, even if modulation and demodulation are digital signal processing, an analog circuit is necessary for interface with the line, and an analog front-end LSI is used in this part.
The analog front-end LSI is mainly composed of a transmission / reception filter that removes out-of-band signals, an A / D, and a D / A converter, and an attenuator (ATT) that sets the transmission level and covers changes in input level. Some have a built-in automatic gain control circuit, a cable equalizer for equalizing the frequency characteristic of the subscriber line, a delay equalizer for equalizing the group delay distortion of the carrier link, and a carrier detector.

As a method of manufacturing these LSIs, a DSP uses a digital IC process similar to that of a microprocessor or the like, and an analog front-end LSI uses a process dedicated to analog, like an A / D converter.

For constant speed models with a transmission speed of 1200 bps or less, FSK or PS
The K-modulation method is used, but since these methods can be realized by a circuit with a simple circuit configuration and are not easily affected by line distortion and do not require an automatic equalizer, the digital section and the analog section are integrated into a single chip. Has been realized.

As a conventional example of the present invention, IEE, Journal of Solid State Circuit SC1
Vol. 9, No. 6, pp. 869 to 877 (December 1984) "A Single-Chip Frequency Shift Keyed Modem Implemented Using Digital"
Signal Processing ”(IEEE, Journal of Solid
State Circuit VoL.SC-19, No.6, p869-877 (12/1984)
“A Single−Chip Frequency−Shift Keyed Modem Impl
emented Using Digital Stgnal Processing ").

This modem is a constant speed modem incorporating only the FSK modulation method, but shows one direction for realizing LSI. In other words, this modem has 9 data modes and 19 operation modes, and integrates all necessary functions such as modulation, demodulation, and filters on a single chip together with A / D and D / A converters. It is realized by digital signal processing of the two DSPs. In addition, it has a built-in serial interface defined by RS232C, V, and 24 standards, a loopback test function, and the like.

As hardware, each of the two DSPs has a data RAM, a coefficient ROM, and an instruction ROM, and the two DSPs operate independently. As a result, the modulation process and the demodulation process can be performed simultaneously, and a so-called full-duplex process is realized. Also,
The A / D, D / A converter selects a high sampling rate based on the Nyquist sampling theorem, but selects a higher sampling rate to further remove aliasing noise due to sampling. The complementary sigma-delta method is used as the A / D converter.The number of pure analog circuits is reduced, and A / D conversion at the required sampling rate is performed using digital circuits such as decimators and interpolators. Getting the signal.

For this reason, even if integrated with a DSP on a single chip, there is little variation in characteristics as a semiconductor device and stability, and even when mass-produced, characteristics are reproducible. The company claims that it has the ability to implement complex functions without increasing the chip size.

[Problems to be solved by the invention]

The above-mentioned prior art has the following drawbacks. Unless these drawbacks are solved, it is difficult to perform full-duplex (communication) processing by integrating the high-speed modem of the present invention with a one-chip LSI.

It is considered that the conventional one-chip LSI integration can be realized by a technically simple transmission system called a constant speed modem. In addition, since full-duplex processing has been realized by using two DSPs, if this is applied to a high-speed modem as it is, operation performance is low. Therefore, when the operation performance is improved, the circuit scale increases with two DSPs, and it is difficult to integrate one chip LSI. Also, A / D,
There is a problem that the required precision cannot be obtained because the number of D / A conversion bits is small, and it is difficult to apply to a high-speed modem.

In addition, in order to perform full-duplex processing of a conventional high-speed modem, a multi-chip configuration using at least two DSPs is used, and the number of components is large, so that there is a limit to miniaturization, and there is a disadvantage that the apparatus becomes expensive. Was.

In the conventional high-speed modem, the internal software processing is
Processing is divided into sample processing that is performed in synchronization with the timing of A / D and D / A conversion, and baud processing that is performed in synchronization with the timing of generating or demodulating signal points. In order to control the timing by the baud processing, a baud rate timer is required in addition to the sampling timer and the bit rate timer, and there is a drawback that the amount of hardware is large.

In addition, analog front-end LS of conventional high-speed modem
The inside of I has a large proportion of the whole of the pure analog circuit,
There is a drawback that there is a lot of characteristic variation. For this reason, there has been a drawback that the price of the LSI itself is not easily reduced, for example, a technique such as laser trimming is used.

The object of the present invention is to eliminate the above-mentioned disadvantages of the prior art,
An object of the present invention is to provide a full-duplex communication modem capable of performing full-duplex communication processing applicable to a high-speed modem.

[Means for solving the problem]

The above object is achieved by a digital linear codec having a relatively high S / N of 15 bits or more, and a first linear codec which operates independently.
And a second sampling timer and one general-purpose DSP
And first and second interrupts for independently initiating interrupts in the DSP in synchronization with A / D and D / A conversions of the digital linear codec processed in synchronization with the first and second sampling timers, respectively. This is achieved by integrating the generating means in a one-chip LSI and using the one-chip VLSI to perform software processing inside the DSP based on a sampling timing interrupt.

[Action]

First and second DSPs which generate sampling timing interrupts independently of each other in synchronization with the A / D and D / A conversions of the digital linear codec which are processed in synchronization with the first and second independent sampling timers. By the second interrupt generation means, software processing is performed based on each sampling timing interrupt, so that transmission processing and reception processing can be asynchronously processed by one DSP, and full-duplex processing can be realized.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS.

1 to 15 are explanatory diagrams of hardware of a VLSI modem to which the present invention is applied, and FIG. 1 is a diagram showing an entire configuration of the hardware.

In FIG. 1, 1 is a digital signal processor (hereinafter referred to as DSP), 2 is a digitized linear codec (hereinafter referred to as CODEC), and 3 is a modem dedicated circuit (hereinafter referred to as MLOGIC) comprising two independent sampling timers and a serial interface. Reference numeral 4 denotes a digital phase locked loop (hereinafter, referred to as DPLL).

DSP1 is an interface 5 (hereinafter HBUS)
−I / F), an interface 6 for transmitting and receiving data to and from CODEC 2 (hereinafter referred to as CODEC-I / F), and MLOG.
Peripheral bus 7 that exchanges digital data with IC3 (hereinafter I / O
-BUS), and CODEC2 is a CODEC-I /
In addition to F6, it has an interface 9 (hereinafter, referred to as PLLT-I / F) for the CODEC basic timing signal from the DPLL 4, and an analog interface 8 (hereinafter, referred to as A-I / F).

Further, in addition to the I / O-BUS 7 from the DSP 1, the MLOGIC 3 has a serial interface 10 (hereinafter referred to as an S-I /
F) and a sample timing signal interface 11 (hereinafter referred to as SMP-I / F).
Is MLOGIC3 and CODEC2 by SMP-I / F11 and PLLT-I / F9.
Connected to

The data SD from the terminal is input at a predetermined speed through the MLOGIC3 S-I / F10, modulated by DSP1, and then processed.
The signal is input to CODEC2 through CODEC-I / F6, passes through a digital low-pass filter in CODEC2, is D / A converted, is output to A-I / F8, and is transmitted. The received signal is A
-Input via I / F8, A / D converted by CODEC2 and converted as digital signal. After removing out-of-band noise through low-pass filter, deliver to DSP1.

In DSP1, this is demodulated by digital signal processing, and ML
It is output as received data RD from the S-I / F 10 of OGIC3.
DPLL4 is based on the sample timing specified by MLOGIC3.
HBUS-I / F5 of DSP1 has the function of matching the actual sampling timing of CODEC2, and receives the start signal, mode signal, parameter signal, or transmission data necessary for modem operation from the terminal, Conversely, it is used to return received data and notify the terminal of the internal state.

FIG. 2 is a diagram showing the configuration of DSP1. In FIG. 2, 100 is a host interface circuit, 110 is a data memory, 120 is an operation unit, 130 is a control unit, and 140 is a CODEC-I / F circuit.

The host interface circuit 100 has an input register and an output register for data transmission / reception with a terminal, and a data bus and an access signal (R / W, IE, A0 to 3, ▲)
▼, other), the D-BUS is connected to the inside of the DSP. The data memory 110 is composed of a RAM and a ROM, and outputs from those memories are Y-BUS or X-B.
Output selectively to US. Writing is performed via a data bus.

The operation unit 120 has a parallel multiplier and an addition / subtraction logic operation unit,
By pipeline processing, for example, apparently sum of products operation,
It can be executed for each DSP operation clock. Further, since the present arithmetic unit supports a floating-point representation format, it has a feature that a dynamic range of a signal can be widened.

FIG. 3 is a diagram showing a configuration of the control unit 130. In FIG. 3, 131 is a program counter (PC), 132 is a stack, 133 is an instruction storage memory (I-ROM), 134 is an instruction register (I-Reg), 135 is an instruction decoder (I-DEC), 1
36 is a repetition counter (RC), 137 is a status control register (C
TR) and 138 are status display registers (STR), which are connected to the D-BUS as shown in the figure.

The PC 131 generates an address for designating an instruction in the I-ROM 133 and normally updates its value one by one every time the instruction is executed. However, when a jump instruction is executed, the jump address in the instruction is used. Is input to the PC via I-REG134, D-BUS,
The contents are exchanged. In the case of a subroutine jump instruction, the jump address in the instruction is similarly replaced. In this case, the old PC address is temporarily stored in the stack 132 until the subroutine processing is completed. It is possible to refer to the subroutine further during execution of the subroutine by using a plurality of stacks.

When the processing of the subroutine is completed, the stack 132
The process can be resumed by returning the newest old address from. Also, there is an interrupt in those that use the stack.
An interrupt is a forcibly interrupting the flow of the currently executing process,
The interruption process prepared in advance is executed, and this interruption uses the stack 132 as in the case of the subroutine, and temporarily stores the value of the old PC for resumption. The instruction decoder 135 interprets a command word to control the overall operation of the DSP 1 and generates a control signal.

The RC 136 is a register that controls the repetition of the instruction. The RC 136 controls the number of repetitions set in the register 136, and controls the circuit to repeatedly execute the same instruction or a series of processing instructions a specified number of times. In this case, the function can be repeated without interrupting the arithmetic processing by this function, so that the instruction execution efficiency is high. Further, the STR 138 can enable or disable an interrupt, and furthermore, is a register that reflects the input state of the interrupt, and can be read and written by an instruction.

FIG. 4 is a diagram showing a configuration of the CODEC-I / F 140. In FIG. 4, reference numeral 141 denotes a register (SI) which converts serial data (SI) into 16-bit parallel data upon input, and which can be read out by an instruction and input to the D-BUS.
R), and SI is input to SIR by the transfer clock SICK. Reference numeral 142 denotes a status register for knowing the end of transfer by the external signal SIEN and setting a serial input transfer end flag SIF for notifying this, and this SIF flag is reflected on the STR 138 and can be read out by an instruction.

Signal SIEN controls the data input to SIR 141 by gate 143. If the serial input interrupt prohibition signal Isi of the STR 138 is not set, an interrupt signal can be generated by the gate 144 via the gate 149 according to the SIF flag. The SIF flag is cleared when the contents of STR138 are transferred to the accumulator (ACC) by an instruction.

145 was written via D-BUS by instruction
This is a register (SOR) that converts 16-bit parallel data into serial output data (SO) and outputs the SO. The SO is externally output from the SOR by the transfer clock SOCK. Reference numeral 146 denotes a status register for setting the serial output transfer end flag SOF for notifying the end of transfer by the external signal SOEN and notifying the end of the transfer. The SOF flag is reflected in the STR 138 and can be read out by an instruction. Signal SOEN, S by gate 147
Controls data output from OR145.

If the serial output interrupt prohibition signal Iso of the STR 138 has not been set, the gate 148 can generate an interrupt signal via the gate 149 according to the SOF flag. The SOF flag is cleared when the contents of STR138 are transferred to ACC by an instruction. As described above, the SIF flag and the SOF flag can be independently used as interrupt signals, and each interrupt can be independently masked by Isi or Iso of the STR 138.

FIG. 5 is a timing chart of this rolling operation. The signal names in FIG. 5 are the same as in FIG.
R141 and SOR145 operate similarly. Data input is SI, SIC
Operated by K, normally, SIEN is set to “H” for 16 clock periods of SICK to indicate a valid period of data SI. This SIEN
Is the transfer end timing, at which time the transfer end flag SIF is set (to "H").

The DSP program knows the end of the transfer by looking at the interruption by this SIF or directly looking at the SIF of the STR 138, and can fetch data from the SIR 141 to the D-BUS by an internal fetch instruction (SIR → RD). The SIF is returned to the “L” level by transferring the contents of the STR138 to the ACC with an instruction. For SOR145,
While SIF is a flag to allow capture by DSP1, SOF
Is the same operation except that is a write enable flag by DSP1.

FIG. 6 is a diagram showing the configuration of MLOGI3. In FIG. 6, reference numeral 200 denotes a control unit, 220 denotes a transmission unit, 240 denotes a reception unit, and 260 denotes a common unit. The control unit 200 is connected to I / O-BUS7 from DSP1. This is the output signal I-Reg134 of DSP1.
-BUS, D-BUS, timing signals, and the like, and these signals control the entire MLOGIC3. Control unit 200
Generates the timing required to operate the transmitting unit 220, the receiving unit 240, and the common unit 260, and outputs the DSP1 via the BUS.
Is connected to

Among the output signals of the control unit 200, the signals with -WP and -RD are signals obtained by decoding the I-BUS signal, and thereby control the data transfer with the data input / output circuit in each block. Signals with -SW are switch switching signals for switching elements in each block in accordance with the operation mode. The transmission unit 220 is connected to the outside via the S-I / F 10, inputs the transmission data SD by a timing signal, ST 1, ST 2, or TBT signal, and generates the transmission sample timing TXS through the SMPLT interface 11.

The loop signals RD ′ and RT ′ are input from the receiving unit 240, and the monitor signals SD ′ and ST ′ are output to the common unit 260. The receiving unit 240 is connected to the outside via the S-I / F 10, outputs the received data RD by the timing signals RT and RBT, and generates the reception sample timing RXS through the SMPLT interface 11. ET "is a monitor signal. Common unit 260, in addition to the general-purpose input-output circuit P ₀ to P _7, the internal signal _{SD ', ST 1', RT} "
Has a function to monitor

The feature of this configuration is that the instruction signal of DSP1 is extracted and the instruction is interpreted in this part. For this,
There is an advantage that a new instruction can be added without affecting the original instruction of DSP1.

Here, the transmission unit 220 includes a timing divider that generates a sample timing for transmission, a serial / parallel conversion circuit that inputs transmission data, a transfer rate generator, a timing control circuit, and the like. Hereinafter, the configuration of the timing generating portion will be described with reference to FIG.

In FIG. 7, reference numeral 221 denotes a 1-bit shift register that first latches SD, 222 denotes a serial / parallel converter (S / P) that receives an output of the 1-bit shift register 221 and converts a serial signal into a parallel signal, 223 instructs S / P222 output (SD-
RD) is a gate for inputting to the BUS, 224 is a frequency divider (ST) for generating the SD transfer timing, 225 is a register for setting the frequency division ratio in ST224 by an instruction (ST-WR), 226
Is the frequency divider (TXS) that generates the sampling timing, 2
27 is a transmission timing control register.

FIG. 8 shows the operation in the case of transmission by the internal timing operation of the synchronous modem. In the case of synchronous transmission and normal transmission, the switch 228 is set to the a side. The TXS 226 divides the CLK output generated by the control unit 200 to generate a TXS signal. The output CO of the TXS 226 generates a clock synchronized with the rise of the TXS, and writes the frequency division ratio in the ST register 25. Then, the ST frequency divider 224 generates the ST2 signal according to the frequency division ratio. The ST2 signal is supplied to an external terminal device and used as transmission timing of the transmission data SD.
The transmission data SD is supplied to the bit shift register 221 and the S / P 222 to receive the transmission data SD.

The 1-bit shift register 221 latches data at the rising edge of ST2, and the S / P 222 inputs this output (SD ') at the falling edge of ST2. In addition, since the above-described SOF is activated at a timing substantially synchronized with the TXS signal, the DSP 1 can operate in synchronization with these timings. Therefore, the modulation timing can be determined by counting the number of interruptions by the SOF, and the transmission baud timing signal (SBT) can be generated by setting the modulation timing in the transmission timing control register 227 by an instruction (eighth). The figure shows an example of 1200 bps).

In the case of an asynchronous modem such as an FSK type modem, the modulation is performed at the TXS timing, and the switch 228 is set to the TF
It is tilted to the b side by SK-SW, and SD is taken in at every TXS timing. As shown in FIG. 9, the receiving unit 240 includes a receiving sampling timer, a transfer rate generator, a parallel-to-serial converter that outputs received data, a timing control circuit, and the like. 241 reads the demodulated data via the BUS of the control unit 200 in accordance with the DSP1 instruction (RD-WR) and outputs it as received data (RD) through a 1-bit shift register (DFF) 242. This is a shift register (P / S) to be converted. 243, a switching circuit (SEL) for switching the transfer clock of the P / S 241; 244, an RT register for setting the transfer rate (RT) divider 245 by the DSP1 instruction (RT-WR); The RX register that sets the division ratio of the RXS divider 247 that generates the timing RXS by the DSP1 instruction (RXS-WR).
249 is a 1-bit shift register (DFF) which outputs the RSync signal and the RBT 'signal in response to the instruction (RCR-WR).

In the case of a synchronous modem, the switching circuit 243 is tilted to the side a, and the switching ratio is set according to the specified frequency division ratio set in the RXS register 246.
An RXS divider 247 generates a reception sample timing signal RXS. The A / D converter in CODEC2 quantizes the modem input signal at this timing by the RXS signal and takes in the data into SIR141 of DSP1. At the timing synchronized with the RXS, an interrupt occurs in the DSP 1, and in this interrupt processing, data is fetched from the SIR 141 and reception processing is performed.

Here, as the initial adjustment of the timing, first, a reception process is performed at an arbitrary timing in units of an interrupt process, and as a result, an arbitrary demodulation timing is obtained for internal processing by managing the number of interrupt processes, and the demodulation is performed. A timing shift is detected from the demodulated signal due to the timing, and the timing shift is adjusted by adjusting the RXS frequency division ratio and correcting the number of interrupt processes. The RSYNC signal is used to adjust the timing of the RT frequency divider 245 to the demodulation timing synchronized with the corrected RXS timing. In other words, the instruction (RCR) from DSP1 at the SIF interrupt timing at the baud timing
−WR), the RT divider 245 is reset by the RSync signal from the timing control register 248, but the RT divider 2
45 operates by receiving the output CO of the RXS frequency divider 247,
The RT timing is synchronized with the S timing.

After the above timing initial adjustment is completed, as shown in FIG. 10, the demodulated data can be written to the P / S 241 by the DSP1 command (RD-WR) in synchronization with the falling change of the reception demodulation timing RBT '. For example, data transfer is performed by delaying this output RD "by one bit at DFF242. The reception modulation timing RBT is shifted by RT at DFF249 at which RBT 'is output from the timing control register 248 by an instruction (RCR-WR). Is output.

In the case of an asynchronous modem such as the FSK method, S
The EL 243 is tilted to the b side, and the received data demodulated at the timing of the RXS signal is output at the timing of the RXS signal.

FIG. 11 is a diagram showing a configuration of the digital PLL 4. No.
In FIG. 11, reference numerals 300 and 310 denote phase comparison circuits, and 320 and 330.
Is a variable frequency dividing circuit, and 301 and 311 are OR gates.

For input signals TXS, RXS, CLK, RES from MLOGIC3, CO
By comparing the phases of the sampling timings RXS 'and RXS' inside DEC2, generating reset signals RES-T and RES-R for CODEC2, and correcting the period of CLK-T and CLK-R, During the correction, the number of CLK-T (or CLK-R) in one cycle of the sample timing does not change, and CLK-T (or
By dispersing the period of CLK-R) so that it does not fluctuate sharply, the phase is adjusted so as to operate at the sample timing designated by DSP1 without impairing the characteristics of CODEC2.

FIG. 12 is a timing chart for explaining the operation of the digital PLL 4. In the figure, only TXS is shown, but R
The same is true for XS. Immediately after turning on the power to the modem, a reset signal (RES) is input from an external circuit to reset the sequential circuits such as flip-flops and counters. Operating from this state, the internal sampling timing (=
If TXS ') is larger than TXS (1), TX
At the end of S, a pulse (RES-T) is generated, and the transmission part of CODEC1 centering on D / A conversion is reset.

After TXS and TXS 'are synchronized by reset (2),
Intentionally shortened the cycle slightly by DSP1 signal processing
In the case of TXS (3), in synchronization (4), the cycle of CLKT at which the variable division period occurs becomes short, and the end timing of the internal TXS 'is advanced to synchronize. Whether the phase comparison circuit 300 generates a reset signal (RES-T) or responds by changing the width of CLK-T is determined by the characteristics of the phase comparison circuit 300. In the case of the embodiment, the CLK, 7.3728 MHz, Sample period 96
A window of ± 1.5 μS is provided for 1/00 second,
Fine adjustment was made inside and reset was made outside. In this case, the sample period is 768 clock periods, but the number of operation clocks of CODEC2 is 128.

When correcting the sample period, for example, set the period to about 1
In the case of (4) in which μS is shortened, the frequency is commanded to the variable frequency divider 320, and as a result, the variable frequency divider 320 narrows the width by one CLK for every 16 operation clocks (CLK-T), Correct the sample timing by making the clock slightly denser. Conversely, if the sample period TXS is slightly extended (about 1 μS in the example) (5), the phase comparator
300 instructs the variable frequency divider 320 to decrease the frequency. As a result, the variable frequency divider 320 increases the width of one CLK for every 16 CLK-Ts and slightly coarsens the clock CLK-T. Modify the sample timing. The same goes for the RXS side.

Note that the modem standard defines the modulation frequency and its accuracy, and the accuracy is ± 0.01%. Therefore, even if the maximum deviation occurs, the required correction amount is about 1 μS only after several pulses of TXS and RXS have passed, and usually RES-T and RES-R except for the initial phase adjustment.
Does not occur.

CODEC2 is a D / A unit that converts a digital signal to an analog signal as shown in FIG. 13, and an interface between an A / D unit that converts an analog signal to a digital signal and an external circuit,
It comprises a control circuit, a timing circuit, etc., 400 is a transmission buffer register (T-BUS), 410 is a D / A conversion circuit (D-A
/ A), 420 is an attenuation circuit (AT), 430 is a smoothing filter (PF), 440 is a switch (SW) for switching the signal flow for testing, and 450 is an analog output buffer.

460 is a 16 frequency divider, 470 is a transmission side timing signal generator (TTMG), 500 is a digital output buffer, 510 is an out-of-band signal processing filter (PF), 520 is an amplifier circuit (AMP), 53
0 is an A / D converter (A / D), 540 is a receive buffer register (R
-BUS), 550 is a changeover switch (SEL), 560 is a 16 frequency divider,
570 is the receiving side timing signal generator (RTMG), 580 is CO
This is the system control register (CONT) for the entire CEC.

The signal on the left side of FIG. 13 is the CODEC-I / F signal 6 of the DSP 1, and a 16-bit wide digital signal is input at the timing shown in FIG.

FIG. 14 shows the input and output of the CODEC-I / F signal 6 and the CO of FIG.
6 is a timing chart showing how DEC2 operates. When the power is turned on to the modem LSI, a system reset signal is generated immediately after the power is turned on, and these are DSP1, MLOGIC3, DPLL4
Through the RES-T signal and input. In this case, CLK
It is assumed that −T is continuously input, and that TXS ′ is synchronized with TXS generated by MLOGIC3 by DPLL4. When the RES signal returns to "L", the DSP1 program starts operating and initializes each part.

CODEC2 initialization starts from CONT580. CONT580 is
It controls the switching of the attenuation SW440 of the ATT420, controls the amplification of the AMP520, etc.
Control signals are exchanged through CODEC-I / F6. That is, CONT1 is a signal that signals a control signal to be input to CONT580 from SO, and CONT2 is a signal that controls the control signal via SI to CONT5.
This is a signal to be read from 80, which is
The shift register in 0 is ready to be loaded, TBUF400 is disabled, and the frequency divider 460 also outputs the SOEN signal (3.6864MHz
(A signal indicating the validity of the data transfer of "H") during the 16 pulse section of the clock CLK-T.

With this signal, the control signal written to the SOR 143 of DSP1 by the instruction of DSP1 is stored in the shift register in CONT580. The above capture state is reset at the timing of the falling edge of SOEN, and the subsequent sample timing
For TXS, the input data input to D / A410 is TBUF400
Is stored in TBUF400, like CONT580, is also composed of a shift register, as shown in FIGS. 5 and 14.
Sends a 16-bit transmission signal at each TXS falling timing.
Receive from O.

The received transmission data is converted to an analog signal by the D / A 410, the signal size is adjusted by the ATT 420, and the out-of-band signal is removed by the PF 430. Then, the Aout terminal is driven by the transmission buffer 450 through the SW 440 and output. . These are created by timing signals generated by the TTMG470. The TTMG is composed of a counter for dividing the CLK-T input to generate TXS 'and a combinational circuit for synthesizing the divided pulse of each stage of the counter. The TTMG is initialized at the REST timing, and the CLK-T768 The timing required for the TXS 'and the other transmitting side is generated for each unit and at a timing substantially uniformly distributed.

Therefore, unless REST goes “H” again,
The operation is performed by allocating 768 CLK-T signals to one cycle.

When receiving the analog reception waveform Ain, the reception side receives the analog reception waveform Ain in the reception buffer 500, and enters the filter PF510 via the switching circuit 440. The PF510 is a low-pass filter that removes out-of-band signals prior to A / D conversion.The output is amplified by the AMP 520, converted to a digital signal by the A / D 530, and then shifted to the RBUF54, a shift register.
Store in 0. This digital signal is passed through SEL550
The signal is output as SI and input to DSP1 through SIR141.

The receiving side is also operated by a timing signal generated by a timing generation circuit (RTMG) including a counter and a combination circuit, as shown in () of FIG. It is the same as the transmitting side that the timing necessary for the operation of the receiving side other than RXS 'is generated at the timing initialized by the RESR and distributed almost uniformly every CLK-R768. Therefore, unless RESR becomes “H” again,
The entire operation is performed by allocating 768 CLK-R signals as one cycle.

The reason for uniformly dispersing the timings is that the noise generated by the digital circuit is unbalanced and becomes large noise, which has the effect of preventing strong influence on the analog circuit. For this reason, the D / A 410 and A / D 530 are of the oversampled type, which operate at the timing of the power-of-two ratio and are configured using a serial operation circuit as shown in FIG.

That is, as shown in FIG. 15 (a), the D / A 410 converts the TXS ', that is, the 16-bit digital signal output at the sampling timing of 9.6K samples and 1 second, into a sample of 4 times the sampling rate (38.4K samples / second). Hold circuit (HOLD) 411 to hold while resampling at the timing
This output is processed and a low-pass filter (LPF) that removes unnecessary high-frequency signal components is sampled at a fine cycle of 412, output of LPF412 output at 38.4K samples / sec. And a high-speed 8-bit D / A conversion circuit (D / A) 414 for converting the output into an analog signal. The output of the TBUF 400 is passed to the ATT 420.

Among them, the analog circuit is a part of the D / A 414 and is limited.
Since it is operated at a power of 2 synchronized with the above and at almost uniformly dispersed timing, almost no quantization noise and switching noise can be seen in the analog signal output at 614.4K samples / sec. / Noise ratio. Further, since the final sample timing is as high as 614K samples / sec and the signal band is about 3KHz, it is possible to use the filter 430 with low required accuracy.

In the case of a modem, the LPF 412 requires extremely strict accuracy than the characteristics of a transmission line. However, since the LPF 412 is realized by a 32-bit operation using a digital circuit, excellent characteristics can be realized. In addition, as shown in FIG.
A / A to DSP1 SIR141 with 6K samples / sec sampling cycle
Operates so that D-converted analog signals can be sent out.
First, an 8-bit A / D converter (A / D) 531 converts an analog signal input from the AMP520 into a sample at a sample period of 1.2288 MHz.
Convert to a bit digital signal.

Next, this output digital signal is input to a first decimation circuit (DECM1) 532 which converts the output digital signal into a signal of 307.2 K samples / sec.
Further, the digital signal having a sample period of 307.2 KHz is input to a second decimation circuit (DECM2) 533 and converted into a digital signal having a sample period of 38.4 KHz. Then put this signal into a low pass filter (LPF) 534 to save 3.4K
Hz or higher signal is deleted, and the decimation circuit (DUMP) 535
To obtain a digital signal with a period of 9.6K samples / sec.

These circuits use the A / D / D / A conversion cycle required by the system at a much higher sampling frequency than the A / D
In order to operate the D / D / A converter, it is generally called an oversampled A / D / D / A conversion method.

In terms of A / D conversion, the A / D531 provides 8-bit precision. However, by thinning this out, the amount of noise can be reduced. Accuracy is expected to improve, and as a result, 15-bit accuracy is obtained as a whole. Also, noise can be removed by the LPF 534, which is about 3 dB in this embodiment. When these are summed, a conversion accuracy of about 95 dB is theoretically obtained. Actually, it is a finite-length operation, and the generation of noise due to the operation is unavoidable, and noise from the analog circuit is unavoidable, so that the accuracy is less than 90 dB.

Next, software incorporated in DSP1 in the VLSI modem of the present embodiment will be described below with reference to the drawings.

Figure 16 shows the overall configuration of the software.
It consists of a main process and an interrupt process. Here, the modulation / modulation processing of the modem is roughly classified into two according to the time processing unit. One is a process that is performed once within one modulation period based on the modulation timing (hereinafter, referred to as baud process). For example, V.27ter 4800 bp determined by the CCITT standard
In the case of s, since the modulation speed is 1600 baud, 625 μs (=
1/1600). The other one is
Based on the sampling frequency, this is a process that is performed once within the time of (1 / sampling frequency). (Less than,
This processing is called sample processing).

Now, if the sampling frequency is 9.6KHz, 104μs
(= 1/9600) must be processed. Considering full-duplex processing, each of the transmission processing and the reception processing includes a baud processing and a sample processing, and is divided into a total of four processings.
If these four processes are not processed in real time, full-duplex processing cannot be realized. In particular, transmission processing and reception processing are generally asynchronous, so transmission baud processing and reception baud processing must be performed independently. There is. Therefore, as shown in FIG. 16, the reception processing is performed in the main processing, and the transmission and reception sampling processing and the transmission baud processing are performed in the interruption processing.

That is, as shown in FIG. 17, first, the A / D conversion ends in synchronization with the reception sample timing RXS, and the A / D
When the D-converted value is input, an interrupt is generated in the DSP 1 by the interrupt flag SIF, so that in the interrupt process by the interrupt, the process performed at each reception sample timing, that is, the above-described reception sample process can be performed. On the other hand, in the case of transmission, similarly, in synchronization with the transmission sample timing TXS, when data transfer from the SOR 145 is transferred to D / A conversion, S
Since an interrupt is generated in the DSP 1 by the OF flag, the process performed at each transmission sample timing in the interrupt process by the interrupt, that is, the above-described transmission sample process can be performed.

The baud process is a process performed once in one modulation cycle. For example, in the case of 480 bps of V.27ter, one modulation cycle is 625 bps.
μs, which is six times the sampling period of 104 μs. Therefore, if the interrupt processing performed in synchronization with the sampling period is performed six times, it is one modulation period. That is, one modulation cycle can be managed by counting the number of interrupt processes. Therefore, after the reception sample interrupt is counted six times, the next new reception baud process may be performed. The transmission can be performed in the same manner. The baud timing can be notified in the form of an interrupt count value or a flag.

When an interrupt occurs, the contents of the program counter 131 of the DSP 1, that is, the current program counter value of the main processing are saved in the stack 132, and a predetermined PC address (vector address) for storing the start address of the interrupt processing is stored in the PC.
Set. This starts the interrupt processing. When the interrupt processing ends, the program counter value saved in the stack 132 is set in the program counter 131, and the main processing returns. In the interrupt processing, first, the register is saved, and then, as a determination of the interrupt requirement, the ST is executed.
The SIF or SOF flag reflected in R138 is checked to determine which interrupt causes a jump to interrupt processing.

As shown in FIG. 16, it is first determined whether or not the interrupt is caused by the SIF flag. If the interrupt is caused by the SIF flag, the interrupt is caused by the sample timing on the receiving side, so that the reception sample processing is performed. Here, the count of the reception sample interrupt, that is, the reception sample counter is counted. When one modulation cycle is 6 sample cycles, for example, the reception sample counter is assumed to repeatedly count from 0 to 5, and the reception sample counter is set to 0. , RBT 'is output by the timing control register 238 to notify the modulation timing to the outside.

When the reception sample processing is completed, it is next determined whether or not an interruption due to the SOF flag has occurred. If the interruption is due to the SOF flag, the transmission sample processing is performed because the interruption is due to the sample timing on the transmission side. Thereafter, the transmission sample interrupt is counted, that is, the transmission sample counter is counted. For example, if the transmission sample counter is 0, the transmission baud processing is performed. Thus, the transmission baud processing is performed for every six transmission sample counters, that is, the transmission baud processing can be performed for each modulation cycle. Also, as shown in FIG. 16, the reception baud processing is performed in the main processing, so that the processing can be performed asynchronously with the transmission baud processing, and full-duplex processing can be realized.

Here, in the main processing, the reception baud processing is executed by notifying the reception modulation timing by the value or flag of the reception sample counter in the interruption processing by the reception sample interruption. FIG. 17 shows a schematic flow of the full-duplex processing.

In FIG. 16, after the transmission process is completed, it is further determined whether or not there is an interrupt. If there is an interrupt, the interrupt factor is determined and the interrupt process is performed. If there is no interrupt, the registers are restored. And returns to the main processing. This is because the interrupt is masked so that a double interrupt does not occur during the interrupt processing. Therefore, as shown in FIG. 18, the transmission is performed when the interrupt processing is performed by the reception interrupt in the full-duplex processing, for example. In some cases, the SOF flag, which is the cause of the interrupt, is set. In this case, if the process returns to the main side without determining whether or not there is an interrupt at the end of the interrupt processing, as shown in FIG. When the interrupt mask is released by returning to the process, since the SOF flag is already set, the process immediately shifts to the interrupt process, the register is saved, and the cause of the interrupt is determined.

However, by determining whether there is a new interrupt factor at the end of the interrupt process by looking at the SIF or SOF flag reflected in the STR 138, as shown in FIG.
There is no need to return to the main processing, and the processing is simplified without saving and restoring registers twice in the interrupt processing.

In the above description, the transmission baud processing is performed by the interrupt processing. However, as shown in FIG. 19, a configuration in which the reception baud processing and the transmission baud processing are performed by the main processing may be adopted.

In FIG. 19, the transmission baud processing is performed after the reception baud processing is completed, and the difference from the example of FIG. 16 in the interruption processing is that the transmission baud processing is replaced with the transmission baud processing at the transmission baud timing.
This is the part where SD is taken in and saved. That is, the output of the S / P 222 for converting the SD of the MLOGIC3 from serial to parallel is saved by the gate 223 in the internal data RAM. In the transmission baud processing, baud processing such as encoding is performed using the saved SD.

Also, when transmitting, the terminal or the operator
(Transmission request) This signal is detected by software by writing a signal to an input register in the host I / F circuit 100 of the DSP 1 or by setting the general-purpose input / output circuits P _{0 to} P ₇ in the common unit 260. When the RS is OFF, the transmission operation is prohibited. Similarly to the transmission side, the processing on the transmission side writes an RXEN (reception enable) signal to an input register in the host I / F circuit 100 of the DSP 1 or uses the general-purpose input / output circuits P _{0 to} P ₇ in the common unit 260. Whether to detect this by software and prohibit the receiving operation depending on the setting, or to start the receiving operation if the signal is sent through the line and is large enough to be received , Only one of the transmission processing and the reception processing can be processed even in the full-duplex processing state.

〔The invention's effect〕

According to the present invention, a digital linear codec of an oversampling type and a relatively high S / N of 15 bits or more has a small analog circuit portion and a high accuracy A / D, D / D
A conversion can be realized, a one-chip integration with other digital circuits can be achieved by a manufacturing process for digital circuits, a high-speed modem can be integrated on a one-chip semiconductor, and two programmable and maskable independent circuits can be integrated. Two interrupt generating means that have independent sampling timers and start DSP interrupts independently of each other in synchronization with the A / D and D / A conversions of the digital linear codec that is processed in synchronization with each sampling timer. The sample processing can be performed independently by the interrupt processing of those DSPs, and the baud processing can be managed by counting the sample processing, making it easy to build a program without having to take special timing. In addition, the processing efficiency can be increased, and high-speed modem 1-chip LS
Full-duplex processing can be realized by I-integration, and there is an effect that miniaturization and cost reduction can be achieved.

Further, the modem using the VLSI of the present invention can process all the modulation and demodulation functions and operation procedures with one piece of software, which facilitates multi-mode one-chip integration, and changes and corrections of programs and parameters. effective.

[Brief description of the drawings]

FIG. 1 is an internal block diagram of a circuit according to an embodiment of the present invention, FIG. 2 is a block diagram of an internal circuit of DSP1 in FIG. 1, FIG. 3 is a circuit block diagram of a control unit in FIG. Is the same CODEC-I / F
5 is a timing chart of FIG. 4, FIG. 6 is a block diagram of an internal circuit of the MLOGIC3 of FIG. 1, FIG. 7 is a circuit diagram of a transmitter of FIG. 6, and FIG. 7 is a timing chart, FIG. 9 is a circuit diagram of the receiving unit, and FIG.
11 is an internal circuit block diagram of the DPLL4 of FIG. 1, FIG. 12 is a timing chart of FIG. 11, FIG. 13 is an internal circuit block diagram of the CODEC 2 of FIG.
14 is the timing chart of FIG. 13, and FIG. 15 is the timing chart of FIG.
FIG. 16 is a detailed block diagram of the D / A unit and the A / D unit, and FIG.
FIG. 17 shows an embodiment of the overall configuration of the program incorporated in the SI, FIG. 17 is a timing chart of FIG. 16, and FIG.
FIG. 16 is an auxiliary diagram for explaining FIG. 16, and FIG. 19 is a diagram showing another embodiment of the entire configuration of the program incorporated in the VLSI. DESCRIPTION OF SYMBOLS 1 ... Digital signal processor 2 ... Digitalization linear codec 3 ... Modem exclusive logic 4 ... Digital phase locked loop circuit

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasuyuki Kojima 3-1-1, Sachimachi, Hitachi-shi, Ibaraki Pref. Hitachi Research Laboratory, Ltd. (72) Inventor Yoshimune Hagiwara 1-280, Higashi-Koigabo, Kokubunji-shi, Tokyo (72) Inventor Kouji Imazawa 1450, Kamizuhoncho, Kodaira-shi, Tokyo Inside the Musashi Plant, Hitachi, Ltd. (72) Inventor, Hajito Ishihara 2326 Imai, Ome-shi, Tokyo Device Development Center ( 56) References JP-A-58-40944 (JP, A) JP-A-63-187842 (JP, A) Nikkei Electronics, No. 441, p. 159-162 Proceedings of the IEICE Autumn National Convention, Vol. B-2, p. B-2-186 (58) Field surveyed (Int. Cl. ⁶ , DB name) H04L 27/00-27/38

Claims (1)

(57) [Claims] An A / D and D / A converter, a digital signal processor, first and second sampling timers that operate independently of each other, a logic circuit specific to a modem, and the first and second sampling timers. First and second interrupt generating means for independently activating an interrupt to the digital signal processor in synchronization with a sampling timer, wherein the digital signal processor is capable of at least performing reception processing for each modulation period of a modem. A full-duplex communication modem which performs transmission processing and reception processing for each sampling period by interrupt processing by an interrupt generated by the first and second interrupt generating means.