JP2003529947A - Wireless communication system and method - Google Patents

Abstract

Abstract: A system including, inter alia, a wireless communication system integrating a wireless receiver and transmitter with a host computer platform, including a data access channel for sending digital data representing a baseband modulated signal to a memory space of an application program, and A method is provided. That is, the system employs wideband digitization of incoming signals such as RF signals, directs the digitized data to the application memory space of a general purpose workstation, and performs digital signal processing to obtain the information encoded in the digitized signal. It can be executed by an application program running on a general-purpose workstation.

Description

Detailed Description of the Invention

[0001] described this matter of the relevant application claims priority to US patent application Ser. No. 60 / 071,485, entitled, filed on January 13, 1998 "virtual radio", the contents of the application as a reference Included herein.

TECHNICAL FIELD The present invention relates generally to communication systems, and more particularly to wireless communication systems capable of communicating audio, video and data signals.

[0003] Wireless telecommunications field of invention is rapidly expanding in recent years, demand for wireless telecommunication services and devices continues to increase. This significant growth is, in part, due to the proliferation of new communication standards and the development of new hardware technologies. For example, the successful adoption of the cellular telecommunications standard will fuel the growth of the mobile phone industry and introduce new hardware technologies that will increase the conversion rate between the analog and digital domains and increase the digital signal processing capability. , Has been promoting the development of smaller and more power-saving mobile phones.

Although these entirely new standards and hardware technologies have provided many new devices that often work very well, these devices are generally application specific and the features that the device may provide. It is based on an application specific hardware design that is almost always limited to. Among other things, new hardware devices typically include dedicated bus architectures, components, and other specialized devices that make the system less flexible, harder to upgrade, harder to expand, and harder to shrink. , Has adopted a special purpose hardware architecture.

Digital radios, or software radios, have been developed to address some of the scalability issues that arise from the use of dedicated hardware architectures. Software radio employs analog-to-digital converters and digital signal processors to process broadcast waveband signals and produce a data stream representing the information being transmitted on a selected channel. EDN magazine (1996
See Brannon and Brad, Nov. 1, 2013, "A Wide Dynamic Range A / D Converter Opens the Way to Broadband Digital Radio Receivers." The data stream is then passed to a software application that further processes the data stream to execute the application at hand. For example, a software radio application providing the functionality of an FM radio receiver processes an incoming data stream to decode a signal transmitted at a particular radio frequency assigned to a particular radio station, processing the RF signal. Can output music or audio signals encoded in.

Software radio thus provides greater flexibility by providing a data stream to a computer system that can employ an application program that processes the data stream in accordance with program instructions. That is, by changing the software that processes the data stream, the user can upgrade or extend the functionality performed by the software radio. This provides a higher degree of flexibility and thus a stronger telecommunications device.

In addition, software radios now exist that provide a data stream of modulated or demodulated data to an application program that can run on a general purpose workstation. The use of the general purpose workstation allows for easier integration of wireless communication functions with data processing functions and wireless communication with other data processing systems. For example, the increased integration level above
Along with the resources available on the data processing platform, such as network communication, higher capacity data storage, and other such capabilities, the wireless communication capabilities of software radio can be boosted.

While software radio provides more flexibility than application-specific hardware architectures, software radio does provide application-specific digital hardware for signal processing that derives a data stream representing information encoded in a broadcast signal. That is, a digital signal processor (DSP) is still used. Therefore, in software radio, most of the signal processing is typically done in dedicated digital signal processing hardware on an application-specific platform, and there is no opportunity to modify or change the way the signal processing is done to produce the data stream. Little or no given. For example, even in software radio, the basic signal processing, which determines the channel width, the number of channels that can be processed by the software application at one time, and other similar parameters, may still be done in dedicated hardware.

Therefore, software radios still draw a boundary between application software of the user and demodulated data available from the RF signal, an application specific hardware architecture. This limits the flexibility of software radio and diminishes its ability to provide telecommunications capabilities to the data processing environment.

[0010] SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a wireless communication device that can be modified or changed signal processing being performed by the wireless communication device.

Another object of the present invention is to provide a wireless communication system and method that provides greater flexibility to a data stream generated by a wireless communication device.

Other objects of the invention will in part be obvious and will in part be presented in the following description of the systems and methods presented herein.

The present invention provides, among other things, a system and method including a wireless communication system that integrates a wireless transceiver with a general purpose processing platform and includes a data access channel that directs digital data representing a modulated signal to a memory space of an application program. To do. That is, the system employs wideband digitization of incoming signals such as RF signals to direct the digitized data to the application memory space of a general purpose processing platform to obtain information encoded in the digitized signal. Can be performed by an application program running on a general-purpose processing platform.

Detailed Description of the Embodiments The foregoing and other objects and advantages of the present invention will be more fully understood from the following further description of the objects and advantages with reference to the accompanying drawings. Ah

To provide a general understanding of the present invention, certain embodiments are described herein that include a cellular receiver wireless communication system. However, the systems and methods described herein can be modified and altered for other applications, and additions and alterations to the embodiments described herein without departing from the scope of the invention. It will be obvious to those skilled in the art that

The systems and methods described herein include, among other things, a wireless access channel that integrates a wireless transceiver with a host computer platform and sends digital data representing modulated signals to the memory space of an application program. A communication system is included. That is, the above system uses wideband digitization of an incoming signal such as an RF signal to provide digitized data to the application memory space of a general purpose processing platform so that an application program running on a general workstation will receive the digitized signal. Can perform digital signal processing to obtain encoded information. For this purpose, the systems and methods described herein only optionally include a data interface board for exchanging data between the wireless transceiver and the input / output bus of the general purpose processing platform. Rather, a software routine library is optionally included with a framework that includes a class or set of classes that can embody an abstract design for a solution for wireless communication applications.

FIG. 1 shows a wireless communication system including a transceiver 12, a converter 14, a host platform 16, a persistent storage device 18, and an input / output device 20. The system 10 shown herein provides a platform on which processes for performing desired wireless communication operations can operate. As shown in FIG. 1, the transceiver 12 is connected to the converter unit 14 via a bidirectional communication path, and the converter unit 14 is subsequently connected to the host platform 16 via a bidirectional communication path.
The host platform 16 is connected to the persistent storage device 18 via a bidirectional communication path, and is also connected to the input / output device 20 via a bidirectional communication path. For purposes of illustrating the system and method of the present invention, the system 10 is described as including an application program that provides the functionality of a cellular receiver for processing the US cellular band. However, the system described herein is in no way limited to any particular application, including cellular modems, radio receivers, television receivers, wireless network interface cards, garage door openers and channel selection devices. Other application programs may be run on the system 10 to provide functionality for other purposes, including remote control devices such as, or any other type of wireless communication service, virtual device or application.

In one embodiment, the illustrated transceiver 12 is as a front end to the system 10 for capturing and converting selected broadcast band of interest into a baseband signal or a substantial baseband signal. It includes an RF receiver unit that is operable. For this purpose, the transceiver 12 shown in FIG. 1 comprises an antenna element 22 connected to a preamplifier 24, which is connected to a wideband filter 28.
The functional elements depicted in the transceiver 12 illustrate that the receiver can capture the RF signal and generate a wideband IF (intermediate frequency) signal that can be sent from the RF signal to the converter unit 14. In one embodiment, the transceiver unit 12 may include a commercially available RF receiver such as the type manufactured and sold by Tellabs Company of Lisle, Illinois, USA. However, it will be apparent to one skilled in the art that other transceivers or tuners may be employed and the transceiver device chosen will depend in part on the application.
For example, although the unit 12 shown in FIG. 1 is described as a transceiver, the transceiver 12 can be a receiver unit only or a transmitter unit only, depending on the application. In addition, the system 10 may include multiple transceivers, thus connecting multiple transceivers to a host platform and providing 10kH for each transceiver.
Receive through separate portions of the RF frequency band, including z to 1 GHz, or also through microwave frequency bands, infrared wavelength bands, visible light wavelength bands, or any other suitable communication frequency band or channel separate portions. Or it can be sent.

FIG. 1 further illustrates that the system 10 includes a converter element 14. Figure 1
In the illustrated embodiment, converter element 14 is an Analog Device Corporation of Norwood, Massachusetts, USA.
s Corporation) is a high performance analog-to-digital converter of the type manufactured and sold. The analog-to-digital converter functions to convert data from the analog domain to the digital domain, and vice versa for converting data between the digital domain and the analog domain.

The design and use of converters, such as converter 14, is well known in the electrical engineering arts, and any suitable converter can be employed in system 10 to convert signals between the analog and digital domains. . Furthermore, it is usually natural that the sampling rate driving the converter 14 depends on the bandwidth of interest, generally the highest frequency of the selected band, and the amount of oversampling desired to improve the signal to noise ratio in the digital domain. Will.

The converter element 14 is connected to the host platform 16 shown in FIG. 1 via a bidirectional path. The host platform 16 may be, for example, an IBM compatible personal computer running a Pentium class microprocessor having MMX capability and operating at a clock frequency of 200 MHz, and having an internal PCI bus of 33 MHz and at least 64 megabytes of internal random access memory (RAM). , A general purpose computer workstation. The host platform 16 is shown schematically in FIG.
, CPU 32, operating system 34, computer memory 36 capable of maintaining data memory space 38 and program memory space 40 for application processes, and output controller 48 connected to output device 20.
including. The host platform 16 is only one embodiment of a general purpose processing platform so that the term general purpose platform provides a flexible architecture to facilitate loading and running various application programs. It will be obvious to one skilled in the art to include a designed, computer platform.

In this example, host platform 16 operates to perform signal processing on the digitized wideband IF data sent from converter 14. For this purpose, the host processor 16 can run the process 44 shown in the program memory space 40. Operating system 34, which manages resources on host platform 16 such as memory resources provided by computer memory 36, may allocate a portion of memory space 38 to process 44 for use by process 44. The operating system 34 can manage the data flow between the interface 30 and the portion 42 of the data memory 38 allocated to the process 44, as described below,
Broadband data may also be transferred between process 44 and interface 30. The direct data transfer between the process 44 and the interface 30 provides the process 44 with a constant flow of data samples or blocks of data samples for processing, and also virtual memory operations, multi-level cache and I / O resources of the operating system 34. Reduce or eliminate time delays and transfer jitter that can occur in contention for

FIG. 1 further connects the host platform 16 to a persistent storage device 18, which may be a hard disk drive, tape drive, flash memory, or any other type of storage device capable of persistently storing data. Show what you can do. The system 10 can use the storage device 18 to store wideband IF data, demodulated data, or any portion of data processed by a signal processing application program running on the host platform 16. In FIG. 1, the host processor 16 has an input / output device 2
It is shown that an output controller 48 connected to 0 may be included. In one embodiment, the output controller 48 is a Stillwater, Okla.
It can be a sound card such as the Sound Blaster® card manufactured and sold by Creative Labs, Inc. For this example, the sound card can be connected to one or more audio input / output devices, such as a microphone and a pair of amplified speakers commonly used in commercially available personal computers. In other applications, the input / output device may include a video display such as a television monitor, as well as a data display for displaying data transmitted over a wireless channel. Further, the input / output device may also include a device, such as a remote control device, used to generate or respond to command signals transmitted over a wireless channel.

FIG. 2 illustrates one embodiment of an interface card, such as interface card 30 shown in FIG. More specifically, FIG. 2 shows an interface card 60 that can be made as a plug-in card, or daughter card, that can be inserted into an expansion slot on the motherboard of the host platform 16. As shown in FIG. 2, the interface card 60 is a PCI / PCI
Bridge 62, configuration memory 64, PCI controller component 68, output page address memory 70 and input page address memory 7
2, as well as output data memory 74 and input data memory 78. The interface card 60 shown in FIG. 2 includes a PCI / PCI bridge 62.
Via the input / output memories 74 and 78, such as the converter 14 shown in FIG.
Can be connected to the analog front end of the system.

More specifically, the interface card 60 shown in FIG. 2 may be a full size PCI card that complies with PCI specification version 2.0. The interface 60 functions as a bus master for direct memory access, direct memory access for offloading data transfer from the CPU 32,
It can serve as a target when accessing the control and status registers of the CPU 32.

The PCI / PCI bridge 62 connects the PCI card to the host platform 16
May be any commercially available PCI bridge device suitable for interfacing with the PCI bus of a workstation such as. Such PCI
One of the / PCI bridge components is Intel Corporation.
21050-AA manufactured and sold by the Corporation. PC
The I / PCI bridge 62 can be connected to the PCI controller element 68 via a communication path. The PCI controller element 68 may be any element suitable for controlling the operation of the interface board 62, and in one embodiment, Xilinx Corporation of Milpitas, Calif., USA. A Field Programmable Gate Array (FPGA) such as the type manufactured by The Company. The FPGA can be programmed to include a PCI controller and a DMA engine to provide a broadband interface between the analog front end and computer memory 36. The configuration data is stored in the configuration memory 64 and is accessed by the controller 68 at the start of operation or during operation.

In an optional embodiment, the interface card 60 can have a daughter card interface that can be connected to the converter 14. The daughter card can carry the converter 14 as well as any additional components that can be used to generate the data to be sent to the interface card 60. The illustrated interface 60 includes a pair of data buffer memories, such as FIFO memories, connected to both the receiver and transmitter units, each at the input and output of the above system. . If desired, the system can be provided with only one buffer that is only connected to the receiver or transmitter units. The buffer is
It absorbs the jitter caused by the burst access to the PCI bus of the host platform 16. On the input side, the buffer will hold in and hold samples until the interface device 60 has acquired the PCI bus and can transfer data to the memory 36 of the host computer 16. On the output side, the buffer is the memory 36
Excess data that has been transferred from, but is waiting to be accepted by converter 14 can be retained. The buffers 74 and 78 also serve to temporarily decouple the timing of the interface card 60, which typically operates with the PCI clock, from the converter 14 or the daughter card, which typically operates with the converter's sampling clock. This reduces or eliminates the need for the design to take into account synchronization or instability issues. The buffer also separates the data transfer and processing from the fixed rate domain of the analog front end, allowing the data transfer and processing to be bursty or sporadic as is common with shared data transfer resources.

In the embodiment shown in FIG. 2, the PCI interface between the interface card and the PCI bus has a capacity of about 1 Gbit / sec. By doubling the bus width from 32 bits to 64 bits and doubling the clock speed from 33 MHz to 66 MHz to allow wider bandwidth, P
There are also specific upgrade methods for increasing the CI bus bandwidth. Although the interface card 60 shown in FIG. 2 is intended to interface with a PCI bus, other embodiments transfer information from the ISA bus, S-bus, or interface card to the host workstation 16. It will be apparent to those skilled in the art that any other possible interface to the data bus can be implemented in the system described herein.

The interface card 60 shown in FIG. 2 operates as a PCI bus master and starts a transfer on the PCI bus. Therefore, the interface board 60
Can execute a DMA sample stream to or from computer memory 36 at high speed with minimal intervention of CPU 32. 1
In one embodiment, the interface card 60 is a computer memory 3
Implements one variation of the scatter / gather DMA that flushes data pages between 6 and the interface card 60. For this purpose, the interface card 60 has one FIF assigned to the input and one assigned to the output.
Included are two page address memories, which may be O memories. These memories may hold physical page addresses associated with buffers in memory space, such as virtual memory space organized by operating system 34. For example, at the end of one page transfer, the interface 6
0 can read the next page address from the head of the appropriate page address memory and start data transfer to or from the memory 36. The interface card 60 can trigger an interrupt if the supplied page address is followed by a low, and the page address can be supplied by the interrupt handler of the device driver attached to the interface card 60. Therefore, the interface card 60 stores the physical page address in the memories 70 and 72 directly mounted on the interface card 60. If desired, the page address can be stored in a memory table maintained in computer program memory 36. The interface card 60 shown in FIG. 2 can transfer all data pages between the computer memory 36 and the interface card 60. Of course, the transfer of all pages results in a page-ordered, total page length buffer that is easier for the operating system 34 to manipulate.

The interface card 60 is used by the operating system 3 to perform a direct memory access transfer of the data buffer to the application data memory 38.
Works in cooperation with 4. In one embodiment, operating system 3
4 provides a multitasking operating system including a virtual memory system for managing memory resources on the platform 16, Unix (Unix).
x) The operating system may be implemented. In one particular embodiment, operating system 34 is a Linux operating system that provides a Unix-like operating system to the Intel processor architecture. Other versions of Unix,
Alternatively, other operating systems can be employed without departing from the scope of the invention. Continuing with the Unix operating system example, the operating system can be modified to include device drivers and enhanced virtual memory systems, each operating to achieve a direct memory data transfer of a page of data. The device driver enables continuous data transfer between the interface card 60 and the application data memory 38. For this purpose, the system can employ a ring buffer that can transfer samples. The buffer may be part of the operating system kernel's virtual memory space and may be locked down to physical memory. Portions of memory can be locked down using any suitable technique, including the m_lock system call. The device driver can initially fill the input page address memory 72 with the address from the buffer at the beginning of the ring buffer. When this memory 72 is emptied to some programmable level, the interface card 60 generates an interrupt and the interrupt handler transfers more addresses from the beginning of the ring buffer. The level at which an interrupt can be triggered can be set so that there are enough pages left to capture incoming samples before the interrupt handler can supply a new address.

3-5 schematically illustrate the data flow that occurs as data travels through the transceiver 12 to the ring buffer and then to the application memory 38. In particular, FIG. 3 shows that the RF data transmission is captured by a receiver unit such as the transceiver 12 shown in FIG. In FIG. 3, the receiver includes a multi-band front end that can select the center frequency and width of an RF band under software control. For example, a 95X series wideband receiver manufactured by Rockwell Company can be adapted to software for selecting the center frequency and width of an RF band within a range extending from 2 MHz to 2 GHz. Provides a multi-band front end. Such a front end enables a multiband-multimode radio system. In another example, the front end may operate in the 2.5 GHz ISM band. As further shown in FIG. 3, a converter that may perform direct sampling, bandpass sampling, or other suitable sampling process to provide a digitized IF data stream for the wideband signal from the transceiver 12. It can be passed to a converter such as 14. In one embodiment, the IF signal is digitized by a 12-bit converter such as the AD9042 converter manufactured by Analog Devices. This converter can digitize signals at a rate of 40 MSPS (megasamples / second). This gives an IF bandwidth of 20 MHz. As shown in FIG. 3, the digitized IF data stream can be provided to an interface with a host computer, such as PCI interface 30 shown in FIG.

The PCI interface transfers data to the memory 34 of the host platform 16 at a transfer rate that is fast enough to meet the timing required by the process that is processing the signal of data, such as the process 44. You can For example, in order to transfer a 16-bit (ie, minimum sampling rate of 20 MHz) sample stream in a 10 MHz wide IF band to an application process, a data rate of 320 Mbit / sec is required. FIG. 3 shows a digitized IF to ring buffer 50 maintained in the virtual memory space of the kernel.
By indicating the transfer of data pages, the above data transfer to memory 34 is indicated. In FIG. 3, the ring buffer includes four buffers 52, 54, 56 and 58, and each buffer can store data as a plurality of pages. But,
It will be apparent to those skilled in the art that the number of buffers provided by ring buffer 50 is application dependent, and each buffer can contain hundreds of pages of memory space if desired. As discussed above, the interface card 30 has a list of page addresses that specify the memory locations to which the interface card 30 should supply data. As the interface card operates, data pages are transferred to the buffer of ring buffer 50 and ring buffer 50 begins to fill. That is, the ring buffer 50 stores the data to be transferred to the application memory 38 and, if necessary, sufficient data to accommodate the excess data when the application data cannot process the data at the rate of the incoming data. It provides a hangar, so that applications can occasionally catch up by processing the buffer faster than it fills.

To transfer data to the application memory space 38, the enhanced virtual memory system can operate to swap buffers from the application virtual memory space with buffers in the kernel virtual memory space.
For example, when the application requests data read from the device driver, the application program can transfer the data in the buffer at the end of the ring buffer 50. The system 10 performs a buffer swap operation to send the data in the buffer buffer at the end of the ring buffer 50 across the kernel-application boundary. 4 and 5 illustrate data transfer from the virtual memory space of the kernel to the memory space of the application program.

In particular, FIGS. 4 and 5 show the virtual memory space of the kernel and the buffers 50 maintained therein, along with the application memory space with the buffers 60 stored therein. The buffers shown in Figures 4 and 5 each provide a repository for a certain amount of data. In this hangar, virtual addresses indicated by the numbers 0 to 5 on the left side of the buffer 58 and numbers 6, 3, 58, 467, 2 on the right side of the buffer 58.
And 94 are associated with both physical addresses. Those skilled in the art will appreciate that the physical memory address is the computer memory 34 where the data is stored.
Represents a real physical memory location in. Similarly, in the application memory space, the buffer 66 has multiple pages with associated virtual memory addresses and physical memory addresses. For the buffer 66, the virtual memory address is indicated by the numbers 0 to 5, and the physical memory address is indicated by the number 2.
5, 98, 105, 3 and 6. In order to achieve data transfer between the kernel virtual memory space and the application program memory space, the physical memory of the buffer being transferred from the kernel virtual memory space is the bottom of the virtual address of the buffer 66 in the application memory space. Swapped out from, thus swapping the buffer provided by process 44 with the buffer in the system kernel. In one practice, each of the pages in the user buffer jumps to a separate physical page. The physical address of the page table enters the kernel and the user buffer is then swapped, thus altering the page table in the virtual memory system causes the system to effect data transfers to the application data space. Page table operation is back
(Bach) and J. Maurice, "Design of Unix Operation System"; Prentice-Hall, Inc. (1986)
In accordance with principles well known in the art, including those described in. Further, it will be apparent to those skilled in the art that any system for swapping buffers from kernel memory space with buffers in application memory space can be implemented with the systems described herein.

To facilitate buffer swapping, an application program such as process 44, upon initialization, verifies or defines the size and number of buffers in ring buffer 50, and thus any READ system made by the operating system. Process 44 to specify the buffer size that is also given to the call
Let us know. Therefore, when the application program executes the malloc () system call, memory allocation is performed that allocates a memory space that matches the buffer size of the ring buffer 50. As a result, the buffers swapped between kernel memory space and application space are the same size.

When outputting data, the process 44 uses the interface card 60.
Can be written in the card 60 as an I / O device. If necessary,
The device driver can maintain the buffer queue that process 44 wrote to the device driver. The size of the queue can be limited to prevent the application's processes from using all the physical memory available on the host platform 16. In operation, the device driver can initially store the address of the buffer at the head of the queue in the output page address FIFO 70. If the output page address FIFO 70 is empty, or is empty to some programmable level, the interface 60 will trigger interrupts and the operating system's interrupt handler will allow these buffers to If is available, the buffer at the head of the queue starts from the FIFO memory 7
Can be replenished with 0.

In one embodiment, the I / O system described herein is a system running on a 200 MHz Pentium Pro platform running Linux with a 33 MHz, 32-bit wide PCI bus. Is 512
It has been shown to support continuous sample stream rates up to megabits / second. Peak burst rate is 933 megabits / second for input,
The output is 790 megabits / second.

Returning to FIG. 1, with the digitized IF data in program memory 36, it can be seen that process 44 can then perform signal processing on the digitized IF samples to demodulate the transmitted signal. In one embodiment, process 44 includes a cellular receiver process that demodulates wideband digitized IF data to provide a wideband digital receiver that can operate in the "A-sideband" of the US cellular band.
This cellular receiver process provides a receiver that can continuously monitor the 10 MHz cellular band and provide the ability to demodulate FM signals anywhere in that band. In this embodiment, the transceiver 12 and converter 14 in a single unit containing a Tellab RF receiver that converts the 825-835 MHz band to a baseband signal and then samples the signal at 25.6 MSPS.
Can be integrated. The 12-bit sample stream is provided to interface card 30, which performs a direct memory access to send samples to memory 36 of host 16 for processing by process 44. Process 44 can control system parameters such as channel filter size and various sampling rates. This allows the parameters to be modified even when the receiver is operating.

FIG. 6 provides one functional block diagram of a cellular receiver process capable of demodulating sampled IF data being supplied to program memory 36. The cellular receiver process may be an executing computer program running in program space 40 of computer memory 36. The computer program is
It can be written in C, C ++, Java, or any suitable computer language and can be developed using standard software debug tools. The program also provides signal processing algorithm routines, Matteo Frigo and Steven G. Johnson.
It may also include routines from commercially available components, such as the FFTW package, developed by Microsoft Corporation and freely distributed. Other commercially available routine libraries or sets of classes for building user interfaces or other functionality can also be used. As known to those skilled in the art, the program can include multiple routines, classes, or modules, each performing some of the processing performed by the cellular receiver process 80. As shown in FIG. 6, the cellular receiver process 80 may include a channel selection stage 82, a quadrature demodulator stage 84, a low pass filter and decimation stage 88, and an audio band pass filter 90, and an output controller 48. . As discussed above, IF samples can be provided to the application program's memory space via a DMA transfer, and the cellular receiver process 80 can perform operations at a rate sufficient to process incoming samples, thus dropping sample drops. Can be avoided.

As shown in FIG. 6, the cellular receiver process 80 can employ a “data pull” architecture. Data flow is from input to output, while control flow is from output to input. By placing control downstream, the architecture can aggressively employ demand-driven execution, facilitating the construction of a system that can meet the requirements of downstream modules. Since the downstream component can only request the data that the downstream component needs from the upstream component, the total amount of processing that must be done is reduced. For example, consider an audio system to which various output devices can be attached. The driver for the output controller 48 is
For example, telephone quality audio with a sampling rate of 8 kHz for 8-bit quantization, or C with a sampling rate of 44 kHz for 16-bit quantization.
Depending on the application, such as D-quality audio, the amount of data needed can be controlled.

The cellular receiver process 80 shown in FIG. 6 uses an upstream-facing communication path to control the data transfer between each stage of the process. In one practice, each module can request data from its upstream neighbor. Thus, each module can call the immediate upstream module (or modules) requesting the required data. The data sent between modules can be processed on a sample-by-sample basis. Alternatively, process 80 may process the data block or payload. Payloads 92, 94 and 98 shown in FIG.
Data payloads such as can be large enough to take advantage of the data and instruction cache effects, but small enough to avoid unacceptable latency. To process the data payload, signal processing applications may employ algorithms designed to operate on blocks of data rather than single samples, including signal processing algorithms such as the Fast Fourier Transform. The development of other such algorithms was developed by Oppenheim.
), Et al., "Digital Signal Processing," according to principles well known in the art, including those described by Prentice Hall, Inc. (1975).

To process the data, the cellular receiver process 80 includes a channel selection filter stage 82. This stage, or module, has the task of extracting a narrowband FM signal from the 10 MHz wide frequency band (the AMPS channel bandwidth is 30 kHz) from the digitized IF samples. The stage 82 shown in FIG.
The above task is accomplished with a filter designed to combine a three-step conversion of the signal to baseband, low-pass filtering and decimation to an intermediate sampling rate. This processing step represents the largest part of the computational load. The channel selection filter 82 receives as input R _s = 25.6M from the RF front end.
The original samples of the PSP are used to create a composite baseband signal with a variable intermediate sampling rate R _D.

Separation of narrowband channels in wideband receivers is a computer-intensive task that is typically done with dedicated hardware such as a digital down converter (DDC) built into the dedicated hardware. . "Aye
E-Communications Magazine, Magazine, Vol. 33, No. 5 (199
May 5), pp. 46-54, "DSP Bottleneck" by Rupert Baines. The wideband signal is converted to a composite baseband signal by a quadrature frequency multiplier and then low-pass filtered to prevent aliasing due to decimation. There are decimation-only FIR filters that perform decimation operations with high efficiency-high efficiency is important because the sampling rate for wideband receivers can be 30 MSPS or more. The channel selection filter requires about 100 operations per input sample, and it is estimated that the total number of operations is 3000 MOPS (OPS: the number of operations per second).

In one embodiment, the channel selection filter 82 is a hardware DDC.
According to the configuration of. The individual steps of the down-converter process, ie, the generation of sine / cosine multiplication factors, frequency conversion and filtering, are performed at physically remote locations within the DDC to implement a hardware DDC configuration in software. Threads are employed to achieve a high degree of pipeline parallelism. In addition, subdivision parallel operation can be added within the FIR filter.

FIG. 7 shows reduced sample processing at a high sampling rate,
And another embodiment of a software DDC operating to reduce the rate at the beginning of a series of processes. As shown in FIG. 7, the software DDC takes the digitized wideband IF signal samples and provides them to two routines functionally represented at blocks 102 and 104 to perform frequency conversion and decimation low pass filtering. To do. Both common mode signals and quadrature signals are provided to logic block 106. Logic block 106 can collect the data and provide any formatting and transfer functions needed to send the data payload to another module. In this embodiment, a FIR filter (low order IIR) is used to generate an output signal that depends on the filter input sample x [n] and thus compute only the output sample y [n] needed after decimation. Used (for filters). This is, of course, to reduce the calculation load by using a large decimation coefficient that exists when a narrow band signal is processed by a wide band receiver. Furthermore, the pre-calculated frequency shift factor is incorporated into the synthetic FIR filter, so only phase correction will be required after each output sample is calculated. This feature makes the FIR filter time varying, but all variations can be combined into a single, time varying multiplicative coefficient applied after filtering.

In a particular embodiment, the frequency shifting and filtering multiplication and convolution steps are combined to create a synthesis filter.
To this end, the process transforms the real-valued received signal samples r [n] into the baseband (in frequency) by multiplying them by an appropriate complex exponential function, the first step in the selection of a particular channel:

[Equation 1] To execute. Here, f _c is a carrier frequency before conversion to baseband, and T _s is a sample interval. The above result is then filtered with an Mth order FIR filter h [m]:

[Equation 2] At this point, the two steps of frequency conversion and filtering are combined:

[Equation 3] Here, c [m] = h [m] e ^−2πfcmTs is a synthesis filter coefficient. This process, of course, not only reduces the number of operations, but also requires the operation of the unfiltered baseband signal x [n], which involves the burden of writing intermediate results to memory only for recall in the next step. Is to eliminate.
Also, although many techniques are available for designing real-valued FIR filters to meet the desired specifications in the smallest order, using complex-valued filter coefficients for h [m] is, of course, computationally expensive. This is so as not to impose extra. Therefore, the process reduces the required filter order M of the original LPF by reducing the complex coefficient FIR filter without increasing the computational load required for the final synthesis filter, compared to the real value h [m]. Recent advances in design are available.

The process described above is the only process that can down-convert incoming signals, and depending on the application, other techniques can be used that simplify construction and use less memory to store the filter coefficients. Can be used. It is also desirable in the process described above to calculate the filter coefficient c [m] and to change the frequency at which the filter is tuned (or pre-compute and store a separate filter for any desired frequency). In some cases, the desired carrier frequency must be known in order to recalculate the coefficients. However, since each set of filter coefficients is probably used several thousand to several million times,
Precalculation or recalculation can result in improved cost efficiency. This technique is similar to the idea of using an analytic filter to select and decimate only the positive frequency components of a real-valued signal for the passband of interest, but with the combination of transform and lowpass filtering in FIG. The filter can be quickly redesigned to select another f _c . Moreover, the overhead incurred by storing these coefficients is minimal if the processing is done on a general purpose processing platform and the data structure serves as an option / means for storing the data. Other filter designs can include the adoption of stochastic algorithms as an efficient way to prevent aliasing during the decimation process. Further, it will be apparent from the above description that the wideband processing system described herein can be used to process multiple channels in a wideband signal. In this case, each channel may be handled by a separate process or module, or by a single process looking for eight transmit channels. Furthermore, the system can be used to perform channel selection according to any method including FDMA, TDMA, CDMA or spread spectrum.

Returning to FIG. 6 again, in the composite FM signal, the desired information (voice in the case of a mobile phone) is carried by the instantaneous frequency which is the time derivative of the phase of the composite signal. The signal is therefore demodulated using a simple quadrature demodulation algorithm, which approximates the derivative of the signal phase by the phase difference between appropriately scaled successive samples. This quadrature demodulation is performed at stage 84 of process 80.

The last two steps of the process are implemented as a finite impulse response (FIR) filter. The first step can simply be a low pass decimation filter that removes high frequency components that cause aliasing when the sampling rate is reduced to an audio rate R _{A of} typically 8000 samples / sec. This is done in stage 88. The final step performed in stage 90 is an optional bandpass filter that removes out-of-band noise from the speech signal.

To facilitate the development of signal processing programs such as the cellular receiver process 80 described above, the system optionally provides, for example, a portable adaptive signal processing system with real-time constraints. , A programming environment that supports the development of application programs that process digitized IF samples. The programming environment can include a routine library, or a class or set of classes, written in a computer programming language such as C, C ++ or Java. If desired, the programming environment is a set of classes designed to be extended and subclassed by application programmers, along with some example applications designed to be used by application programmers and modified by application programmers. It can include a packaged, object-oriented application framework consisting of libraries. These sample applications generally constitute useful systems within their own right. The framework can provide "wired" interconnections between object classes that provide functionality and infrastructure for application developers. This interconnection provides the developer with an architectural model and design, freeing the developer from focusing on problem areas. By providing the infrastructure, the framework can reduce the amount of standard code that a developer must program, test, and debug. In general, the basic concepts of frameworks are familiar to those skilled in the art. Some examples of frameworks include the X toolkit, Motif toolkit, Smalltalk model-view controller GUI and MacApp (MacApp).
There is.

If desired, the programming environment can support adaptive signal processing, including adaptive programming to achieve adaptation to environmental factors, such as an application program implementing a channel equalizable modem. To this end, the system can provide an algorithm for detecting environmental changes, such as a channel estimation algorithm, and a mechanism for making specific system modifications based on the detected changes. Similarly, the programming environment changes dynamically,
Or it can support the adaptation of system operating parameters to the user in anticipation of the user's demands which may require modification. For example, the programming environment may provide for changes on the part of the user, such as the user changing the parameters representing the radio station. Similarly, the programming environment can provide for activation of controls that represent pushbuttons for selection between AM / FM broadcasts. The change between AM and FM broadcast requires a change in the algorithm used in the application program for demodulation of digitized IF data. The programming environment can further include routines or classes to enable functional adaptation. Functional adaptation provides signal processing techniques such as phase locked loops that are adaptive in nature.
These techniques generally adapt the signal and can modify system parameters or functions to meet specified requirements. For example, a receiver trying to lock on to the start frequency of a hopping sequence can adapt the system to probe various frequencies until a start code is found. This type of adaptation is done with no specified external constraints, or with external constraints, according to specified constraints. In addition, the system provides adaptations that are responsive to the amount of available resources. For example, the application program can detect whether there are spare CPU cycles available. Once the CPU processing power is determined to be available under the current system conditions, it runs a channel estimation algorithm that requires more computational power that can be used to seek better overall system performance. . Conversely, if resources suddenly become scarce due to bursts of activity by other processes, the system can adapt, perhaps by running algorithms that require less resources and sacrificing some robustness and accuracy.
Also, this form of adaptability clearly improves the performance of applications as faster processors become available.

The system described above allows for transmission and reception of cellular communications using the US cellular band. However, the advantage of doing the processing in software is that the sending process can be separated from the receiving process, so the systems and methods described herein allow the same device to receive and decode messages under a protocol with the same device. It enables a virtual communication temporary connection system that can and can send messages by another protocol. This allows the creation of temporary connections between disparate wireless systems. In another example, a radio broadcast using frequency modulation can be received, decoded, then encoded using amplitude modulation and rebroadcast, thus causing an AM receiver to receive the same data as an FM receiver. it can.

In another embodiment, the system described herein may include a network interface card (NIC) that implements software signal processing, thus providing a wireless network interface function that may be dynamically modified. Can be provided. This software wireless network interface is FS
It may be comparable to a commercial frequency hopping radio operating in the 2.4 GHz ISM band employing K modulation. Parameters such as FSK frequency shift and hopping channel spacing can be dynamically modified by software, and the constraints imposed by hardware are the IF bandwidth and the RF bandwidth over which the signal is converted. The ability to dynamically modify channel width, channel spacing and hopping sequences allows the system to adapt to its environment and provide better denoising and hostile jamming attack insensitivity.

The software network interface architecture can be a more sophisticated version of the OSI layering model that further divides existing link and physical layers, as shown in FIG. As shown, the software NIC can be connected to a hardware device that performs the processing of the frequency conversion layer 102 and the analog domain-to-digital domain conversion layer 104. If the data is in the digital domain, the software NIC can implement the other layers to be implemented for network data transfer. As shown in FIG. 8, these layers include a multiple access layer 108 and a modulation layer 1.
10 and line coding layer 112 are included. The multiple access layer 108 can be implemented by implementing any suitable protocol for sharing data transfer media. At layer 110, the modulation of selected IF data may provide for the collection of data transmitted on the wireless channel. At layer 112, the data can be coded according to transmission requirements. The data link layers 116 and 114 may also be implemented by any suitable technique capable of performing data encapsulation and decapsulation and access control of the transmitted and received media.

The sequence of the processing module for the transmission application is shown in FIG. The system interfaces with the host at the IP layer through the device driver 126, which is simply found in the kernel as another network device driver. However, instead of passing the packet to a hardware device, the driver passes the packet to user space 122, where a software radio process is executed. The first level of processing is network framing. As an example of this, packets can be framed to carry data and byte stuffing can be performed. A length code indicating the total length of the packet including the stuff value,
Can be inserted after the start code. The next module receives the continuous bit output by the network framing layer, performs byte framing, and inserts start bits, stop bits and parity bits.

The conversion of each bit into a discrete signal is performed by the FSK module 132, and then the frequency hopping module 134 assigns this waveform to the appropriate frequency. All possible transmission waveforms can be known a priori. There are two possible waveforms corresponding to 1 or 0 for each hopping frequency. All of these waveforms are pre-computed and stored at start-up, significantly reducing the operations required to generate the transmitted waveform. With a Pentium Pro of 180 MHz, it took 2.2 microseconds to generate an IF waveform equivalent to a single bit. This is about 45
This corresponds to a possible transmission data rate of 0 kbs.

To generate the continuous phase waveform, the previously calculated waveform is actually oversampled and the sub-sampling set corresponding to the output sampling rate is copied to the output buffer. Oversampling allows indexing into the buffer to match the phase, the pattern can be treated as a ring buffer, and a waveform can be generated for any bit period. After copying the sample to the output buffer, the phase value is updated and used as an index for the waveform corresponding to the next bit. In a similar manner, the system can maintain a continuous phase during hopping, even if hopping occurs mid-bit.

Reception is essentially an inverse of the transmission system shown in FIG. The receiver detects the presence of a valid transmission, synchronizes to it, and inverts and performs the function of each of the transmission layers. Similar to the above, by combining the parameters of frequency hopping and FSK demodulation, the system can constrain the receiver to look for one of two valid waveforms at a given hopping frequency. Separate functions have been implemented for tracking the hopping sequence and for examining and demodulating the bits. These bits are deframed and then the IP packet is extracted. The driver then passes this packet to the Host IP layer for processing.

Those skilled in the art will be aware of many equivalents to the embodiments and practices described herein, or will be able to ascertain using no more than routine experimentation. For example, it should be appreciated that the systems and methods described herein can be used not only in developing baseband communication systems, but also in developing systems for developing baseband applications. Of course, the system described herein also offers advantages over the prior art, including the ability to select one or more channels from a wideband IF signal and selectively process the channels. .

Therefore, it is to be understood that the invention is not limited to the embodiments disclosed herein, but rather should be construed broadly as permitted by law, and in accordance with the appended claims. Of course.

[Brief description of drawings]

FIG. 1 shows a functional block diagram of a wireless communication system including an application program for processing a modulated signal.

[Fig. 2]   Figure 2 shows a functional block diagram of one of the interface cards as shown in Figure 1.

[Figure 3]   2 is a schematic diagram of data flow between components of the system shown in FIG. 1.

[Figure 4]   3 is another schematic diagram of data flow between components of the system shown in FIG. 1.

5 is yet another schematic diagram of data flow between components of the system shown in FIG. 1. FIG.

FIG. 6 shows as a functional block diagram one embodiment of the process for processing digitized IF signal samples sent to the memory space of a cellular receiver process.

7 illustrates another embodiment of a down converter module that can be used in the cellular receiver process shown in FIG.

FIG. 8 shows the network layer of a network interface card according to the invention.

FIG. 9 shows as a functional block diagram the software components of an application for sending packets of network data.

[Explanation of symbols]

  10 wireless communication system   12 transceiver   14 Converter   16 Host computer platform   18 Persistent storage   20 I / O devices   22 Antenna element   24 preamplifier   28 Wide band filter   30 interfaces   32 CPU   34 Operation system   36 computer memory   38 data memory space   40 memory space for application programs   48 output controller   50 ring buffer   60 interface cards   62 PCI / PCI bridge   64 configuration memory   68 PCI controller component   70 Output page address memory   72 Input page address memory   74 Output data memory   78 Input data memory

─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Tennen House, David El             Massachusetts, United States             20815 Chevy Chase Curty             Su Street 7717 (72) Inventor Gatag, John Sea             Massachusetts, United States             02173 Lexington Emerson Law             Do 273 (72) Inventor Imart, Michael             Massachusetts, United States             02167 Chestnut Hill Hammond             Pond Parkway 327 Apartment             1 F term (reference) 5K034 AA10 AA14 DD01 EE03 EE11                       FF11 HH01 HH02 HH63                 5K061 BB06 JJ06 JJ07

Claims (19)

[Claims] 1. A method of processing a radio signal: converting between a wideband signal and a high sampling rate digital signal; storing the samples of the high sampling rate digital signal directly in a memory accessible by a computer program. And processing the high sampling rate digital signal samples under the control of the computer program. 2. Method according to claim 1, characterized in that the sampling is continuous. 3. The method of claim 1, wherein samples are stored at a rate equal to the sampling rate. 4. The method of claim 1, wherein the wideband signal has a bandwidth of 10 MHz and the sampling rate is at least 20 megasamples / second. 5. The method of claim 1, wherein the processing further comprises modulating a signal into the digitized IF signal. 6. The method of claim 1, wherein processing further comprises demodulating the digitized IF signal into a signal. 7. The method of claim 1, wherein the processing further comprises a channel selection step. 8. In a radio receiver: a converter for digitizing a wideband IF signal; and modulating the digitized IF signal and selecting a channel such that multiple channels are available for multiple processes, said selecting A radio receiver comprising a processor for processing the selected channels. 9. In a radio transmitter: including a processor for modulating a digital signal from a multiplex process into a selected digital wideband IF signal channel; and a converter for converting the digital IF signal into an analog wideband signal. A radio transmitter characterized in that 10. A method of processing a radio signal: converting between a radio frequency signal and its analog intermediate frequency signal in the analog domain; said analog intermediate frequency signal and corresponding digitized intermediate frequency signal data A step of temporarily storing the digitized intermediate frequency signal data in a buffer; a page of the digitized IF signal data arranged in page order between the buffer and a memory for direct memory access; A method for transferring the digitized intermediate frequency signal data by a computer program. 11. A direct memory access method is used to transfer data between a buffer and a system memory space: an application assigns at least one page of random access memory in which the digitized intermediate frequency signal data is stored to the data. Swapping system space to user space for access; swapping at least another page from user space to system space to allow direct memory access transfer for the at least another page; and user space 11. The method of claim 10, further comprising: processing the digitized intermediate frequency signal data in an application. 12. A direct memory access controller maintaining a list of addresses of system space pages available for data transfer; removing page addresses when corresponding data is transferred; and the number of page addresses in the list. 11. If the threshold value is less than a predetermined threshold value, the processor further includes a new page address by interrupting the processor so that the interrupt handler supplies the new page address. Method. 13. A method of providing a direct memory access scheme: maintaining a list of physical page addresses associated with buffers in memory in a direct memory access controller; removing page addresses from the list; Transferring a new page address between the device and a memory corresponding to the page address of the list; and continuously repeating the read and transfer steps. 14. A page address read step, followed by a continuous repeat with the read and transfer step: removing the page address from the list; and when the number of page addresses in the list is less than a predetermined threshold. 14. The method of claim 13, further comprising: providing a new page address by interrupting a processor, so that an interrupt handler supplies the new page address. 15. In a radio: a receiver for converting a signal between a radio frequency and an intermediate frequency; a converter for converting between the intermediate frequency signal and a data stream; random including user space and system space Access memory,
A memory organized into pages in which the system space can be accessed directly by a memory access controller, user space pages can be swapped into system space, and system space pages can be swapped into user space; A radio characterized in that it includes a direct memory access controller for arranging and transferring pages of data between the system space and the system space; and a software application for accessing the user space. 16. A list of addresses of system space pages ready for data transfer, maintained by the DMA controller.
Including: adding a new page address to the list by interrupting the processor when the number of page addresses falls below a predetermined threshold, so that the interrupt handler supplies the new page address. The radio according to claim 15. 17. In a radio: a tuner for converting a radio frequency signal into an intermediate frequency signal; a data processing platform having a processor and a memory; on the data processing platform for demodulating a digital data signal representing the intermediate frequency signal A computer program running on a computer; and a converter for converting the intermediate frequency signal into a digital data signal and storing the digital signal in a portion of the memory that is mapped into a memory space associated with the computer program. Radio characterized by including. 18. An operating system for allocating memory resources to a program running on said date processing platform, and for supplying to said converter an address signal representative of a portion of said memory space associated with said computer program. The radio of claim 1, further comprising: 19. In a temporary connection for coupling disparate communication devices: a data processing platform having a processor and a memory; for demodulating a digital data signal representing an intermediate frequency signal and transmitted according to a first communication protocol. A first computer program for processing the demodulated signal to identify an information signal; and for modulating the information signal and for transmitting the modulated information signal according to a second communication protocol. A second computer program; and, therefore: a communication device adopting the first communication protocol can communicate with a communication device adopting the second communication protocol; a temporary connection.