JPS60213143A - Am stereophonic type automatic deciding circuit - Google Patents

Abstract

PURPOSE:To decide what stereophonic type includes a modulated input signal concerned easily by digitally counting a pilot signal selected out of the demodulated input signal and separating its pulse train into plural kinds to decide the modulated input signals. CONSTITUTION:A pilot signal S0 included in a demodulated input signal Si applied to a terminal 11 is converted into a digital signal S1 by a waveform shaping circuit 13 and applied to an AND circuit 14. The AND circuit 14 opens its gate for a fixed period to apply a pilot signal S1 to a binary counter circuit 15. The counter circuit 15 counts up the inputted pilot signal, holds the pilot signal for a specific period and then outputs it to deciding circuits A, B having different separation accuracy. The deciding circuit A or B separates the pulse train of the pilot signal held for the specific period of decide the pilot signal and outputs the decided result to terminals 01-05 through a latch circuit 20. If the pilot signal is not included in any stereophonic type, a signal is outputted from a monophonic terminal 0M to execute monophonic display.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic AM stereo system determination circuit for determining a plurality of different AM stereo systems.

The AM stereo system is known, but since there are multiple systems, the receiving side must prepare a receiver compatible with each system.

Individual method among multiple methods? For this determination, a method is used to detect the pilot signal So' included in the difference signal (LR) of the demodulator of the receiver.

Each pilot signal S in the mentioned methods.

The frequency f. is °(1) Magnabock 2 method ... 5 (Hz) (
2) Peller force type ... 10 [Hz] (3) Kahn method ... 15 (Hz) (4) Motorola method ... 25 (Hz) (5) ... Liss method ...
55 (Hz) is adopted for each.

Therefore, the receiver requires a determination circuit for determining each method.

FIG. 1 is a block diagram showing the determination circuit in the receiver.
(2) is an input terminal, 2 is a bandpass filter, 3 is a waveform shaping circuit, 4 is a holding circuit, and the pilot signal frequency f is used for the KAU difference signal (L-R) manually input from Hanako 1. is included, so the pilot signal frequency f selected by the bandpass filter 2. is waveform-shaped by the waveform shaping circuit 3 and then applied to the holding circuit 4. The holding circuit 4 is for holding the human input signal for a certain period of time, and has a pilot signal frequency f. 4-r functions to prevent the influence of this on the determination operation when an unstable state occurs where the signal is detected or not detected.

By the way, in a conventional receiver, a determination circuit having the configuration shown in FIG. 1 must be prepared for each method. For this reason, when implementing an IC for the determination circuit, the bandpass filter 2 is particularly important for the component resistor R]~ as shown in Figure 2.
R3, capacitor C].

Since the 02 Y external attachments had to be made into parts, there was a drawback that the number of IC bins increased.

Further, when the selectivity (Q) of the bandpass filter 2 is low, the pilot signal frequency f. There was a risk that the determination circuit would malfunction due to a signal with a frequency close to .

The present invention has been made to address the above problems, and involves digitally processing a pilot signal selected from demodulated human input signals, counting the digital pilot signal over a certain period of time, and converting this pilot signal into a signal over a specified period of time. It is an object of the present invention to provide an AM stereo power type automatic judgment circuit which is configured to hold and separate and judge into a plurality of types according to seven pulse trains, thereby eliminating the conventional problems.

Embodiments of the present invention will be explained below with reference to the drawings.

FIG. 3 is a diagram showing an AM stereo camera type automatic reading circuit according to the present invention, where IJ is an input terminal, 12 is a bandpass filter, 13 is a waveform shaping circuit, 14.18 is an AND circuit, 15 is a single counter circuit, 16 is a frequency divider circuit, 17 is an inverter circuit, 19 is a determination circuit, 20 is a latch circuit, 21 is a NOR circuit, η is one reference signal input terminal, 2
This is a 3-way switching signal input terminal.

The above judgment circuit 19 detects the minute #l! It is composed of two types of circuits A and BK with different precision, and the selection is made by adding terminal B.
This is done by the switching signal S5. Output signals A1-A5 from the determination circuit 19 are applied to a latch circuit section, held for a certain period of time, and then output as output signals O1-05. Here, the output signals 01 to 05 correspond to (11 to (5)) of the five different AM stereo systems described above, 0 is the Hamagna box system judgment output, 02 is the Vera one-way judgment output, and 03 is the Vera one-way judgment output. 04 is the Motorola method determination output, and 05 is the Norris method determination output 7.

If the latch circuit unit does not output any of these different stereo system determination outputs, the NOR circuit 21 outputs an output signal OM indicating a monaural state.

First, the demodulated human input signal Si applied to the terminal 11 has a selected frequency f. The pilot signal S is separated into the Ondo signal and the pilot signal So by the band pass filter 12 of Lr60 [H2]. is selected and added to the waveform shaping circuit 13. The waveform shaping circuit 13 receives the pilot signal S. The signal is then digitally processed and converted into a digital signal. The digitized pilot signal S] is applied to the AND circuit 14 together with the control reference signal S2 applied to the terminal 22K, and the AND circuit 14 is operated for a certain period of time Tg.
(G) Open Y to allow the output signal Sl to pass through and add it to the binary counter circuit 15. The release time Tg of the gate circuit 14 is expressed by the following formula.

Tg ='/ CF・(L+・f2・f3−f4−f5
)QCM) (5ec)...(1) FIG. 4 is a timing chart showing the flow of the above series of signals.

In other words, the gate is opened over a cycle period (H level period) of one cycle period T of the control reference signal S2, and the passed pilot signal S3 is added to the binary counter circuit and output during this period. Pulskamon small (counting) is performed. Subsequently, the count data is held for the next half cycle period. The binary counter circuit 15 is supplied with the control signal S4, which is the reference signal S2 divided by 2 by the frequency dividing circuit 16, together with the pilot signal S3.
The pulse count is performed over the gate open time Tg of the cow cycle period (corresponding to the above period TK).

Pulse counting is first performed by the first element (flip 70 tube, etc.) 15AK comprising a "two-digit" number, and a signal Bes Bl is outputted from its output terminals Q and Q, respectively.

Subsequently, the signals Bo and Bl are frequency-divided by 1/2 by the second element 15B constituting the "two digits" and sent to its output terminal Q.

Signals B15B1 are output from Q respectively. Thereafter, pulse counting is performed by dividing the frequency by "/2" by the subsequent element in the same manner.
The signal Bay B5 is outputted from the output terminals Q and Q respectively.

These output signals BO*BO to B5yB5 counted by the binary counter circuit 15 for a period of 1 g are held for the next half cycle period and are applied to the determination circuit 19.

The determination circuit 19 is configured as shown in FIGS. 5(al) and (b), and receives each output signal BO from the binary counter circuit 15.
eBO'= B5 * B5 Y: Output lines A11 to A! 12 and this output line 11~]2
It includes a plurality of NAND circuits 24A to 24Eg which are appropriately combined to form a human power line. Also, the NAND circuit 24
A-24g one human power line A! 13, the switching signal Ss applied to the terminal B or its inverted signal Ss
is supplied.

In the determination circuit of FIG.
5) Minutes! A determination is made to determine whether or not a pilot signal is included, and if so, which method is used.

The difference in FIG. 5 (act (b)) is a minute 1111/f1 degree difference, (a) is for basic accuracy, and B) is for high accuracy, and the gate opening time Tg is different for each.

FIG. 6 is a table showing the output logic of the binary counter circuit 15 in FIG. 5 (alt (b)).

The determination circuit 19 in FIG. The judgment frequency is set by combining the output signals Bn, B, χ of the digit elements.In the separation accuracy, Tg=0, 2 (sec
), the determination cycle becomes faster, but since the resolution of the binary counter circuit is only 1 bit, there is a risk of malfunction.

In the case of 1g=Lσ(sec), the resolution of the counter circuit can be doubled, so the judgment speed will be slower, but the separation accuracy can be increased, so there is less risk of malfunction.Therefore, manual labor is required. The gate open time Tg and the determination circuit can be selected depending on the signal level.

Frequency f of gate opening time Tg and control base S signal S2
The relationship with c is expressed by the following formula.

fc≦l/(Tg+data judgment time)...(2)
Therefore, by keeping Tg accurate, the data hold time only needs to be as short as possible for data determination, and fc can vary somewhat.

As shown in FIG. 4, the binary counter circuit is cleared during the remaining half cycle period following the half cycle period of the control signal S4. A5 is added to the output signal A1 of the determination circuit 19 to the latch circuit. Since these judgment signals A1 to A5 are output only during the data hold time in FIG. 4, the output data is held by the latch circuit even after the binary counter circuit is reset. The determination signal is rewritten every data hold time, and the current state of logic is maintained as long as the logic of the determination signal does not change.

When any of the blade signals 0□ to 05 is received from the latch circuit, it is possible to automatically select which type of pilot signal VC1!81] by using the above-mentioned procedure.

If there is no demodulated human input signal neutralization pilot signal, there is no output signal from the latch circuit adder, so a signal is output from the NOR circuit 21, thereby making it possible to suppress the fact that it is a monaural signal.

Therefore, depending on the presence or absence of the output signal from the latch circuit, the demodulated signal can be easily determined as a stereo signal or a monaural signal.

As is clear from the above description, according to the present invention, a pilot signal selected from demodulated human input signals is digitally processed, a digital pilot signal Y is counted which is gated for a certain period of time, and this pilot signal is held for a certain period of time. Since it is configured to separate and judge a plurality of food items according to the pulse train, the following advantages can be obtained and the conventional disadvantages can be eliminated.

(11) Judgment of multiple AM stereo systems can be performed using one set of filter circuits and one set of judgment circuits, so it is possible to reduce the number of bins for external components for filters when implementing IC. .

(2) Since the pilot signal is digitally processed, there is no malfunction due to adjacent frequency signals.

(3) Even in the case of automotive use, is there a combination of the frequency of the control reference signal and the NAND circuit in the judgment circuit? By simply changing it, the accuracy of separation judgment can be increased, making it stable against external noise.

(4) Determination as to which type of stereo signal or monaural signal the demodulated human input signal is can be made simply by determining the presence or absence of a single pilot signal, and since the frequency is also monitored, the determination can be made accurately.

(5) Since the signal is judged by digital processing, the FAM of the selection frequency of the bandpass filter is no longer necessary.
The control reference signal must be stabilized even against temperature changes.
This allows the determination accuracy in each mode to remain unchanged.

[Brief explanation of the drawing]

1 and 2 are block diagrams and circuit diagrams showing the conventional example, FIGS. Figure 6 is a timing chart and a logic diagram for explaining the present invention. 12... Band pass filter, 13... Waveform shaping circuit, 14, 18. 24A to 24g... NAND circuit, 1
5, 15A to 15F...Binary counter circuit,
16... Branch circuit, 19° 19A, 19E... Judgment circuit, Addition... Latch circuit, 21... NOR circuit. Figure 1 Figure 6 Procedural Amendment (Music) May 10, 1980 Special Patent Application No. 069484 2 Title of Invention AM Stereo System Automatic Determination Circuit 3 Relationship with the Amendment Person Case Patent Applicant Address name (148) Clarion Co., Ltd. 4 agents 〒1
05 Address: Shiba 3-chome, 2-14 Shiba, Minato-ku, Tokyo Telephone: (03) 455-8746 Claims and details of the invention (1) Claims of the present application The range l is corrected as follows. A low-pass filter for selecting a pilot signal from the RX and A power signals, a waveform shaping circuit for converting the pilot signal into a digital signal, and a gate circuit for passing the digitized pilot signal for a certain period of time. and a binary circuit that counts the digital signals that have passed through the gate circuit and holds the digital signals for a specific time.
An AM stereo system automatic judgment circuit characterized in that it includes a counter circuit, and a judgment circuit for separating and judging the digital signal held for the specified period of time into a plurality of types according to its pulse train. 2. The determination circuit is characterized in that it includes a plurality of NAND circuits having a plurality of output lines from a binary counter circuit and a plurality of input lines configured by appropriately combining the output lines with different contents. An AM stereo system automatic determination circuit according to claim 1. 3. The AM stereo system according to claim 2, wherein each of the 36 NAND circuits in the determination circuit is provided with input lines having different combinations.
Judgment circuit. (21 Amend "Band" to "Low" on page 4, line 1 of the specification of the present application. (3) Amend "Band Jvr Low" on page 6, line 1 of the same document. JO Patent of August 1982 Office Commissioner Manabu Shiga 1 Display of the case 1982 Patent Service No. 069484 3 Person making the amendment Relationship with the case Patent applicant Address Name (148) Clarion Co., Ltd. 4 Agent 〒1
05 Address Corrected to Shiba 3-chome Building, 3-2-14 Shiba, Minato-ku, Tokyo.

Claims (1)

[Claims] 1. A bandpass filter for selecting a pilot signal Y from demodulated input signals, a waveform shaping circuit for converting the pilot signal into a digital signal, and a waveform shaping circuit for converting the pilot signal into a digital signal, and a waveform shaping circuit for converting the pilot signal into a digital signal, and a gate circuit for passing the digital signal; a binary counter circuit for counting the digital signal that has passed through the gate circuit and holding the digital signal for a specific time; An AM stereo system automatic determination circuit characterized by including a determination circuit for separating and determining a plurality of types. Multiple people composed of different content combined as appropriate? 2. The AM stereo system automatic determination circuit according to claim 1, further comprising a plurality of NAND circuits. 3. The AM stereo system automatic determination circuit according to claim 2, wherein each NAND circuit in the above-mentioned publication circuit is provided with a large number of circuits having different combination contents.