JPH05203685A - Input signal detection circuit - Google Patents

Abstract

PURPOSE:To simplify circuit constitution by eliminating the necessity of strictly removing noise components at the front stage of a frequency measuring circuit. CONSTITUTION:A counter circuit 9 measures the frequency of an input signal IN using a reference signal BP and agreement signals which are output from an AND gate 10 when the result of this measurement agrees with a predetermined frequency are counted by a register circuit 12. When the register circuit 12 counts three successive outputs of the agreement signals a judgement signal G is output from the AND gate 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input signal detection circuit for determining that an input signal is proper when the input signal matches a predetermined frequency, and more particularly to an input signal detection circuit formed in a semiconductor integrated circuit. Regarding the circuit.

[0002]

2. Description of the Related Art For example, there is a detection circuit for detecting the presence / absence of an analog signal input, such as a signal detection circuit for detecting a billing signal transmitted from an exchange in a telephone. It is configured in one semiconductor integrated circuit. However, a noise component is likely to be included in a signal input through a public telephone line, such as a billing signal of a telephone, and if such a noise component is left as it is, it becomes impossible to stably detect an accurate input signal. ..
Therefore, the conventional input signal detection circuit is provided with a frequency counter circuit for measuring the frequency of the input signal, and when this frequency counter circuit measures a predetermined frequency, it is determined that an appropriate signal has been input. Generally, an analog signal is converted into a digital pulse and input to this frequency counter circuit, but at the time of this conversion, a zero-cross detector with hysteresis is used, and a filter that removes noise components is built in to make the analog signal accurate. The digital pulse is converted into a digital pulse so that it is not affected by noise components.

[0003]

However, in the conventional input signal detection circuit, the frequency counter circuit for detecting the frequency of the input signal outputs the determination signal by one sampling, and the frequency counter circuit It is necessary to strictly remove noise components when converting an analog signal into a digital pulse in the preceding stage.
It is necessary to form a stable zero-cross detector using an S operational amplifier, and a resistor for providing hysteresis in the zero-cross detector must be provided, which complicates the circuit configuration and increases the pattern area. There was a problem that it was difficult to configure within. this is,
The same applies to the case of configuring a filter circuit.

An object of the present invention is to measure the frequency of an input signal on the basis of a reference signal and continuously perform the measurement result. When the measured frequency matches a predetermined number of times in succession, the input signal is An object of the present invention is to provide an input signal detection circuit which can simplify the circuit configuration and reduce the pattern area in the integrated circuit by determining that the input signal is appropriate.

[0005]

SUMMARY OF THE INVENTION An input signal detection circuit according to the present invention comprises a frequency measuring means for measuring the frequency of an input signal based on a reference signal and a frequency measuring means for measuring the frequency of the input signal when the measured result coincides with a predetermined frequency. The frequency discriminating means for outputting the coincidence signal, the counting means for continuously counting the number of times the coincidence signal is output from the frequency discriminating means, and the input signal when the counting means continuously counts the coincidence signal output by a predetermined number. And a determining unit that determines that the unit is appropriate.

[0006]

According to the present invention, the frequency of the input signal is measured based on the reference signal, and when the measurement result matches the predetermined frequency, the coincidence signal is output from the frequency discriminating means. The coincidence signal output from the frequency determining means is measured by the counting means, and when the counting means continuously measures a predetermined number, the input signal is determined to be proper. Therefore, it is not necessary to strictly remove the noise component from the input to the frequency measuring means, and it is not necessary to provide a zero-cross detector or a filter circuit, and the circuit configuration is simplified.

[0007]

1 is a circuit diagram showing the configuration of an input signal detecting circuit according to an embodiment of the present invention. Further, FIG. 2 is a timing chart of signals of respective parts in the input signal detection circuit. The input signal detection circuit 1 is a circuit that detects an input of an analog signal of 1 KHz, and performs frequency measurement sampling three times continuously. Analog input signal I
N is converted into a digital pulse S1 by the inverter 2 and input to the data terminal of the D flip-flop 3 for delaying one cycle. The flip-flop 3 inverts the positive / negative of the digital pulse S1 and outputs the synchronization signal S2 delayed by one cycle of the system clock SCk. This digital pulse S1 and synchronization signal S2
Is input to the NOR gate 4 and the AND gate 5.

The NOR gate 4 is "H" only when both the digital pulse S1 and the synchronizing signal S2 are "Lo".
Then, the AND gate 5 outputs a count start signal CSt which becomes "i". The AND gate 5 outputs a count stop signal CSp which becomes "Hi" when both the digital pulse S1 and the synchronizing signal S2 are "Hi". The CSt and the stop signal CSp are input to the RS flip-flop 6. The RS flip-flop 6 performs a predetermined operation using the start signal CSt as a set signal and the stop signal CSp as a reset signal. The data is input to the data terminal of the flip-flop 7. The flip-flop 7 outputs a count reset signal CR for controlling the operation of the count circuit described later according to the Q output of the RS flip-flop 6.

The counter circuit 9 is composed of a frequency dividing circuit and divides the frequency of the 10 KHz reference signal BP. The reference signal BP is input to the AND gate 8. The AND gate 8 takes the logical sum of the reference signal BP and the count reset signal CR and inputs it to the counter circuit 9. Therefore, the reference signal BP is input to the counter circuit 9 only when the count reset signal CR is "Hi". The states of the first and third stages of the counter circuit 9 are AN
It is input to the D gate 10. Therefore, when the counter circuit 9 counts five pulses of the reference signal BP, the output C1 of the first stage and the output C3 of the third stage of the counter circuit 9 become "Hi". A reset signal is supplied from the AND gate 11 to the reset terminal of the counter circuit 9.
The AND gate 11 takes the logical sum of an inversion signal of a determination signal G, which will be described later, a count reset signal CR and an all clear signal ACL which sets the circuit state immediately after the activation.

The determination signal G is "Lo" before the determination of the input signal, and the all clear signal ACL is always set to "Hi" after a lapse of a fixed time from the start. Therefore, AND
The gate 11 operates when the counter reset signal CR is "Hi" before the determination of the input signal.

The output C1 of the first stage and the output C3 of the third stage of the counter circuit 9 are both input to the AND gate 10. The AND gate 10 takes the logical sum of these outputs C1 and C3 and inputs it to the register circuit 12. Therefore, the register circuit 12 outputs "Hi" when the counter circuit 9 counts 5 based on the frequency of the reference signal BP during the operation of the counter circuit 9 in which the count reset signal CR is "Hi". A signal is input. The register circuit 12 is composed of three stages of registers that store the detection state of the counter circuit 9. The outputs B1 to B3 of each register are logically ORed in the AND gate 13 and output as the determination signal G. Therefore, when the count value of the counter circuit 9 becomes "3", all the outputs B1 to B3 of the register become "Hi", and the judgment output G which is the output of the AND gate 13 becomes "Hi".

The register 12 and the flip-flop 3 output a decision signal G and then a release signal AR.
Is input, and the operation is stopped when the release signal AR is "Hi". Further, when the determination signal G becomes "Hi", the output of the AND gate 11 becomes "Lo", the contents of the counter circuit 9 are reset, and the operation is stopped.

As described above, in this embodiment,
The frequency of the count reset signal CR synchronized with the digital pulse S1 of the input signal IN is set to the reference signal B of 10 KHz.
The number of times of output of the coincidence signal (equal to the output C3 of the third stage of the counter 9) output from the AND gate 10 when the measurement result coincides with the proper input signal frequency using P Can be continuously counted in the register circuit 12, and the judgment signal G can be output from the AND gate 13 when the number of output of the coincidence signal becomes “3”.

The count value of the number of times the match signal is output from the register 12 is not limited to "3".

[0015]

According to the present invention, it is possible to judge whether or not an input signal is proper by continuously sampling a predetermined frequency a plurality of times. There is an advantage that it is not necessary to strictly remove an input noise component, and a complicated circuit configuration can be eliminated to reduce a pattern area.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an input signal detection circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart of signals in each unit of the input signal detection circuit.

[Explanation of symbols]

 1-input signal detection circuit 9-counter circuit (frequency measuring means) 12-register circuit (counting means) 13-AND gate (determination means)

Claims (1)

[Claims] 1. A frequency measuring means for measuring a frequency of an input signal based on a reference signal, a frequency discriminating means for outputting a coincidence signal when a measurement result of the frequency measuring means coincides with a predetermined frequency, and a frequency discriminating means. And a determining means for continuously counting the number of times the coincidence signal is output from the device, and a determining means for determining that the input signal is proper when the counting means continuously counts the outputs of the coincidence signal by a predetermined number. An input signal detection circuit characterized by the above.