JPS6313503Y2 - - Google Patents

Description

[Detailed Description of the Invention] Technical Field The present invention relates to a period measuring circuit, and more particularly to a period measuring circuit for independently measuring the periods of various input signals.

BACKGROUND ART A period measuring circuit measures a physical quantity such as rotational speed by measuring the period of an input signal. For example, in the electronic control system of a car, the rotational speed of the wheel is calculated by measuring the period of the rotation pulse signal emitted from the sensor that detects the rotation of the wheel, and the ignition pulse period of the engine is also calculated. The rotational speed is thereby calculated, and various controls are performed based on these calculated values. As described above, cycle measurement circuits have become indispensable in electronic control systems for automobiles.Especially in recent years, electronic control has become more complex and the rotation of the front and rear wheels can be detected to lock the wheels during brake operation. With the introduction of antiskid devices to prevent skidding, the number of signals that require period measurement is also increasing.

FIG. 1 is a circuit diagram showing an example of a period measuring circuit using a microprocessor commonly used in the past, in which a counter 1 is connected to a clock oscillation circuit 2.
The reference clock pulse CP supplied from the circuit 3 is sequentially counted, and the count value is reset each time an input signal IN delayed to some extent is supplied via the delay circuit 3. Therefore, this counter 1 receives the input signal
This means that the number of clock pulses CP during each period of IN is counted, and the counted value is held in the latch circuit 4 which uses the input signal IN as a latch control input immediately before being reset.

On the other hand, the microprocessor 5, which uses the input signal IN as an interrupt signal, takes in the output value of the latch circuit 4 supplied via the data bus DB every time the input signal IN is supplied, and uses that data as the reference clock pulse CP. The period of the input signal is determined and sent by performing arithmetic processing to multiply the period of the input signal. By repeating this process every time the input signal IN is supplied, the input signal
Each cycle of IN can be measured sequentially.

However, the period measuring circuit with the above configuration cannot perform period measurements on a wide variety of input signals, and is therefore unsuitable for use in electronic control circuits of automobiles, for example, where there are many types of signals that require period measurement. It is.

On the other hand, a counter that is cleared by the input signal and counts the reference clock signal for each type of input signal, and a latch circuit that holds the count value immediately before each counter is reset are provided. It is also possible to put the microprocessor into an interrupt state using the OR signal of each input signal and have it take in the output value of each latch circuit, but the microprocessor can only accept the next interrupt signal after receiving the interrupt signal. A re-interrupt time T ₁ is required until this happens. That is, when the microprocessor receives an interrupt signal, it takes in the data and processes it, then returns to the original routine and becomes ready to receive the next interrupt signal. Therefore, if a plurality of input signals are supplied at intervals of less than time _T1 , there is a problem that the output value of the latch circuit cannot be taken into the microprocessor.

DISCLOSURE OF THE INVENTION Accordingly, an object of the present invention is to provide a period measuring circuit that can measure the periods of various input signals generated close to each other in time.

In order to achieve such an objective, the present invention calculates the logical sum of various input signals, and if this logical sum signal is close to the re-interrupt period _T1 of the microprocessor, the predetermined A synthesized input signal for multiple input signals is created by delaying both signals over a period T ₂ for a re-interrupt period T ₁ or more, and a reference signal generated between each period of this synthesized input signal is processed. Each time the synthesized input signal is supplied to the microprocessor as an interrupt signal, the count value of the clock pulse is sequentially taken in, and the microprocessor determines the type of input signal to which the interrupt signal belongs and determines whether there is a delay. At the same time, determine the count value of the reference clock pulse between the generation of the interrupt signal in response to the same type of input signal,
Further, the measurement value of the period for each input signal is calculated and outputted by making corrections based on the presence or absence of delay processing over the period _T2 .

In the period measurement circuit configured in this way, it is possible to measure the periods of multiple types of input signals, so there is no need to provide a measurement circuit for each input signal as in the past. The cost when measuring the periods of multiple types of input signals is significantly reduced. In addition, since the same circuit is used to measure the periods for a plurality of types of input signals, it has various excellent effects, such as simplifying the circuit and making it suitable for downsizing the device.

BEST MODE FOR CARRYING OUT THE INVENTION The period measuring circuit according to the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a circuit diagram showing an embodiment of the period measuring circuit according to the present invention, and the same parts as in FIG. 1 are indicated using the same symbols. In the figure, numeral 6 is an AND gate that receives two types of negative logic input signals A and B, and outputs a logical sum signal C for the input signals. Reference numeral 7 denotes a first monomultivibrator circuit, which is triggered by the trailing edge of the output signal generated from the AND gate 6 and generates a pulse having a time width of the re-interrupt period _T1 of the microprocessor 5. When the first mono-multivibrator circuit 7 is triggered again during its operation, it is of a trigger type that continues to generate an output for a period _T1 from this point onwards. 8
9 is a first gate circuit that receives the output signal C of the AND gate 6 and the set output signal _Q1 of the first mono-multivibrator 7 and generates the output signal D, for example, an OR gate; A third gate circuit receives the reset output signal ₁ of the vibrator circuit 7, for example, an OR gate; 10 is a second monomultivibrator circuit triggered by the output signal E of the OR gate 9; An output signal F having a time width T ₂ that is sufficiently short with respect to the period is generated. Reference numeral 11 denotes a trailing edge differentiator circuit, which receives a set output signal Q ₂ supplied from the second monomultivibrator circuit 10.
By differentiating the trailing edge of G
occurs. 12 is a first gate circuit; for example, a second gate circuit receives the output signal D of the OR gate 8 and the output signal G of the trailing edge differentiating circuit 11 and generates a composite input signal H;
The gate circuit is, for example, an OR gate, and its composite input signal H is supplied to the input terminal of the delay circuit 3, the latch control input terminal L of the latch circuit 4, and the interrupt terminal of the microprocessor 5, respectively. 13 is a trailing edge delay circuit that receives the set output signal _Q2 of the second mono multivibrator circuit 10, and delays the trailing edge of the input signal by a predetermined time and then outputs the input port of the microprocessor 5. Supply P ₁ . Input signals A and B are supplied to the microprocessor 5 at its input ports P ₁₀ and P ₂₀ .

In the period measuring circuit configured in this way,
When input signals A (A ₁ to _{A 3} ) and input signals B (B ₁ to _{B 3} ) shown in FIG.
As shown in FIG. 3c, the logical sum of both signals is sent out as an output signal C. Output signal C
When is generated, the first mono-multivibrator circuit 7 is triggered by the rising edge.
The set output signal _Q1 is sent out in the form of a pulse with a duration _T1 each time it is triggered, as shown in FIG. 3d. However, input signals A and B are
As shown by A ₂ , B ₂ and B ₃ , A ₃ in Figures a and b, if they occur close to each other within time T ₁ , the third
The triggered output signals are as shown in FIG. d between times t ₁ and t ₂ and between times t ₃ and t ₄ , respectively. The set output signal _Q1 of the first mono-multivibrator circuit 7 is logically summed with the output signal C of the AND gate 6 in the OR gate 8, so that it is connected to the AND gate as shown in FIG. 3e. An output signal D is generated from which the signals corresponding to the input signals B ₂ and A ₃ which are supplied within time T ₁ from the output signal C of 6 are removed.

On the other hand, the OR gate 9 inputs the reset output signal ₁ of the first mono multivibrator circuit 7 and the output signal C of the AND gate 6 shown in _FIG . Input signals B ₂ , A ₃ provided in close proximity
Only the signal corresponding to is extracted and sent as the output signal E as shown in FIG. 3g. This output signal E then triggers the second mono multivibrator circuit 10 at its trailing edge, thereby
Input signals B ₂ and A ₃ that are generated sufficiently short and close to the period of input signals A and B are expressed as time T ₁
A third output signal F of a predetermined constant value having a time width _T2 sufficient to separate the
Generate as shown in Figure h. The output signal F generated in this manner is differentiated in the trailing edge differentiator 11, thereby producing an output signal delayed from the output signal E by a time _T2 , as shown in FIG. 3i. G is generated. Then, this output signal G is combined with the output signal D of the OR gate 8 in a second gate circuit, for example, the OR gate 12, thereby outputting a combined input signal H shown in FIG. 3J. In this case, the composite input signal H is the input signals A ₁ , B ₁ , A ₂ , B ₃ supplied at intervals exceeding time T ₁ are combined as they are, and the input signals supplied closely within time T ₁ are combined as they are. B ₂ and A ₃ are synthesized after being delayed for a certain period of time T ₂ so that the time T ₁
(re-interrupt time). Therefore, when this composite input signal H is used as an interrupt signal, the microprocessor 5 executes the interrupt operation each time to capture data. That is, when the composite input signal H is supplied to the clear terminal CL of the counter 1 via the delay circuit 3, the counter 1 sequentially counts the reference clock pulses CP generated during each cycle of the composite input signal H. latch circuit 4 which outputs the synthesized input signal H as a latch control signal.
sequentially latches and outputs the counted values of counter 1 immediately before being reset. Each time the composite input signal H is supplied to the interrupt signal input terminal, the microprocessor 5 enters the interrupt mode and outputs the output signal of the latch circuit 4, that is, the third
A ₁ , B ₁ , A ₂ , B ₂ ', of the composite input signal H shown in Figure j.
The count values of counter 1, which counts the reference clock pulses CP generated between B ₃ and A ₃ ', are taken in.

On the other hand, the trailing edge delay circuit 13 receives the output signal F generated from the second monomultivibrator circuit 10.
By delaying the trailing edge and outputting it, a delay discrimination signal I indicating that the composite input signals B ₂ ′ and A ₃ ′ generated at that point have been delayed for a certain period of time T ₂ is obtained. It is supplied to the input port _P1 of the microprocessor 5.

Next, the operation of the microprocessor 5 is shown in Figure 4.
This will be explained using the flowchart shown in FIG.
First, when the composite input signal H is generated, the microprocessor 1 starts operating in interrupt mode and moves to step _S1 shown in _FIG . It is determined whether or not. Here, if the determination in step _S1 is YES, the process moves to step _S2 and it is recognized that input signal B is being supplied. Also, if the determination in step S ₁ is NO, the process moves to step S ₃ and the input port
Determine whether a signal is supplied to _P20 .
If the result of this determination is YES, the process proceeds to step _S4 , where it is recognized that input signal A is being supplied, and if the result of this determination is no, the process proceeds to step _S5 . Recognize that input signals A and B are supplied simultaneously. The above is the operation for determining the supply status of input signals A and B.

Next, the operation of calculating the period of the input signal will be explained using the flowchart shown in FIG. When the cycle calculation operation is started, it is determined in step _S6 whether or not the delay determination signal I is supplied to the input port _P1 . If the result of this determination is no, the process moves to step _S7 , where the state of the flag INTE indicating the signal at input port _P1 at the time of the previous count value acquisition is determined, and if the result of this determination is no, the process proceeds to step S7. If so, in step _S8 , the count value N of the counter 1 held in the latch circuit 4 is set as the count value _N0 for the true period, and the period is calculated based on the reference clock pulse CP. In addition, if the determination in step _S7 is YES, the process moves to step _S9 and the count value N is set for a certain period of time.
Count value of reference clock pulse CP corresponding to T ₂
The period is calculated by using the value obtained by adding N _T2 as the count value N for the direct period. In other words, if the flag INTF is "1", the previous combined input signal H
is delayed by a certain period of time T ₂ . Therefore, the true period in this case is the delay time
The period is shortened by T ₂ , and in step S ₉ this count value N ₀ is corrected to obtain the period. And the steps
By moving to _S10 and returning the flag INTF to "0", it is set to indicate that the current combined input signal H is periodic to the input signal when calculating the next true period.

On the other hand, if the determination in step _S6 is YES, the current combined input signal H is
In step _S11 , the count value N is delayed for a certain period of time to indicate that it has been delayed for _T2 .
The period is calculated by taking in the value obtained by subtracting the count value N _T2 corresponding to T ₂ as the count value N ₀ for the true period. When this processing is completed, the process moves to step _S12 and the flag INTF is set to "1".
is set to indicate that an addition of N _T2 is required when calculating the next cycle.

By sequentially performing these operations, 2
Respective period measurements for different input signals will be determined even if both signals are in close proximity.

In the above embodiment, only the case where two types of input signals are handled has been described, but the present invention is not limited to this, and can similarly be applied to period measurement for two or more types of input signals. It can be done. However, in this case, an input port is used to capture the input signal in order to determine the type of input signal being supplied when the interrupt signal is supplied.
It becomes necessary to increase P ₁₀ and P ₂₀ as the number of types increases.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a conventional period measuring circuit, FIG. 2 is a circuit diagram showing an embodiment of the period measuring circuit according to the present invention, and FIGS. 3 a to 3 j are parts of the circuit shown in FIG. Operation waveform diagrams, FIGS. 4 and 5 are flowcharts showing the operation of the circuit shown in FIG. 2. 1...Counter, 2...Clock oscillation circuit, 3
...Delay circuit, 4...Latch circuit, 5...Microprocessor, 6...And gate, 7,
10...First and second mono multivibrator circuits, 8...First gate circuit (OR gate), 9...
...Third gate circuit (OR gate), 12...Second
Gate circuit (OR gate), 11... trailing edge differential circuit, 13... trailing edge delay circuit.

Claims (1)

[Scope of utility model registration request] A retrigger type first mono multivibrator circuit that generates a pulse with a time width T ₁ triggered by the trailing edge of various input signals whose period is to be measured, and an output generation period of this first mono multivibrator circuit. a first gate circuit that takes out the input signal supplied at a time other than the first gate circuit;
a third gate circuit that takes out the input signal supplied during the output generation period of the mono-multivibrator circuit; and a second gate circuit that is triggered by the output signal of the third gate circuit and generates a pulse with a predetermined time width _T2 . a mono multivibrator circuit, and a second gate circuit for calculating the logical sum of the pulse signal generated in synchronization with the trailing edge of the output signal generated from the second mono multivibrator circuit and the output signal of the first gate circuit. a counter that counts reference clock pulses using a signal obtained by slightly delaying the output signal of the second gate circuit as a clear signal;
a latch circuit that latches the counted value of the counter when the output signal of the gate circuit is generated;
a trailing edge delay circuit that delays the trailing edge of the output signal generated from the mono-multivibrator circuit to generate a delayed discrimination signal; and an output signal of the latch circuit that is set in interrupt mode by the output signal of the second gate circuit; a microprocessor that takes in the delay discrimination signal and each of the input signals, the time width T ₁ is longer than the re-interrupt time of the microprocessor, and the time T ₂ is longer than the period of each input signal. The microprocessor is set to a time sufficient to separate input signals that are supplied in short and close proximity to each other for a time exceeding the time _T1 , and the microprocessor is configured to be able to determine the type of input signal in the interrupt mode. The count value between the input signals of the same type is calculated, and after the count value is modified according to the time width _T2 depending on the presence or absence of the delay discrimination signal, the period is calculated based on the reference clock pulse. A period measurement circuit characterized by calculating and outputting.