JPS5982871U - Period measurement circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing an example of a conventional period measurement circuit;
The figure is a circuit diagram showing one embodiment of the period measuring circuit according to the present invention, and FIGS. 3 a to 3 are operational waveform diagrams of each part of the circuit shown in FIG.
4 and 5 are flowcharts showing the operation of the circuit shown in FIG. 2. 1...Counter, 2...Clock oscillation circuit, 3...
・Delay circuit, 4... Latch, circuit, 5... Microprocessor-16... AND gate, 7.10.
...1st, 2nd. Mono multivibrator circuit, 8,9
．． 12...OR gate, 11... Trailing edge differential circuit, 1
3... Trailing edge delay circuit. Figure 2 - Figure 3 5 1 111-1,1

Claims (1)

[Scope of utility model registration request] Except for the output generation period of the retrigger type first mono-multivibrator circuit that generates a pulse with a time width T□ triggered by the trailing edge of the various input signals whose period is to be measured, and the first mono-multivibrator circuit. a first gate circuit that takes out the input signal that is supplied at the time of , a second gate circuit that takes out the input signal that is supplied during the output generation period of the first monomultibibreak circuit, and this second gate circuit. a second mono multivibrator circuit that is triggered by the output signal of and generates a pulse with a predetermined time width T2; and a second mono multivibrator circuit that is triggered by the output signal of a second gate circuit that calculates the logical sum of the pulse signal and the output signal of the first gate circuit; a counter that counts reference clock pulses using a signal obtained by somewhat delaying the output signal of the second gate circuit as a clear signal; a latch circuit that latches the counted value of the counter when the output signal of the second gate circuit is generated; and a latch circuit that delays the trailing edge of the output signal generated from the second mono-multivibrator circuit to generate a delayed discrimination signal; an edge delay circuit; and a microprocessor which enters an interwoven mode by the output signal of the second gate circuit and takes in the output signal of the latch circuit, the delay discrimination signal, and each of the input signals, and □ is equal to or longer than the re-interconnected time of the microprocessor, and the time T2 is sufficiently shorter than the period of each input signal and sufficient to separate input signals that are supplied in close proximity for a time exceeding the time T□. The microprocessor determines the type of the input signal at the included key time, calculates the count value between the input signals of the same type, and uses this count value as the presence/absence of the delay discrimination signal. A period measuring circuit characterized in that the period is calculated and outputted based on the reference clock pulse after correction according to the time width T2.