JPS6161633B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a wheel rotation speed calculation circuit, and more particularly to a wheel rotation speed calculation circuit that is most suitable for application to anti-skid control of a vehicle.

Recently, various anti-skid control devices have been developed as braking devices to provide more effective and safe braking to automobiles on any road surface. In each of these anti-skid control devices, the rotational state or skid state of the wheel is calculated, and the brake fluid pressure transmitted to the wheel cylinder of the wheel brake device is controlled according to this result. Alternatively, in calculating the skid state, the wheel rotation speed, that is, the wheel speed is required. For example, in calculating the rotational state, deceleration is calculated from the wheel speed, and in calculating the skid state, an approximate vehicle speed is calculated from the wheel speed, and the slip rate is calculated from these results. The wheel deceleration is compared to a predetermined deceleration reference value, the wheel slip rate is compared to a predetermined slip rate, and
The brake fluid pressure is controlled based on these results, but the basis of control is the wheel speed in any case.

Recent anti-skid control tends to be digitally controlled, but in order to obtain the wheel speed mentioned above, the output from the wheel rotation speed sensor installed on the wheel is converted into a pulse train, and the wheel speed is calculated based on this pulse train. . In other words, the frequency of this pulse train is proportional to the wheel rotation speed, but conventionally, the pulses of this pulse train during a certain period of time are counted, or high-frequency pulses are calculated between the pulses of the pulse train, that is, the wheel rotation at that time. The wheel speed was calculated by counting at a period inversely proportional to the speed.

However, in the former method, in order to increase the accuracy of the wheel speed, the above-mentioned fixed time must be made considerably longer, and the calculation requires a long time. Furthermore, in the latter method, the calculation accuracy differs greatly depending on whether the wheel speed is high or low.

Furthermore, both of the above methods required complex circuitry to obtain differential manipulation of the wheel speed, ie, wheel deceleration or acceleration.

The present invention has been made in view of the above-mentioned points, and it is an object of the present invention to provide a wheel rotational speed calculation circuit that calculates wheel speed almost instantaneously and that allows differentiation operation to be performed very easily. This purpose, according to the invention, consists of a first divider that counts a constant high-frequency signal and generates one pulse each time this count value equals a constant digital value; a wheel speed signal generator that generates a wheel speed signal with a frequency proportional to the wheel speed signal; a computing unit that calculates and outputs a digital value corresponding to the wheel rotation speed based on the wheel speed signal of the wheel speed signal generator; a first counter that continuously counts the pulses generated by the first divider within a period related to the cycle of the wheel speed signal; received,
a second divider that counts the high frequency signal and generates one pulse each time the counted value becomes equal to the output of the first counter; and a pulse generated by the second divider. a second counter that continuously counts the period or period of the wheel speed signal within a period or period subsequent to the period or period, and supplies this counted value to the arithmetic unit as a signal based on the wheel speed signal. A wheel rotation speed, characterized in that when the count value of the second counter is not equal to the certain digital value, the output of the arithmetic unit is corrected by an amount corresponding to this difference. This is achieved by an arithmetic circuit.

Hereinafter, details of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a wheel rotation speed calculation circuit for anti-skid control of an automobile, which is an embodiment of the present invention. In the figure, 1 is an n-bit first divider, and its CLK terminal has a A high frequency pulse fo as shown in FIG. 2A is supplied. Furthermore, a digital setting device 1a that generates a constant digital value N is connected to the preset input terminals P ₁ , P ₂ , ..., _Po , and an inverter 1b is connected to the PE terminal.
This input terminal has a power supply ON as shown in Figure 2 F.
At times, a pulse in the negative direction is instantaneously generated, and thereafter a signal of "1" is supplied. When the power is turned on, a certain digital value N is set to the first value by the digital setting device 1a.
is preset to divider 1 of . The divider 1 counts high frequency pulses fo, and every time this count value becomes equal to the preset digital value N, it divides by 1.
Generates two pulses from the output terminal OUT. That is, the first divider 1 generates a pulse train having a frequency obtained by dividing the high frequency o of the pulse fo by a preset digital value. This pulse train is supplied to the CLK terminal of the n-bit first counter 2. The R terminal of this counter 2 is supplied with a reset wheel speed pulse R as shown in FIG. 2E. The first counter 2 counts the pulse train of the first divider 1 and is cleared by the wheel speed pulse R. Output terminal O ₁ of first counter 2,
A count value is output from O ₂ , . . . O _o and is supplied to a D-latch type latch circuit 3. This latch circuit 3 has n bits like the first counter 2, and the output terminal of the first counter 3
O ₁ , O ₂ ,...O _o are the input terminals D ₁ ,
D ₂ , ... are connected to D _o . A latching wheel speed pulse RI as shown in FIG. 2D is supplied to the L terminal. That is, this pulse RI is supplied. That is, when this pulse RI is received, the output of the first counter 2 is latched.

Output terminals Q ₁ , Q ₂ , . . . Q _o of the latch circuit 3 are connected to a microcomputer 4. In this embodiment, the microcomputer 4 functions as a wheel rotational speed calculation circuit, and has a comparison function, a memory function, a calculation function, and the like. A certain digital value N is stored in this microcomputer 4, and a digital input related to the wheel speed pulse described later is supplied, this digital input is compared with the above-mentioned certain digital value, and based on this comparison, the current A digital value M corresponding to the wheel rotation speed is calculated and output. The output of the latch circuit 3 is output from the microcomputer 4 at a predetermined timing with the same value.
The input terminals P ₁ , P ₂ ,...P of the second divider 5 of the bits
_o and preset. It is assumed that the timing of this brisset is performed by supplying a timing pulse related to the timing of the operation of the microcomputer 4 to its control terminal (not shown). The timing pulses may be, for example, the reset or latch wheel speed pulses described above.

The above-mentioned high frequency pulse fo is supplied to the CLK terminal of the second divider 5 and counted. One pulse is generated from the OUT terminal each time this count value becomes significant due to brisset or the like. That is, the second divider 5 generates a pulse train having a frequency obtained by dividing the high frequency pulse frequency o by the preset value.

The pulse train from the second divider 5 is supplied to the CLK terminal of a second m-bit counter 6. A reset wheel speed pulse R is supplied to the R terminal of the counter 6. The counter 6 counts the pulses of the second divider 5 and its count value is cleared by the wheel speed pulse R. _The output terminals O ₁ , _{O 2 , .} pulse RI
is supplied. This pulse RI causes the output of the second counter 6 to be latched in the latch circuit 7. The output terminals Q ₁ , Q ₂ , . . . Q _n are connected to the microcomputer 4, where the output of the latch circuit 7 is compared with the constant digital value N mentioned above.

Next, the generation circuit for wheel speed pulses R and RI will be explained. This generation circuit includes a wheel speed sensor 8, a waveform shaping circuit 9, and a D flip-flop 10,1.
1 and 14 and NAND elements 12 and 13. The wheel speed sensor 8 is attached to a wheel of a car and generates a signal in the form of a sine wave with a frequency proportional to the rotational speed of the wheel. This signal is the waveform shaping circuit 9
The waveform is shaped here and shown in Figure 2B.
A rectangular wave fi as shown in is obtained from the waveform shaping circuit 9. This square wave fi is a D flip-flop 10
is supplied to the D terminal of On the other hand, the above-mentioned high frequency pulse fo is supplied to the C terminal, and this pulse fo
As shown in FIG. 2A, the Q output of the flip-flop ₁₀ becomes "1" with the rise of pulse a1, and becomes "0" with the rise of pulse _a4 .
becomes. In other words, as shown in Figure 2C, a pulse whose rising and falling edges are synchronized with the pulse fo.
fi is obtained from the Q terminal of flip-flop 10. In this way, the pulse fi obtained by synchronizing the pulse fi with the clock pulse fo is supplied to the D terminal of the next D flip-flop 11, and is also supplied to one input terminal of the NAND element 12. be done.

This flip-flop 11 is also supplied with the clock pulse fo, and the flip-flop 10 in the previous stage receives pulse a ₁ of the clock pulse fo.
A pulse fi' is obtained from the Q terminal triggered by the rising edge of the pulse fi', but since the rising edge of the pulse fi' lags behind the rising edge of the pulse _a1 by about nanoseconds, the flip-flop 11 The rising edge of pulse fi' is not read by the rising edge of pulse ₁ , but is read by the rising edge of the next pulse _a2 . Therefore, the output of flip-flop 11 is "1" at the rising edge of clock pulse _a1 and becomes "0" at the rising edge of the next clock pulse _a2 . Flip flop 1 like this
1 is supplied to the other input terminal of NAND element 12, so at the rising edge of clock pulse _a1 , the output of NAND element 12 becomes "0".
and becomes "1" at the rising edge of clock pulse _a2 . That is, the pulse shown in FIG.
A pulse obtained by inverting RI is obtained from the NAND element 12. The output of this NAND element 12 is the other one.
A power supply is supplied to one input terminal of the NAND element 13, and a power supply as shown in FIG. 2F is supplied to the other input terminal.
When turned on, a pulse in the negative direction is instantaneously generated, and thereafter a signal of “1” is supplied, so in the end,
From the NAND element 13, an output obtained by inverting the output of the NAND element 12, that is, a wheel speed pulse RI shown in FIG. 2D is obtained. As mentioned above, this pulse RI is used as a latch pulse for the L of the latch circuits 3 and 7.
Supplied to the terminal.

The output of the NAND element 13, ie, the pulse RI, is supplied to the D terminal of the third D flip-flop 14. On the other hand, high frequency pulse fo is supplied to the C terminal. As mentioned above, the output of the flip-flop 11 becomes "0" due to the rise of pulse a ₂ during this pulse fo, but since it becomes "0" with a delay of about nanoseconds, the output of pulse a ₂ becomes "0". At the time of rising, the output of NAND element 13 is still “1”
Therefore, with the rise of the pulse _a2 , the Q output of the flip-flop 14 becomes "1", and with the rise of the next pulse _a2 , the NAND element 13 becomes "0" with a delay of about nanoseconds. When reading the output of , its Q output becomes "0". In this way, a reset wheel speed pulse R as shown in FIG. 2E is obtained from the Q terminal of flip-flop 14. This pulse R is supplied to the first counter 1 and the second counter 6 as described above.
The wheel speed pulses RI and R are obtained in the above manner, and it is clear that these frequencies are proportional to the rotational speed of the wheels and are equal to each other.

The wheel rotation speed calculation circuit according to the embodiment of the present invention is constructed as described above, and its operation will be explained next.

Assume that the car is now traveling at a constant speed. That is, the wheel rotation speed is at a constant value V,
It is assumed that the digital output of the microcomputer 4 is at a constant value M. The value of M is proportional to the wheel rotation speed, and this proportionality constant is determined depending on the required measurement accuracy. At this time, each circuit 2, 3, 5, 6, and 7 generates a constant signal, while the first counter 1 always generates a pulse train of a constant frequency o/N. This pulse train is fed to a first counter 2 and counted continuously within each period of the wheel speed pulse R.
Now, since the wheel rotation speed is constant, the frequency i (or fi') of the pulse R is constant. Therefore, within each period of the pulse R, the first counter 2 calculates fo/Nf
Count i number of pulses.

On the other hand, as shown in FIG. 2D and E, the latch circuit 3 is supplied with the latch wheel speed pulse RI that was generated earlier by a time corresponding to the period of the clock pulse fo. The digital output fo/Nfi of counter 2 of 1 is latched.

Note that this latch circuit 4 is of the D latch type, so
When the pulse RI is supplied, the digital output of the first counter 2 at this time is latched in place of the previous latched content (the latched content remains unchanged since it is in a steady state).

The output fo/Nfi of the latch circuit 3 is supplied to a microcomputer 4, from which it is preset to a first divider 5 at a predetermined timing (pulses R or RI may be used for this purpose). This divider 5
counts high-frequency pulses fo and generates one pulse each time the count value becomes equal to fo/Nfi. That is, the first divider 5 generates a pulse train with a frequency of Nfi. This pulse train is fed to a second counter 6 and counted continuously within each period of the pulse R. Now, since the frequency fi of the pulse R is constant, N pulses are counted within each period. This count value N is determined by the latch circuit 7 by the latch wheel speed pulse RI.
is latched to. Since this latch circuit 7 is also of the D-latch type, when the pulse RI is supplied, the digital output of the second counter 6 at this time is latched instead of the latched contents of the previous cycle (in the steady state). (The latch contents remain unchanged).

The output N of the latch circuit 7 is supplied to the microcomputer 4 and compared with a constant digital value N stored therein, but since they are the same, the digital output M of the microcomputer 4 is not modified; Well, it keeps a constant value.

Now, let the above constant speed be the assumed minimum speed Vmin,
A case will be explained in which the car is accelerated from this state by pressing the accelerator.

As the wheel rotation speed increases, the wheel speed pulse R,
The frequency of RI increases, and its period shortens inversely. In other words, assume that the frequency, which was fi in the above-mentioned steady state, increases by Δfi in the R or RI pulse period immediately after the accelerator is pressed and several cycles after the accelerator is pressed again. Then, the second
The count value of counter 6 is from N to Nfi/fi+Δ
decreases to fi. This digital value Nfi/fi+Δfi is latched in the latch circuit 7 by the next latching wheel speed pulse RI, and the contents of this latch circuit 7 are supplied to the microcomputer 4. In the computer 4, it is compared with a constant digital value N.
Now, if the count value of the second counter 6 reaches N-1 due to the change in Δfi, the following relationship holds true.

Nfmin/fmin+Δfi=N-1 (1) Here, fi is set according to the set minimum speed Vmin.
Let it be fmin. From the above equation (1), Δfi=fmin/N-1 (2) is obtained.

Since the wheel rotation speed V is proportional to the frequency fi of the wheel speed pulse R or RI, the above equation (2) can be rewritten as ΔV=Vmin/N−1 (2) (However, ΔV is the wheel rotation speed relative to the change in Δfi. amount of change in rotational speed).

Therefore, the count value of the second counter 6 is 1.
If the value is decreased by .DELTA.V, a digital value 1 with a weight of .DELTA.V is added to the wheel rotation speed calculation circuit in the microcomputer 4, and this output becomes M+1.

If the frequency of the wheel speed pulse, that is, the wheel rotation speed further changes by an equal amount Δfi from this state, the count value of the second counter 6 at this time is N(fmin+Δfi)/fmin+Δfi+Δfi
=N(fmin+Δfi)/fmin+2Δfi, but if we substitute the relationship in equation (2) above into this equation, we get (However, it is assumed that N is sufficiently larger than 1).

That is, the count value of the second counter 6 decreases by 1 when the wheel rotational speed changes by an equal amount Δfi, that is, by ΔV. As a result, a digital value 1 having the same weight of ΔV is further added to the wheel rotational speed calculation circuit in the microcomputer 4, and the microcomputer 4 outputs a digital value of (M+2).

Also, from the initial state, nΔfi (where n is an integer)
If the frequency of the wheel speed pulse changes by
The count value of the second counter 6 at this time is Nfmin/fmin+nΔfi, but if we substitute the relationship in equation (2) above into this equation, we get (However, N is sufficiently larger than 1 and n).

That is, if the frequency of the wheel speed pulse changes by nΔfi, the count value of the second counter 6 decreases by n. As a result, the digital value n is added to the wheel rotational speed calculation circuit in the microcomputer 4, and the microcomputer 4 outputs a digital value (M+n).

The relationships in equations (3) and (4) above hold regardless of the magnitude of fmin, and since the second counter 6 is reset every time the wheel speed pulse R occurs, the approximate equation (3) It is clear that the errors in equation ) are not accumulated and all wheel rotational speeds are calculated with approximately the same accuracy.

As described above, the digital value corresponding to the set maximum speed Vmax is obtained from the microcomputer 4 as the vehicle accelerates.Next, the case where the brake is applied from this state will be explained.

The frequency of the wheel speed pulse corresponding to the set maximum speed Vmax is set as max, and this is set as mal−fmin+PΔ
fi (where P is an integer), and if we now feel that the frequency of the wheel speed pulse R is Δf, the count value of the second counter 6 at this time is: Although this is not strictly (N+1), by taking N sufficiently large,
It can be made almost equal to this.

Therefore, the arithmetic unit of the microcomputer 4 subtracts "1" from (M+P), and the microcomputer 4 obtains a digital value of (M+P-1). Thereafter, in the same manner, each time the frequency of the wheel speed pulse R decreases by Δi, the digital value of the arithmetic unit in the microcomputer 4 is decreased by 1, and when the specified minimum speed Vmin is reached, the original digital value M
is obtained from the microcomputer 4.

As described above, according to the circuit of this embodiment, the wheel rotation speed is calculated almost instantaneously, and not only can the measurement accuracy be increased compared to the conventional method, but also the wheel rotation speed per bit can be calculated almost instantaneously. Since the value is approximately constant regardless of whether the wheel rotational speed is high or low, the wheel deceleration can be easily determined. For example, if the number of correction bits per unit time for the wheel rotation speed calculation circuit in the computer 4 is counted,
Deceleration or acceleration is immediately determined.

Although not shown, the digital output of the wheel speed calculator of the computer 4 is supplied to the approximate vehicle speed calculation circuit and the slip rate calculation circuit, and is used as a control signal for the valves that control the brake fluid pressure of the wheels as well as the acceleration and deceleration mentioned above. is formed, but since various configurations are known, a description thereof will be omitted.

Although the embodiment of the present invention is configured as described above,
Of course, the present invention is not limited to this, and various modifications can be made based on the technical idea of the present invention.

For example, in the above embodiments, the case where the present invention is applied to an automobile has been described, but of course it is also applicable to other vehicles such as two-wheeled motor vehicles.

In addition, in the above embodiment, the wheel speed pulses R, RI
A clear signal or a latch signal is provided to the counter or latch circuit each time the wheel speed pulse R,
A clear signal or a latch signal may be obtained every plural cycles of RI, for example every four cycles.
In this way, a plurality of wheel speeds can be calculated with just one circuit shown in FIG.

Further, in the above embodiment, the digital value of the arithmetic unit in the microcomputer 4 is changed by one each time the count value N of the second counter 6 changes by one, but the present invention is not limited to this. The digital value of the arithmetic unit may be changed by a plurality of values each time the value changes by one. Further, the ratio of change in the digital value of the calculation unit to the change in the count value of the counter 6 may be switched between a high range and a low range of the wheel rotation speed. In this way, even if the constant value N mentioned above is relatively small,
It is possible to accurately calculate the wheel rotation speed over the entire range.

The wheel speed calculation circuit of the present invention has the above-described configuration, and has the extremely remarkable effect of being able to instantaneously calculate the wheel speed and performing the differential operation extremely easily.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a wheel speed calculation circuit according to an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the operation of the circuit. In the figure, 1...first divider, 2...
...First counter, 4...Microcomputer, 5...Second divider, 6...Second counter, 8...Wheel speed sensor, 10, 11, 14...
...flip flop.

Claims (1)

[Claims] 1. A first divider that counts a constant high frequency signal and generates one pulse each time this count value equals a constant digital value, and a wheel speed signal with a frequency proportional to the rotational speed of the wheel. a wheel speed signal generator that generates a wheel speed signal, an arithmetic unit that calculates and outputs a digital value corresponding to the wheel rotation speed based on the wheel speed signal of the wheel speed signal generator, and a generator that generates the first divider. a first counter that continuously counts pulses within the period of the wheel speed signal or a period related to this period; a second divider that counts the signal and generates one pulse each time the counted value becomes equal to the output of the first counter; a second counter that continuously counts within the period or period after the period or period of the signal and supplies the counted value to the arithmetic unit as a signal based on the wheel speed signal, A wheel rotation speed calculation circuit characterized in that, when the count value of the second counter is not equal to the predetermined digital value, the output of the calculation unit is corrected by an amount corresponding to this difference.