JPS6133055A - Conversion circuit of communication speed - Google Patents

Abstract

PURPOSE:To attain communication between communication processors having different speeds of communication in an information system, by detecting the communication speed which is supplied to a communication processor and performing the transmission/reception of data according to the detected speed. CONSTITUTION:When a signal is supplied from a communication line 11, the detection signals are outputted from the rear and front edge detecting circuits 19 and 18 respectively. A flip-flop circuit 20 outputs logic 1, and the oscillation signal of an oscillator 16 is transmitted as a gate signal of a gate circuit 21. These gate signals are counted by a counter 22 and outputted to a latch 12. The value of the counter 22 is compared with the value of a latch 13 which holds the minimum value. Then a comparator 14 outputs the minimum count value of the counter 22. A converter 15 decides a ratio of division with said minimum count value and outputs it to a divider 17. The oscillation frequency of the oscillator 16 is divided to obtain a communication speed. Then the communication is performed between the communication processors of different speeds based on said communication speed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a communication speed conversion circuit for an information system that exchanges information using communication processing devices having different communication speeds.

Conventional configuration and its problems Conventionally, as shown in FIG. 1, when information is exchanged between communication processing devices having different communication speeds, for example, communication processing device 1
Communication must be performed by matching the communication speed of the communication processing device 2 with the communication speed of the communication processing device 2, and as shown in Fig. 2, there are multiple communication processing devices 2 to 4 with which to communicate, and each communication speed is different. In this case, the communication speed must be changed each time depending on the communication processing device of the other party with which information is to be exchanged, which is very inconvenient. A communication processing device whose communication speed cannot be switched has the disadvantage that it cannot communicate with a communication processing device having a different communication speed.

OBJECT OF THE INVENTION The present invention is intended to eliminate such conventional drawbacks.The present invention detects the communication speed input to a communication processing device and processes the communication so that communication between communication processing devices with different communication speeds can be easily performed. Data is received and transmitted depending on the speed.

Composition of the Invention The communication speed conversion circuit of the present invention converts the edges (leading edge and trailing edge) of a serial data signal input to a communication processing device when communicating between communication processing devices having different communication speeds. An edge detection circuit that detects and outputs a detection signal, and outputs a signal only during the time from the leading edge detection signal to the trailing edge detection signal or from the trailing edge detection signal to the leading edge detection signal of the output signal of the edge detection circuit. a flip-flop circuit, a gate circuit that uses the output of the flip-flop circuit as a gate signal and passes an oscillator signal, and counts the output signal of the gate circuit for the time that the gate is open, and ends counting when the gate closes. A counter that outputs a count signal, a latch that holds the count value that is the output of the counter, a latch that holds the minimum value among the count values that are sequentially input to the latch, and the values of the latch and the latch are compared. a comparison circuit that outputs the smaller value among the respective values; and a frequency division of the oscillator signal based on the count value output from the comparison circuit at the time of the gate signal of the gate circuit when the count value is counted by the counter. and a frequency divider that divides the oscillator signal into the time of the minimum gate signal input to the gate circuit by the output of the converter. The present invention is characterized in that communication with communication processing devices having different communication speeds is performed using the minimum time interval of the gate signals as the communication speed.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Fourth
A configuration example is shown in the figure. When communication processing device 7 communicates with communication processing devices 8 to 1o having different communication speeds, communication speed conversion device 6 is connected to communication circuit 11 in parallel. Communication processing devices 8 to 1o have different communication speeds and the same signal string "00101"
101” to the communication processing device 7 (communication processing device 8
~1° (as shown in a'%-C in FIG. 3), the communication processing device 7 must receive the signal using the communication speeds of the communication processing devices 8 to 10.

At this time, a communication speed conversion circuit 6 that automatically detects the communication speeds of the communication processing devices 8 to 1o and outputs the detected communication speeds to the communication processing device 7 is shown in FIG.

In the following explanation, signals are expressed using logic levels "1" and "0". When a signal (see Fig. 6 C) is input from the communication line 11, the trailing edge of the input signal changing from "1" to "0" is detected, and when detected, a detection signal of "1" (see Fig. 6 C
Similarly, the trailing edge detection circuit 19 outputs a leading edge that changes from "0" to "1" and outputs a "1" detection signal (6th
The edge portion of the input signal is detected by the leading edge detection circuit 2o which outputs the signal shown in FIG. The detection signals from the leading edge detection circuit 2o and the trailing edge detection circuit 19 are received, and the time from the time when the leading edge detection signal is detected to the time when the trailing edge detection signal is detected, or vice versa, is determined from the time when the trailing edge detection signal is detected. "1" is output from the flip-flop circuit 20 only during the time until the leading edge detection signal. The output of this flip-flop circuit 20 is used as a gate signal of a gate circuit 21, and the oscillation signal of the oscillator 16 is passed therethrough. Since the output signal of the gate circuit 21 corresponds to the time interval between edges, this signal is counted by the counter 22. When the gate signal becomes '0'', the counting by the counter 22 is finished and the counted value is sent to the ratte 12. The count value of the counter is cleared to 0.The above operation is performed when the counter 2 is output every time a series of edge detection signals including the leading edge detection signal and the trailing edge detection signal are detected.
2 and output to the latte 12. When detecting the communication speed with this communication speed conversion circuit 6, if the maximum value that can be input to the latch 13 is substituted as a default value, the value of the latch 13 and the value of the latch 12 are first compared using the ratio pattern 14, A small value is output and the latch 13 holds the small value. Thereafter, the value of the counter 22 held in the latch 12 and the value of the latch 13 are compared, and the comparator 14 outputs the value of the counter 2.
The smallest value counted by 2 is always output. The output from the comparator 14 is output to the latte 13 and also to the converter 15. The converter 15 receives the output of the comparator 14, which is the minimum value counted by the counter 22, and divides the frequency of the oscillator 16 at the time of the gate signal of the gate circuit 21 when the counted value is measured. is determined and output to the frequency divider 17.

Further, in the converter 16, when a certain period of time has elapsed since the comparator signal is first input to the converter 16, an output prohibition signal is output to the gate circuit 21, and the counter 22 stops counting thereafter. That is, the counter 22 counts in the trench where the output prohibition signal is output, and when the output prohibition signal is output, the counter 22 stops counting and determines the frequency division ratio based on the minimum counted value previously counted.

The frequency division ratio is outputted to a frequency divider, and the oscillation frequency of the oscillator is divided, and the result is used as a common communication speed for communication between communication processing devices having different communication speeds.

Effects of the Invention By using the configuration described above, the present invention automatically detects the communication speed transmitted from one communication processing device having a different communication speed, and performs reception or transmission based on the detected communication speed. be able to. As a special case, it can be easily applied to information processing systems with different communication speeds for transmission and reception.

[Brief explanation of drawings]

FIGS. 1 and 2 are diagrams showing examples of connections between conventional communication processing devices with different communication speeds, FIG. 3 is a diagram showing serial data signals when communication speeds are different, and FIG. FIG. 5 is a configuration diagram showing a connection example of a communication speed conversion circuit according to an embodiment of the present invention. FIG. 5 is a configuration diagram of a communication speed conversion circuit according to an embodiment of the present invention. FIG. It is a diagram. 6...Communication speed conversion circuit, 7-10...
・Communication processing device, 11...Communication line, 12.1
3... Latch, 14... Comparator, 15...
...Converter, 16...Oscillator, 17...
... Frequency divider, 18 ... Leading edge detection circuit, 19
-0. ... Trailing edge detection circuit, 2o ... Flip-flop circuit, 21 ... Gate circuit, 22 ...
····counter. Name of agent: Patent attorney Toshio Nakao 11 or 1 person Figure 1

Claims (1)

[Claims] An edge detection circuit that detects the falling (leading edge) and falling (trailing edge) edges of serial data signals input to communication processing devices with different communication speeds, and from the leading edge to the trailing edge or from the trailing edge to the leading edge. a flip-flop circuit that outputs an output signal for a period of time; a gate circuit that uses the output signal from the flip-flop circuit as a gate signal and passes the oscillator signal;
a counter that counts the gate output signal while the signal from the gate circuit is output, stops counting when the gate output signal is no longer output, outputs the counted value to a data holding circuit, and clears the counted value; A latch that holds the output of the counter, a latch that holds the minimum value among the successively inputted counter values, a comparison circuit that compares the values of the latch and outputs the smaller value, and an output signal of the comparison circuit that is the minimum value. A converter that converts the count value of 1 to a length of time and determines and outputs a frequency division ratio for dividing the frequency of the oscillator into the period of that time, and a frequency divider that divides the frequency of the oscillator. The communication processing device detects the communication speed (the minimum time interval from the leading edge to the trailing edge or from the trailing edge to the leading edge) of the serial data signal input to the communication processing device, and exchanges information at the same communication speed as the input signal. A communication speed conversion circuit that enables easy communication even between communication processing devices having different communication speeds.