JPS62133841A - Asynchronizing serial system data communication system - Google Patents

Abstract

PURPOSE:To attain sure data recognition by selecting an in-phase or an antiphase clock in the timing between the data transmission data of a clock having the same frequency as the data transmission speed to use a sampling clock. CONSTITUTION:DFFs 3, 4 use a clock 22 as a clock input CLK and input data 21 and delayed data 21 by a delay element 1 as a data input D. DFFs 5, 6 use an inverted clock 23 the input CLK and the data 21 and the delayed data 21 by the element 1 as the input D. An RSFF 9 outputs a clock selection signal 24 or 25, an AND circuit 10 outputs a clock 22 when the signal 24 is outputted and an AND circuit 11 outputs a clock 23 when the signal 25 is outputted. An AND circuit 11 outputs a clock 23 when the signal 25 is outputted. An OR circuit 12 outputs the clock 22 or 23 outputted from the circuits 10, 11 as a sampling clock 26 to prevent malfunction thereby applying sure data transmission.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an asynchronous serial data communication system.

[Conventional technology]

FIG. 4 is a timing diagram when the data transmission speed and the frequency of the read sampling basic clock are the same in a conventional asynchronous serial data communication system.

FIG. 4(a) is a timing diagram of normal operation, in which the rising edge of the sampling clock read occurs when the transmitted data is stable. In this case, reading errors do not occur and normal transmission can be performed. However, since the transmission data is generally transmitted arbitrarily, as shown in Figure (b), if the change in the transmission data and the reading edge of the sampling clock are at the same time, the transmission data is not determined, so O''
I don't know whether it will be judged as "l" or "l".

Conventionally, a sampling clock with a frequency higher than the data transmission speed is used to prevent reading errors and ensure the certainty of reading the transmitted data when the reading edges of the sampling clock coincide with such changes in the transmitted data at critical timing. was.

FIG. 4 is a timing diagram in the case where the conventional basic clock frequency is eight times the transmission speed.

The 1-bit data time width of the transmission data and the clock period obtained by dividing the basic clock (period t%I) by 8 are the same, and in a normal case, the sampling data at the rising edge of the 8-divided clock (circled in the figure) is the same. The enclosed numbers) are read as the transmitted data. At critical timings when a change in transmission data and a change in the basic clock occur at the same time, data at the rising edge of either the previous or subsequent basic clock is recognized as the transmission data as a measure to prevent malfunction.

[Problem that the invention seeks to solve]

In the conventional method described above, as the transmission speed increases (the time width of one data bit becomes shorter) due to the desire for high-speed data transmission, the supply of the basic clock that is 8 times or more required for data recognition and malfunction prevention becomes high frequency. It becomes too difficult.

For example, in order to achieve a data transmission rate of 10 Mbps, a basic clock of 80 MHz or higher must be provided, which is impossible to achieve with a simple electronic circuit.

An object of the present invention is to provide an asynchronous serial data communication system that can prevent malfunctions at critical timings and can reliably recognize data, even though it requires a high-frequency basic clock.

[Means for solving problems]

The asynchronous serial data communication system of the present invention detects that the time from a change in transmitted data to the first rising or falling edge of a clock having the same frequency as the data transmission rate is within a certain period of time. Then, a timing detection circuit that outputs a detection signal, and a sampling clock that samples the transmission data by using a clock that has the same phase as the clock when the detection signal is not output, and a clock that has the opposite phase to the clock when the detection signal is output. The present invention is characterized in that it includes a clock selection circuit that selects a clock.

[Effect]

Using a clock with the same frequency as the data transmission rate
There are a total of two rising (falling) edges of a clock and its opposite phase clock (clock) in 1-bit transmission data. When the rising (falling) edge of the clock comes within the detection time of the timing detection circuit (this is set to 0 to % of the 1-bit transmission data time width), this edge is discarded and the rising (falling) edge of the clock becomes the sampling edge.

As a result, the sampling edge is always secured in the interval between % and % of the 1-bit transmission data time width, which prevents malfunctions.
This prevents the critical timing of misreading.

Note that in order to detect that a sampling edge has entered within the detection time, one bit "l" must precede the transmitted data, but this is due to the way the protocol is set and there is no problem.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing essential parts of an embodiment of an asynchronous serial data communication system according to the present invention, and FIGS. 2 and 3 are time charts thereof.

A detection time T is set in the delay element 1. Inverter 2
outputs a clock 23 by inverting the clock 22. D
The flip-flop 3.4 uses the clock 22 as the clock input CLK, the input data 21 and the input data 21 delayed by the delay element 1 as data input, and the exclusive OR circuit 7 uses the non-inverting output of the D flip-flops 3 and 4. Q and these detect that the clock 22 enters within the detection time T. D flip-flops 5 and 6 are clock 2
3 is the clock CLK, the input data 21 and the input data 21 delayed by the delay element 1 are used as data inputs, and the exclusive OR circuit 8 inputs the non-inverting output Q of the D flip-flop 5.6. It is detected that death 5f d23 has entered within the detection time T. The RS flip-flop 9 inputs each detection signal to the set input S and the reset input R, and outputs the clock selection signal 24 or the clock selection signal 2.
5, the AND circuit 10 outputs the clock selection signal 24
is output from the lock 22, and the AND circuit 11
outputs the clock 23 when the clock selection signal 25 is output. The OR circuit 12 outputs the clock 22 or the clock 23 output from the AND circuit 10.11 as a sampling clock 26.

Note that the transmission data input line is "0" in a static state with no transmission data, and the transmission start is always 1 bit "l".
” precedes.

Next, the operation of this embodiment will be explained with reference to the time charts of FIGS. 2 and 3.

(1) When the rising sampling edge of the clock 22 is located approximately at the center of the input data 21 (FIG. 2).

In this case, the output of the exclusive OR circuit 7 is "■" and the output of the exclusive logic circuit 8 is "0", so the clock selection signal 24 is "l" (true) and the clock selection signal 25 is "?". ′
0'' (false), clock 22 is selected as sampling clock 26.

(2) When the rising sampling edge of the clock 22 falls within the detection time T (FIG. 3).

In this case, the output of the exclusive OR circuit 7 is "0" and the output of the exclusive OR circuit 8 is "1", so the clock selection signal 24 is "0" (false) and the clock selection signal 25 is ”
1'' (true), the clock 23 is selected as the lock 26 for sampling.

That is, even if the rising sampling edge of the clock 22 falls within the detection time T, the sampling edge of the sampling clock 26 falls outside the detection time T, so no malfunction in reading the input data 21 occurs.

〔Effect of the invention〕

As explained above, the present invention uses a clock with the same frequency as the data transmission speed, and when the sampling edge of the clock comes within the set interval from the time of change of the transmitted data, a clock with the opposite phase of the clock is used. Using a sampling clock has the effect of preventing malfunctions at critical timings and enabling reliable data transmission without requiring a high-frequency clock.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing essential parts of an embodiment of the asynchronous serial data communication system of the present invention, FIGS. 2 and 3 are time charts of the circuit in FIG. 1, and FIG. 4 is a conventional asynchronous serial data communication system. FIG. 5 is a time chart when the frequency of the read sampling basic clock is eight times the transmission speed. l...delay element, 2...inverter, 3.
4, 5.6... D flip-flop, 7.8... Exclusive OR circuit, 9... RS flip-flop, 10, 11... AND circuit, 12... OR circuit,
21...Input data, 22...Clock, 2
3... Clock, 24... Clock selection signal, 25
... Clock selection signal, 26... Sampling clock. Patent applicant: Yaskawa Electric Co., Ltd. Representative: Tadayoshi Wakabayashi Figure 3

Claims (1)

[Claims] In an asynchronous serial data communication system, the time from when the transmitted data changes to the first rising or falling edge of a clock having the same frequency as the data transmission rate is within a certain period of time. a timing detection circuit that outputs a detection signal when the detection signal is detected; and a timing detection circuit that samples the transmission data using a clock that is in phase with the clock when the detection signal is not output, and a clock that is in opposite phase to the clock when the detection signal is output. An asynchronous serial data communication system characterized by comprising a clock selection circuit for selecting a sampling clock to be used.