JP3456912B2 - Data interface circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data data interface circuit, and more particularly to a two-terminal control data interface circuit for converting serial data into parallel data.

[0002]

2. Description of the Related Art The basic function of a serial controller is
These are parallel data conversion of serial data and serial data conversion of parallel data. Generally, serially transmitted received data is converted into parallel data having a data width of 8 bits or 16 bits by serial data conversion, and is taken into an internal data bus.

The parallel data conversion of the serial data can be easily realized by using a shift register having a predetermined bit length (for example, 8 bits). A serial / parallel data conversion circuit mainly composed of a shift register used for this purpose is hereinafter referred to as serial IN / parallel OUT.
(Hereinafter referred to as SI / PO). This SI / PO
When the serial data is input to the input terminal SI and the shift clock SCK is supplied to the clock terminal CK, the data is read at the rising edge of the clock, the data is sequentially shifted, and the parallel data is output to the output terminal PO. Further, this SI / PO generally has a clear terminal capable of resetting an internal shift register and a function of inputting two data inputs to a data input terminal via a NAND gate.

[0004]

However, the conventional serial data interface circuit under the control of two terminals has the following problems.

That is, a hazard (fine pulse) may be superimposed on the shift clock SCK due to an external factor, and it is considered that the circuit malfunctions when the hazard is superimposed on the SCK. It is desirable to eliminate the generation of noise and hazards, but it is difficult to completely prevent noise and the like generated in various places, and in many cases, it is unavoidable to use it in such an environment.

Further, the conventional circuit simply reads serial data, sequentially shifts it, and outputs it as parallel data. Therefore, in order to actually use it, what information is used to start the exchange of data with the outside. You must give it by that method. For example, when one of the NAND gates of the SI / PO is used as a control input and the data input is prohibited, the control input is set to "L" to prevent the internal input of the data input. This control input must be generated and supplied by another control circuit like a chip select (CS) signal. In addition, SI / PO is such NA
If the ND gate is not provided, it is necessary to provide a gate circuit corresponding to this on the input side. In any case, the conventional circuit has a drawback that it cannot be used simply by inputting data because it cannot be a trigger for starting data exchange with the outside and is very difficult to use. .

The present invention provides a data interface circuit which can easily realize a data interface only by inputting data and can prevent malfunction of the circuit even if noise or hazard is superimposed on a clock. With the goal.

[0008]

A data interface circuit according to the present invention reads serial data input to a data input terminal according to a clock input to a clock terminal, sequentially shifts it, and outputs it as parallel data to an output terminal. Shift register, detecting means for detecting that a fixed level signal is input to the data input terminal for a predetermined time, counting means for counting the number of received data, and shifting the clock when the fixed level signal is detected. The control means controls input to the register so that when the count by the count means reaches a predetermined number of data, the control means disables clock input.

The data interface circuit according to the present invention comprises means for detecting the input of a pulse during the detection period of the fixed level signal, and the control means detects the fixed level signal and also detects the fixed level signal. The clock may be controlled so that it can be input to the shift register when no pulse is input during the period.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. First Embodiment FIG. 1 is a circuit diagram showing a configuration of a data interface circuit according to an embodiment of the present invention.

In FIG. 1, a data interface circuit 10 detects that a serial IN / parallel OUT shift register (SI / PO) 11 and a data input terminal DATA are at "L" level for a certain period of time (here, 1 μs). 1 μs detector 12 (detection means), counter 13 (counting means) for counting the number of received data,
AND gate 14, N forming an RS flip-flop
It is composed of OR gates 15 and 16, an inverter 17, a D flip-flop (DFF) 18, and an OR gate 19.

The AND gate 14 and the NOR gate 1
5, 16, inverter 17, D flip-flop (DF
F) 18 and the OR gate 19 constitute a control means for controlling so as to receive the input from the SCK terminal only during the data reception as a whole.

The data input terminal DATA is SI / PO1.
It is connected to the serial input terminal SI of 1 and the input terminal IN of the 1 μs detector 12. In addition, the shift clock SCK
Is connected to the input terminal of the AND gate 14, the reset terminal R of the 1 μs detector 12, and the input terminal CKB of the counter 13.

The SI / PO 11 is a serial IN / parallel OUT shift register, and has a serial input terminal S.
I is connected to the data input terminal DATA, the shift clock terminal CK is connected to the output terminal of the AND gate 14,
The parallel output from the parallel output terminal PO is output to the internal data bus.

The 1 μs detector 12 has a data input terminal DA
This is a circuit for detecting the “L” level of TA for 1 μs. The data input terminal DATA is connected to the input terminal IN, the shift clock SCK is connected to the reset terminal R, and the output terminal OUT is the input terminal of the NOR gate 15. Connected to. Details of the circuit configuration of the 1 μs detector 12 will be described later.

The counter 13 counts only the number of received data, the input terminal CKB is connected to the shift clock SCK and the reset terminal R of the 1 μs detector 12, and the overflow signal terminal CO is connected to the clock input of the DFF 18. Reset terminal R is OR gate 1
9 output terminals. The other input terminal of the OR gate 19 is connected to the reset terminal.

The D input of the DFF 18 is fixed to the "H" level, and the Q output is connected to the input terminal of the NOR gate 16.

The NOR gates 15 and 16 form an RS flip-flop, and the output of the NOR gate 15 is connected to the input terminal of the inverter 17, one input terminal of the NOR gate 16 and the input terminal of the OR gate 19. The output of the NOR gate 16 is connected to the other input terminal of the NOR gate 15.

The output SCKE of the inverter 17 is connected to one input terminal of the AND gate 14, and the AND gate 1 outputs
The other input terminal of 4 is connected to the shift clock SCK.

FIG. 2 is a circuit diagram showing an example of the configuration of the 1 μs detector 12, and FIG. 3 is a timing chart showing the waveform of each part of the circuit of FIG.

In FIG. 2, the 1 μs detector 12 is composed of five D flip-flops (DFFs) 101 to 105, an inverter 106 and a NAND gate 107.

The input data SD is connected to the D input of the DFF 101 and the clock input of the DFF 105, and the master clock CLK is connected to the clock inputs of the DFFs 101 to 103. In addition, resetting is performed for each DFF 101 to 10
5 reset terminal.

The input data SD is input to the D input of the DFF 101, and the output Q1 of the DFF 101 is the next DFF 10
The output Q2 of the DFF 102 is input to the D input of the next DFF 103 and the inverter 106. The output of the inverter 106 is the NAND gate 1
07, and the output Q of the DFF 103 is input to the other input terminal of the NAND gate 107.

The D input of the DFF 104 is fixed to the "H" level, and the output Q of the NAND gate 107 is the DFF 104.
Connected to the clock input of. The output Q4 of the DFF 104 is input to the D input of the next DFF 105,
The output Q of 105 is connected to the output terminal OUT.

The circuit shown in FIG. 2 can change the detection time according to the cycle of the input master clock CLK. As shown in FIG. 3, when the CLK cycle is 1 μs cycle, the circuit shown in FIG. 2 becomes the 1 μs detector 12. Further, if the CLK cycle is 1 ms cycle, it becomes a 1 ms detector. In the present embodiment, the 1 μs detector is configured by supplying the CLK of the 1 μs cycle, but this is only an example and a detector that detects another cycle may be used.

The operation of the data interface circuit 10 configured as described above will be described below. Here, 8
The bit data interface will be described.

FIG. 4 shows the data interface circuit 1 described above.
6 is a timing chart showing the operation of 0.

First, as shown in FIG. 4, the data input terminal D
When “L” level of 1 μs or more is input from ATA,
The 1 μs detector 12 detects the “L” level of 1 μs and outputs “H” to the output terminal OUT. This allows
The DFF 18 is reset, and the NOR gate 15 and
Since 16 constitutes an RS flip-flop, RS
Inverter 17 output S that has inverted flip-flop output
CKE becomes "H" level, and the AND gate 14 can receive the shift clock SCK.

Next, the shift clock SC is input from the SCK terminal.
When K starts to be input, since SCKE is at “H” level, it is input to the clock terminal CK of SI / PO11 via the AND gate 14, and SI / PO11 reads data at the rising edge of this shift clock. , Data is sequentially shifted and output as parallel data to the output terminal PO.

On the other hand, from the SCK terminal, the shift clock SC
When K starts to be input, the 1 μs detector 12 is reset. At this time, the inverter 17 output SCKE is R
The S flip-flop holds the "H" level. Further, at this time, the counter 13 is performing the counting operation, and when the shift clock SCK is counted from 0 to 7, the H pulse is output to the overflow signal terminal CO. Then, the DFF 18 outputs the “H” level from the output Q at the trailing edge of the H pulse output from the overflow signal terminal CO. As a result, the inverter 17 output SCKE, which is the inverted RS flip-flop output, becomes "L" level, and the AND gate 14 cannot receive the shift clock SCK thereafter.

As described above, the data interface circuit 10 according to the first embodiment has the serial IN /
Parallel OUT shift register (SI / PO) 11,
1 μs detector 12 for detecting that data input terminal DATA is at “L” level for a certain period of time, counter 13 for counting the number of received data, AND gate 14, R
NOR gates 15 and 1 forming an S flip-flop
6, the inverter 17, the DFF 18, and the OR gate 19 are provided, and when the 1 μs detector 12 detects the “L” level of the data input terminal DATA for a certain period of time, it is used as a data reception start signal, and the counter 13 counts 8-bit data. Since the shift clock SCK can be input to SI / PO11, the control for starting the exchange of data with the outside as in the conventional example is unnecessary, and the data reception can be started by simply inputting the data. Can
A very easy-to-use data interface can be realized.

Since the input from the SCK terminal is not accepted until the data reception start signal is input, malfunction of the circuit can be surely prevented even if noise or hazard is superimposed on the clock. . Second Embodiment FIG. 5 is a diagram showing an overall configuration of a data interface circuit according to a second embodiment of the present invention. In the description of this embodiment, the same parts as those in the configuration of FIG. 1 are designated by the same reference numerals, and the description of the overlapping parts will be omitted.

In FIG. 5, the data interface circuit 20 outputs a shift register (SI / PO) 11 for serial IN / parallel OUT, a fall detector 21 for detecting the fall of the data input terminal DATA, and a fall detector 21. Is received by the control terminal E, and detects that the data input terminal DATA is at the “L” level for a certain period of time (1 μs), the 1 μs detector 12, the 1 μs detector 1
A D flip-flop (DFF) 22 that holds two outputs according to a change in the data input terminal DATA, a counter 13 that counts the number of received data, an AND gate 14, and a NOR gate 1 that constitutes an RS flip-flop.
5, 16, an inverter 17, a DFF 18, and an OR gate 19.

The fall detector 21 and the DFF 22
Is H during the detection period of “L” level of 1 μs as a whole.
A means for detecting that a pulse has been input is configured.

The data input terminal DATA is SI / PO1.
It is connected to the serial input terminal SI of 1, the input terminal IN of the fall detector 21 and the input terminal IN of the 1 μs detector 12. The shift clock SCK is connected to the input terminal of the AND gate 14, the reset terminal R of the fall detector 21, the reset terminal R of the 1 μs detector 12, the reset terminal R of the DFF 22, and the input terminal CKB of the counter 13.

The falling edge detector 21 detects the falling edge of the data input terminal DATA, and can be simply constructed by, for example, two DFFs and a NOR gate.

The 1 μs detector 12 has a data input terminal DA
This is a circuit for detecting the “L” level of TA for 1 μs. In the present embodiment, a terminal E for controlling the input acceptance of the 1 μs detector 12 is further provided. The control terminal E is connected to the output terminal OUT of the fall detector 21. The data input terminal DATA is connected to the input terminal IN, the shift clock SCK is connected to the reset terminal R, and the output terminal OUT is connected to the input terminal of the NOR gate 15.

The DFF 22 is for holding the output of the 1 μs detector 12, the input D of the DFF 22 is connected to the output terminal OUT of the 1 μs detector 12, the clock input is connected to the data input terminal DATA, and the reset terminal R. Is S
The Q output is connected to the CK terminal, and the Q output is connected to the input terminal of the NOR gate 15 and the reset terminal R of the DFF 18.

The operation of the data interface circuit 20 configured as described above will be described below. Here, 8
The bit data interface will be described.

FIG. 5 shows the data interface circuit 2 described above.
6 is a timing chart showing the operation of 0.

First, as shown in FIG. 5, the data input terminal D
When ATA changes from "H" to "L", the fall detector 21 detects this fall and outputs "H" level from the output terminal OUT. The 1 μs detector 12 receives the “H” level at the control terminal E and becomes in the operable state.

From the data input terminal DATA, 1 μ
When an “L” level of s or more is input, the 1 μs detector 1
2 detects the “L” level of 1 μs to output terminal O
Output "H" to UT.

After that, when the data input terminal DATA changes from "L" to "H" as shown in FIG.
Holds the “H” level of the output of the 1 μs detector 12 at this timing, and outputs the “H” level from the Q terminal. As a result, the output SCKE of the inverter 17, which is the inverted output of the RS flip-flop, becomes "H" level, and the AND gate 14 can receive the shift clock SCK. At this time, the DFF 18 is reset and the reset of the counter 13 is released.

Next, "H" is applied from the SCK terminal to the SCK terminal.
Is input, the falling detector 21, the 1 μs detector 12 and the DFF 22 are reset, but the inverter 1
The 7-output SCKE holds the "H" level by the RS flip-flop. Further, the reset of the DFF 18 is released.

At this time, the counter 13 performs the counting operation at the trailing edge of the shift clock SCK, and the count operation is from 0 to 7.
Up to the H level, the H pulse is output to the overflow signal terminal CO. And
At the trailing edge of the H pulse output from the overflow signal terminal CO, the Q output of the DFF 18 becomes "H" level. At this time, the Q output of the DFF 21 is "L" level, so the inverter 17 output SCKE becomes "L" level. , After that A
The ND gate 14 no longer receives the shift clock SCK.

As described above, the data interface circuit 20 is in the operable state unless the “L” level of 1 μs or more is once input from the data input terminal DATA and the H pulse is not input from the SCK terminal during that time. Even if data is being received, if the above state is input, data reception can be restarted from the beginning.

As described above, the data interface circuit 20 according to the second embodiment includes the fall detector 2 that detects the fall of the data input terminal DATA.
1. The output of the falling detector 21 is received by the control terminal E, and the output of the 1 μs detector 12 and the output of the 1 μs detector 12 that detects that the data input terminal DATA is at the “L” level for a certain period of time changes the data input terminal DATA level. The data input terminal DATA.
Is detected as a trigger for starting data reception only when the "L" level is detected for a certain period of time and the H pulse is not input from the SCK terminal during that period, and the shift clock SCK is set to SI.
Since the input / output is configured to be input to / PO11, the same effect as that of the first embodiment can be obtained, and data can be input again during data reception, and a data interface that is even easier to use is realized. be able to.

Therefore, if the data interface circuit having such excellent features is applied to a serial controller or the like, it is possible to realize a very easy-to-use device without malfunction due to hazard.

The data interface circuit according to each of the above-described embodiments can be applied to the serial controller or the like as described above, but the present invention is not limited to this, and any device can be used as long as it is a serial data interface circuit. Applicable.

Further, in each of the above-mentioned embodiments, the fixed level for a predetermined time is the “L” level of 1 μs, but it is 1 μs.
It may be any time other than the above, and may be another fixed level (for example, “H” level). Also, although the 8-bit data interface has been described, it is needless to say that the bit length is not limited to this and, for example, 16-bit SI / PO is used.
If a counter is used, a 16-bit data interface can be obtained.

Furthermore, the data interface circuit, the DFF, the gate circuit, and the like, which constitute the 1 μs detector and the like,
The type and number of inverters and the like are not limited to those in the above embodiment.

[0052]

In the data interface circuit according to the present invention, the serial data input to the data input terminal is read according to the clock input to the clock terminal, sequentially shifted, and output to the output terminal as parallel data. Detecting means for detecting that a fixed level signal is inputted to the data input terminal for a predetermined time,
Counting means for counting the number of received data,
When a fixed level signal is detected, the clock is controlled so that it can be input to the shift register, and when the count by the counting means reaches a predetermined number of data, the control means for controlling the clock input to be disabled is provided. A data interface can be easily realized simply by inputting data, and malfunction of the circuit can be prevented even if noise or hazard is superimposed on the clock.

The data interface circuit according to the present invention comprises means for detecting the input of a pulse during the detection period of the fixed level signal, and the control means detects the fixed level signal and also detects the fixed level signal. Since the clock is configured to be input to the shift register when no pulse is input during the period, in addition to the above effect, it is possible to input data again during data reception, which is even easier to use. A data interface can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a data interface circuit according to a first embodiment to which the present invention is applied.

FIG. 2 is a circuit diagram showing an example of a configuration of a 1 μs detector of the data interface circuit.

FIG. 3 is a timing chart showing a waveform of each part of the 1 μs detector of the data interface circuit.

FIG. 4 is a timing chart for explaining the operation of the data interface circuit.

FIG. 5 is a circuit diagram showing a configuration of a data interface circuit according to a second embodiment of the present invention.

FIG. 6 is a timing chart for explaining the operation of the data interface circuit.

[Explanation of symbols]

10, 20 Data interface circuit, 11 Serial IN / Parallel OUT shift register (SI / P
O), 12 1 μs detector (detection means), 13 counter (counting means), 14 AND gate, 15, 16
NOR gate, 17 inverter, 18, 22 D flip-flop (DFF), 19 OR gate, 21 falling detector

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03M 9/00 G06F 5/00

Claims (2)

(57) [Claims] 1. A shift register which reads serial data input to a data input terminal according to a clock input to a clock terminal, sequentially shifts the serial data, and outputs parallel data to an output terminal, and a fixed time fixed to the data input terminal for a predetermined time. Detecting means for detecting that a level signal has been input, counting means for counting the number of received data, and controlling the clock so that the clock can be input to the shift register when the fixed level signal is detected, A data interface circuit, comprising: a control unit that disables the clock input when the count by the count unit reaches a predetermined number of data. 2. A means for detecting input of a pulse during the detection period of the fixed level signal, wherein the control means detects the fixed level signal and during the detection period of the fixed level signal. 2. The data interface circuit according to claim 1, wherein the clock is controlled so that the clock can be input to the shift register when no pulse is input.