JPS6020273A - Data transfer system - Google Patents

Abstract

PURPOSE:To enable data transfer to the voluntary processor by issuing input/ output instruction which indicates a processor address from one processor in a data processing system having multiple processors. CONSTITUTION:When input/output instruction is executed in the processor, the input/output unit number and processor address are sent for the input/output controller 2. The processor number to which data are transferred is identified by setting the input/output unit number and processor address to the processor address register 21, and decoding them by the decoder 23. When the processor is the one exclusive for controlling the system, the flag register 22 is set to ON in advance and the decoder 23 is activated, and therefore, the gate circuit 24 of the data line for the processor is opened, and data which are sent fom the input/ output unit can be transferred through the transfer route 5.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a method for transferring data from an input/output processing device connected to one processor to each processor in a data processing system having a plurality of processors. Regarding.

(bl Technology background) As data processing systems have become larger in recent years, the operating system (O3) has been occupying a larger proportion of the programs executed by Prosensor. Therefore, it has been desired for customers to build a ProSensor with less overhead, for example by having the operating system (O5) run on a dedicated processor.

In addition, currently, the operating (O3) and user programs are executed on processors with the same hardware configuration, but if we consider processors with dedicated hardware configurations, each may have unnecessary functions. No longer needed.

For example, in a processor dedicated to the operating system (O3), there is a system control function.

The operating system (O5
) can be used to construct an effective pro-sensor.

In the user-dedicated ProSensor, in addition to eliminating the need for the operating system-dedicated functions mentioned above, for example, in the case of science and technology, there are many floating point calculation instructions, so it is necessary to speed up the instructions, and in the case of office use, it is necessary to Since there are many decimal operation instructions, a data processing system with high processing efficiency can be constructed by increasing the speed of these instructions.

The present invention was devised in light of the current state of data processing systems, and aims to centrally manage input/output processing using a processor dedicated to system control.

(C) Prior art and problems When an input/output command is executed in a data processing system composed of multiple processors, in the conventional technology, the input/output command only specifies the channel number and input/output device number. Therefore, data transfer by the input/output command is performed by the processor that issued the input/output command (
Ultimately, it was only performed on the main memory connected to the processor.

Therefore, even when one processor is assigned as a dedicated processor for system control (including input/output control), data cannot be transferred to other processors using the input/output instructions issued by that processor number. It was necessary to provide an input/output control function for each of the other user-dedicated processors/7 servers. Also, there was a function to transfer data from the input/output processing device connected to one processor to another processor. As an alternative means within the scope of the prior art, there is a method of operating the system control dedicated processor in memory copy mode. (However, it is assumed that each processor and the main memory are connected to each other by a bus.) In this method, the processor dedicated to system control executes conventional input/output instructions and connects to the processor. When receiving data transfer from an input/output processing device, the processor sets the operating mode to memory copy mode, receives the data, and transfers the data to the main memory connected to another processor through the bus. This is a method of isometrically transferring data from one input/output processing device to a plurality of other processors by transferring data.

Therefore, each processor is not involved in the data transfer, so when the data transfer is completed, the system control processor sends an interrupt request, etc.
It was necessary to have each processor notify that the necessary data had been transferred to main memory, and after receiving that notification, proceed to each processor's own processing regarding that data. .

Tdl Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention provides that, in a data processing system composed of a plurality of processors, when one processor is assigned as a processor dedicated to system control, the input/output issued by that processor is The purpose is to provide a method that allows data transfer to other processors by instructions.

(e) Structure and object of the invention According to the present invention, in a data processing system having a plurality of processors, by issuing an input/output command specifying a processor address from one processor, the other processors This is achieved by providing a method that allows data transfer to
Data can be transferred to any processor by simply connecting an input/output processing device to the dedicated system control processor, which has the advantage of making it possible to construct an economical and efficient data processing system.

(f) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram explaining the present invention in detail, and FIG. 2 is a block diagram showing one embodiment of the present invention.

In FIG. 1, numeral 1 denotes a processor, which in this embodiment is composed of a central processing unit and a channel device.

2 is an input/output processing unit (IOC). In this figure, (a) shows a data transfer method using input/output commands in the conventional method 1, for comparison with the present invention, and the input/output commands only include channel device numbers and input/output device numbers. Since no instructions are given, data transfer is performed only to the processor that issued the input/output command.

(B) shows the data transfer method when the present invention is implemented. In this method, the input/output command specifies the processor address of the data transfer destination, so data can be transferred to any other processor. It is.

In FIG. 2, (a) shows an example of a data transfer method using an octopus connection, and (b) shows an example of a data transfer method using an inlet connection.

First, the case of octopus-leg connection will be explained with reference to FIG. 1(b). In (a), 2 is the same as that explained in FIG. 1, 21 is a processor address register (PAR) that stores the processor address specified by an input/output instruction, and 22 is a register for executing the input/output instruction. This flag register (F) is turned on when this input/output processing unit 2 is connected to a processor dedicated to system control. 23 is a decoder, 24 is an AND circuit, and 5 is a data transfer path.

When an input/output instruction to which the present invention is applied is executed in the processor 1, an input/output processing unit (IOC) 2 is assigned the same number as the conventional input/output device number.

The processor address will be sent, so set this to the processor address buster (PAR) 2H,
By decoding with the decoder 23, the processor number to which the data is to be transferred can be identified. If,
If the processor 1 is a processor dedicated to system control, the flag register (F) 22 is set on in advance and the decoder 23 is activated.
Data line gate circuit 24 for the processor 1
is opened and an input/output device (not shown) is connected through the transfer path 5.
Data sent from the processor 1 can be transferred to the processor 1.

Next, the case of bus connection will be explained. In (b), 1 and 2 are the same as those explained in Figure 1,
21.22 are the same as those explained in (a).

25 and 26 are AND circuits, 11 is a processor identification register (PRR), and 12 is a processor number setting circuit (PND), in which a processor number determined by each processor is set. 13 is a comparison circuit (C), 14 is an AND circuit, 3 is a processor address bus, and 4 is a data bus.

In the same way as explained in (a), if the processor 1 is a processor dedicated to system control, the flag register (F'') 22 is turned on in advance.At this time, in the processor 1, the present invention When an input/output instruction is executed, the input/output processing unit (IOC)
2, the processor address is sent along with the conventional input/output device number, this address is set in the processor address register (PAR) 21, and is sent to the processor address bus 3 through the AND circuit 25.
The forwarding destination prosensor address is sent. At the same time, the data to be transferred is sent to the data bus 4 through the AND circuit 26.

In a plurality of processors 1 connected to the processor address bus 3 and the data bus 4, a processor identification register (PRR) 11 provided in each processor 1 is assigned to the processor on the processor address bus 3. 1 number, and compare it with the value of ProSensor device number setting circuit (PND) 12 and comparison circuit (C).
13, and if a match is found, it is determined that the own processor has been selected, and one input/output process is performed by controlling the transfer data on the data bus 4 to be taken in through the AND circuit 14. Data can be transferred from the device to any processor.

Above, we have explained the cases of octopus-leg connection and bus connection in 1), but in the case of octopus-leg connection explained in (b),
If a processor dedicated to system control that can execute the user's output instructions is assigned to any processor of multiple processors, the input/output processing unit with the function described in (b) can be dedicated to the system control. In addition to changing the connection to the processor, it is also necessary to change the connection of the connection path of the octopus leg. In the case of (b), it is also necessary to change the connection of the input/output processing device, and there is a circuit in each processor that identifies whether the data is being transferred to the own processor [11.12 in Figure 2 (b)] .13 equivalent] and connect it to the processor address bus 3.

(gl Effects of the Invention As explained in detail above, according to the present invention, it is possible to specify the number of the processor that transfers data from the input/output device in the input/output command, so the system control processor Data can be transferred to any processor simply by connecting an input/output processing device, making it possible to economically construct an efficient data processing system with little overhead.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the present invention in detail, and FIG. 2 is a block diagram showing one embodiment of the present invention. In the drawing, 1 is a processor, 2 is an input/output processing unit (IOC), 21 is a processor address register (PAR), 22 is a flag register (F),
23 is a decoder, 11 is a processor identification register (
12 is a processor machine number setting circuit (PND
13 is a comparison circuit (C), 3 is a processor address bus, 4 is a data bus, and 5 is a data transfer path.

Claims (1)

[Claims] In a data processing system having multiple processors, an input/output command is provided that can specify a processor number to which data from an input/output device is transferred, and one processor executes an input/output command that specifies the processor address. A data transfer method that is characterized by making it possible to transfer data to other processors.